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WO2018018450A1 - Procédé et système d'application d'une limite de courant à utiliser dans une puce multicœur - Google Patents

Procédé et système d'application d'une limite de courant à utiliser dans une puce multicœur Download PDF

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Publication number
WO2018018450A1
WO2018018450A1 PCT/CN2016/091848 CN2016091848W WO2018018450A1 WO 2018018450 A1 WO2018018450 A1 WO 2018018450A1 CN 2016091848 W CN2016091848 W CN 2016091848W WO 2018018450 A1 WO2018018450 A1 WO 2018018450A1
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WO
WIPO (PCT)
Prior art keywords
current
core
threads
chip
reduced
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2016/091848
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English (en)
Chinese (zh)
Inventor
李媛媛
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to PCT/CN2016/091848 priority Critical patent/WO2018018450A1/fr
Publication of WO2018018450A1 publication Critical patent/WO2018018450A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]

Definitions

  • the present invention relates to the field of electronics, and in particular, to a method and system for applying current limiting in a multi-core chip.
  • Chip English is Chip; Chipset is Chipset.
  • the chip generally refers to the carrier of the integrated circuit, and is also the result of the integrated circuit after being designed, manufactured, packaged, and tested. It is usually an independent whole that can be used immediately.
  • the words "chip” and "integrated circuit” are often mixed. For example, in the common discussion topic, integrated circuit design and chip design say that the chip industry, the integrated circuit industry, and the IC industry are often also meanings. . In fact, these two words are related and different.
  • Integrated circuit entities often exist in the form of chips, because narrowly defined integrated circuits emphasize the circuit itself, such as a phase-shifted oscillator that is simply connected with only five components. When it is still on the drawing, we It can also be called an integrated circuit.
  • this small integrated circuit When we want to use this small integrated circuit for application, it must be a separate piece of real object, or embedded in a larger integrated circuit, relying on the chip to play its role; Focusing on the design and layout of the circuit, the chip emphasizes the integration, production and packaging of the circuit.
  • the generalized integrated circuit when it comes to the industry (different from other industries), can also contain various meanings related to the chip.
  • a method for applying current limitation in a multi-core chip is provided, which solves the shortcomings of the prior art that the current reduction of the multi-core chip cannot be realized.
  • a method of applying current limiting to a multi-core chip comprising the steps of:
  • the method further includes:
  • the reduced thread of the kernel is allocated to run in other kernels.
  • the method further includes:
  • the reduced threads of the kernel are evenly distributed to run in other kernels.
  • an application system for current limiting in a multi-core chip comprising:
  • a detecting unit for detecting the current of each core and the running thread
  • a determining unit configured to determine whether the current of the core exceeds a current threshold
  • the reduction unit if the current of the core exceeds the current threshold, reduces the number of threads of the core.
  • system further includes:
  • An allocation unit that allocates the reduced threads of the kernel to other kernels to run.
  • system further includes:
  • a averaging unit that distributes the reduced threads of the kernel evenly to other cores.
  • the technical solution provided by the specific embodiment of the present invention detects the current of each core and the running thread. If the current of the core exceeds the current threshold, the number of threads of the core is reduced, so that it has the advantage of reducing the current of the chip.
  • FIG. 1 is a flow chart of a method for applying current limiting in a multi-core chip according to the present invention
  • FIG. 2 is a structural diagram of an application system for current limiting in a multi-core chip according to the present invention.
  • FIG. 1 is a flowchart of a method for applying current limitation to a multi-core chip according to a first preferred embodiment of the present invention.
  • the method is implemented by an electronic chip.
  • the method is as shown in FIG. 1 and includes the following steps. step:
  • Step S101 detecting current of each core and running threads
  • Step S102 determining whether the current of the core exceeds a current threshold
  • Step S103 If the current of the core exceeds the current threshold, the number of threads of the kernel is reduced.
  • the technical solution provided by the specific embodiment of the present invention detects the current of each core and the running thread. If the current of the core exceeds the current threshold, the number of threads of the core is reduced, so that it has the advantage of reducing the current of the chip.
  • the foregoing method may further include:
  • the reduced thread of the kernel is allocated to run in other kernels.
  • the foregoing method may further include:
  • the reduced threads of the kernel are evenly distributed to run in other kernels.
  • FIG. 2 is a schematic diagram of an application system for current limiting in a multi-core chip according to a second preferred embodiment of the present invention.
  • the system includes:
  • a detecting unit 201 configured to detect a current of each core and a running thread
  • the determining unit 202 is configured to determine whether the current of the core exceeds a current threshold
  • the reduction unit 203 for the current as the core exceeds the current threshold, reduces the number of threads of the core.
  • the technical solution provided by the specific embodiment of the present invention detects the current of each core and the running thread. If the current of the core exceeds the current threshold, the number of threads of the core is reduced, so that it has the advantage of reducing the current of the chip.
  • the above system may further include:
  • the allocating unit 204 is configured to allocate the reduced thread of the kernel to run in other kernels.
  • the above system may further include:
  • the averaging unit 205 is configured to distribute the reduced threads of the kernel to other kernels for running.
  • Computer readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one location to another.
  • a storage medium may be any available media that can be accessed by a computer.
  • the computer readable medium may include random access memory (Random) Access Memory, RAM), Read-Only Memory (ROM), Electrically Erasable Programmable Read Only Memory (Electrically Erasable Programmable Read-Only Memory, EEPROM), Compact Disc Read-Only Memory, CD-ROM, or other optical disc storage, magnetic storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. Also. Any connection may suitably be a computer readable medium.
  • a disk and a disc include a compact disc (CD), a laser disc, a compact disc, a digital versatile disc (DVD), a floppy disk, and a Blu-ray disc, wherein the disc is usually magnetically copied, and the disc is The laser is used to optically replicate the data. Combinations of the above should also be included within the scope of the computer readable media.

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Sources (AREA)

Abstract

Procédé et système d'application d'une limite de courant à utiliser dans une puce multicœur, le procédé comportant les étapes consistant à: détecter un courant et des fils en cours d'exécution de chaque cœur (S101); déterminer si le courant du cœur dépasse un seuil de courant (S102); si le courant du cœur dépasse le seuil de courant, diminuer le nombre de fils du cœur (S103). Le procédé et le système présentent l'avantage de réduire efficacement le courant.
PCT/CN2016/091848 2016-07-27 2016-07-27 Procédé et système d'application d'une limite de courant à utiliser dans une puce multicœur Ceased WO2018018450A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/CN2016/091848 WO2018018450A1 (fr) 2016-07-27 2016-07-27 Procédé et système d'application d'une limite de courant à utiliser dans une puce multicœur

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2016/091848 WO2018018450A1 (fr) 2016-07-27 2016-07-27 Procédé et système d'application d'une limite de courant à utiliser dans une puce multicœur

Publications (1)

Publication Number Publication Date
WO2018018450A1 true WO2018018450A1 (fr) 2018-02-01

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2016/091848 Ceased WO2018018450A1 (fr) 2016-07-27 2016-07-27 Procédé et système d'application d'une limite de courant à utiliser dans une puce multicœur

Country Status (1)

Country Link
WO (1) WO2018018450A1 (fr)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101076770A (zh) * 2004-09-28 2007-11-21 英特尔公司 根据可用并行数目改变每条指令能量的方法和设备
US20090172423A1 (en) * 2007-12-31 2009-07-02 Justin Song Method, system, and apparatus for rerouting interrupts in a multi-core processor
CN104081315A (zh) * 2011-12-15 2014-10-01 英特尔公司 包括线程合并的用于能效和节能的方法、装置和系统
CN105528330A (zh) * 2014-09-30 2016-04-27 杭州华为数字技术有限公司 负载均衡的方法、装置、丛集和众核处理器
CN106292995A (zh) * 2016-07-27 2017-01-04 李媛媛 电流限制在多核芯片中的应用方法及系统

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101076770A (zh) * 2004-09-28 2007-11-21 英特尔公司 根据可用并行数目改变每条指令能量的方法和设备
US20090172423A1 (en) * 2007-12-31 2009-07-02 Justin Song Method, system, and apparatus for rerouting interrupts in a multi-core processor
CN104081315A (zh) * 2011-12-15 2014-10-01 英特尔公司 包括线程合并的用于能效和节能的方法、装置和系统
CN105528330A (zh) * 2014-09-30 2016-04-27 杭州华为数字技术有限公司 负载均衡的方法、装置、丛集和众核处理器
CN106292995A (zh) * 2016-07-27 2017-01-04 李媛媛 电流限制在多核芯片中的应用方法及系统

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