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WO2018018427A1 - Procédé et système de programmation multitâche basés sur une puce à noyaux multiples - Google Patents

Procédé et système de programmation multitâche basés sur une puce à noyaux multiples Download PDF

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Publication number
WO2018018427A1
WO2018018427A1 PCT/CN2016/091788 CN2016091788W WO2018018427A1 WO 2018018427 A1 WO2018018427 A1 WO 2018018427A1 CN 2016091788 W CN2016091788 W CN 2016091788W WO 2018018427 A1 WO2018018427 A1 WO 2018018427A1
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WO
WIPO (PCT)
Prior art keywords
tasks
core
new
task
new task
Prior art date
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Ceased
Application number
PCT/CN2016/091788
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English (en)
Chinese (zh)
Inventor
张升泽
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
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Individual
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Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to PCT/CN2016/091788 priority Critical patent/WO2018018427A1/fr
Publication of WO2018018427A1 publication Critical patent/WO2018018427A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]

Definitions

  • the present invention relates to the field of electronic chips, and in particular, to a multi-task scheduling method and system based on a multi-core chip.
  • the chip also has its own unique place. In a broad sense, as long as it is a semiconductor wafer manufactured by microfabrication, it can be called a chip, and there is no circuit inside.
  • a semiconductor light source chip for example, a mechanical chip such as a MEMS gyroscope; or a biochip such as a DNA chip.
  • the intersection of the chip and the integrated circuit is on the "circuit on the silicon wafer.”
  • the chipset is a series of interrelated chipsets that are interdependent and can play a bigger role, such as the processor inside the computer and the North-South Bridge chipset, the RF, baseband and power management chipset in the phone. .
  • a multi-core chip-based multi-task scheduling method is provided, which solves the shortcomings of unreasonable task assignment in the prior art.
  • a multi-core chip-based multi-task scheduling method comprising the following steps:
  • the new task is evenly distributed to the core that can receive the new task.
  • the method further includes:
  • the method further includes:
  • the operating frequency of each core is adjusted according to the number of tasks.
  • a multi-core chip-based multi-task scheduling system comprising:
  • An obtaining unit configured to obtain a maximum power of each core in the multicore and a current task number
  • a determining unit configured to determine, according to the maximum power and the current number of tasks, whether the new task can be enabled
  • system further includes:
  • the stop unit is used to stop receiving new external tasks if all cores cannot receive new tasks.
  • system further includes:
  • An adjustment unit for adjusting the operating frequency of each core according to the number of tasks.
  • the technical solution provided by the specific embodiment of the present invention acquires the maximum power of each core in the multi-core and the current number of tasks, and determines whether it can be capable of a new task according to the maximum power and the current number of tasks. If a new task can be received, the new solution is The tasks are evenly distributed to the cores that are able to receive new tasks, so they have the advantage of reasonable task assignment.
  • FIG. 1 is a flowchart of a multi-core chip-based multi-task scheduling method provided by the present invention
  • FIG. 2 is a structural diagram of a multi-core scheduling system based on a multi-core chip according to the present invention.
  • FIG. 1 is a flowchart of a multi-core chip-based multi-task scheduling method according to a first preferred embodiment of the present invention.
  • the method is implemented by an electronic chip.
  • the method is as shown in FIG. 1 and includes the following steps. step:
  • Step S101 Obtain a maximum power of each core in the multi-core and a current task number
  • Step S102 Determine, according to the maximum power and the current number of tasks, whether the new task can be enabled
  • Step S103 if a new task can be received, the new task is evenly distributed to the core capable of receiving the new task.
  • the technical solution provided by the specific embodiment of the present invention acquires the maximum power of each core in the multi-core and the current number of tasks, and determines whether it can be capable of a new task according to the maximum power and the current number of tasks. If a new task can be received, the new solution is The tasks are evenly distributed to the cores that are able to receive new tasks, so they have the advantage of reasonable task assignment.
  • the foregoing method may further include:
  • the foregoing method may further include:
  • the operating frequency of each core is adjusted according to the number of tasks.
  • FIG. 2 is a multi-core chip-based multi-task scheduling system according to a first preferred embodiment of the present invention.
  • the system includes:
  • An obtaining unit 201 configured to acquire a maximum power of each core in the multi-core and a current task number
  • the determining unit 202 is configured to determine, according to the maximum power and the current task number, whether the new task can be enabled;
  • the allocating unit 203 is configured to evenly distribute the new task to the core capable of receiving the new task, as being able to receive the new task.
  • the technical solution provided by the specific embodiment of the present invention acquires the maximum power of each core in the multi-core and the current number of tasks, and determines whether it can be capable of a new task according to the maximum power and the current number of tasks. If a new task can be received, the new solution is The tasks are evenly distributed to the cores that are able to receive new tasks, so they have the advantage of reasonable task assignment.
  • the above system may further include:
  • the stopping unit 204 is configured to stop receiving new external tasks if all cores cannot receive new tasks.
  • the above system may further include:
  • the adjusting unit 205 is configured to adjust an operating frequency of each core according to the number of tasks.
  • Computer readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one location to another.
  • a storage medium may be any available media that can be accessed by a computer.
  • the computer readable medium may include random access memory (Random) Access Memory, RAM), Read-Only Memory (ROM), Electrically Erasable Programmable Read Only Memory (Electrically Erasable Programmable Read-Only Memory, EEPROM), Compact Disc Read-Only Memory, CD-ROM, or other optical disc storage, magnetic storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. Also. Any connection may suitably be a computer readable medium.
  • a disk and a disc include a compact disc (CD), a laser disc, a compact disc, a digital versatile disc (DVD), a floppy disk, and a Blu-ray disc, wherein the disc is usually magnetically copied, and the disc is The laser is used to optically replicate the data. Combinations of the above should also be included within the scope of the computer readable media.

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Sources (AREA)

Abstract

La présente invention concerne un procédé de programmation multitâche basé sur une puce à noyaux multiples. Le procédé comprend les étapes consistant : à acquérir la puissance maximale de chacun d'une pluralité de noyaux et le nombre de tâches actuelles (101) ; à déterminer si une nouvelle tâche peut être reçue par le noyau conformément à la puissance maximale et au nombre de tâches actuelles (102) ; et si une nouvelle tâche peut être reçue par le noyau, à attribuer uniformément de nouvelles tâches aux noyaux susceptibles de recevoir une nouvelle tâche (103). La solution technique offerte par le procédé présente l'avantage d'attribuer raisonnablement des tâches.
PCT/CN2016/091788 2016-07-26 2016-07-26 Procédé et système de programmation multitâche basés sur une puce à noyaux multiples Ceased WO2018018427A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/CN2016/091788 WO2018018427A1 (fr) 2016-07-26 2016-07-26 Procédé et système de programmation multitâche basés sur une puce à noyaux multiples

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2016/091788 WO2018018427A1 (fr) 2016-07-26 2016-07-26 Procédé et système de programmation multitâche basés sur une puce à noyaux multiples

Publications (1)

Publication Number Publication Date
WO2018018427A1 true WO2018018427A1 (fr) 2018-02-01

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PCT/CN2016/091788 Ceased WO2018018427A1 (fr) 2016-07-26 2016-07-26 Procédé et système de programmation multitâche basés sur une puce à noyaux multiples

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WO (1) WO2018018427A1 (fr)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060161923A1 (en) * 2005-01-20 2006-07-20 International Business Machines (Ibm) Corporation Task management in a data processing environment having multiple hardware entities
CN102184125A (zh) * 2011-06-02 2011-09-14 首都师范大学 异构多核环境下基于程序行为在线分析的负载均衡方法
CN102707996A (zh) * 2012-05-15 2012-10-03 江苏中科梦兰电子科技有限公司 一种异构多核处理器上的任务调度方法
CN103870322A (zh) * 2012-12-17 2014-06-18 联发科技股份有限公司 控制任务转移的方法、非暂时性计算机可读介质、异构多核系统
CN106250235A (zh) * 2016-07-26 2016-12-21 张升泽 基于多内核芯片的多任务调度方法及系统

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060161923A1 (en) * 2005-01-20 2006-07-20 International Business Machines (Ibm) Corporation Task management in a data processing environment having multiple hardware entities
CN102184125A (zh) * 2011-06-02 2011-09-14 首都师范大学 异构多核环境下基于程序行为在线分析的负载均衡方法
CN102707996A (zh) * 2012-05-15 2012-10-03 江苏中科梦兰电子科技有限公司 一种异构多核处理器上的任务调度方法
CN103870322A (zh) * 2012-12-17 2014-06-18 联发科技股份有限公司 控制任务转移的方法、非暂时性计算机可读介质、异构多核系统
CN106250235A (zh) * 2016-07-26 2016-12-21 张升泽 基于多内核芯片的多任务调度方法及系统

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