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WO2018014299A1 - Procédé et système de distribution de courant dans une pluralité de cœurs - Google Patents

Procédé et système de distribution de courant dans une pluralité de cœurs Download PDF

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Publication number
WO2018014299A1
WO2018014299A1 PCT/CN2016/090882 CN2016090882W WO2018014299A1 WO 2018014299 A1 WO2018014299 A1 WO 2018014299A1 CN 2016090882 W CN2016090882 W CN 2016090882W WO 2018014299 A1 WO2018014299 A1 WO 2018014299A1
Authority
WO
WIPO (PCT)
Prior art keywords
current
threads
core
execution time
kernel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2016/090882
Other languages
English (en)
Chinese (zh)
Inventor
张升泽
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to PCT/CN2016/090882 priority Critical patent/WO2018014299A1/fr
Publication of WO2018014299A1 publication Critical patent/WO2018014299A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]

Definitions

  • the present invention relates to the field of electronics, and in particular, to a method and system for distributing current in a plurality of cores.
  • Chip English is Chip; Chipset is Chipset.
  • the chip generally refers to the carrier of the integrated circuit, and is also the result of the integrated circuit after being designed, manufactured, packaged, and tested. It is usually an independent whole that can be used immediately.
  • the words "chip” and "integrated circuit” are often mixed. For example, in the common discussion topic, integrated circuit design and chip design say that the chip industry, the integrated circuit industry, and the IC industry are often also meanings. . In fact, these two words are related and different.
  • Integrated circuit entities often exist in the form of chips, because narrowly defined integrated circuits emphasize the circuit itself, such as a phase-shifted oscillator that is simply connected with only five components. When it is still on the drawing, we It can also be called an integrated circuit.
  • this small integrated circuit When we want to use this small integrated circuit for application, it must be a separate piece of real object, or embedded in a larger integrated circuit, relying on the chip to play its role; Focusing on the design and layout of the circuit, the chip emphasizes the integration, production and packaging of the circuit.
  • the generalized integrated circuit when it comes to the industry (different from other industries), can also contain various meanings related to the chip.
  • a method of distributing current in a plurality of cores is provided that addresses the shortcomings of the prior art that cannot achieve distribution of current in multiple cores.
  • a method of distributing current in a plurality of cores comprising the steps of:
  • Each core is assigned a current based on the number of threads and execution time.
  • the method further includes:
  • the method further includes:
  • a distribution system for current flow in a plurality of cores comprising:
  • system further includes:
  • the stop unit is configured to stop allocating threads to the kernel if the current of the core reaches the upper limit.
  • system further includes:
  • An update unit that dynamically updates the thread count table for each core.
  • the technical solution provided by the specific embodiment of the present invention acquires the number of threads allocated by each core, acquires the execution time of each thread, allocates current to each core according to the number of threads and the execution time, so it has multiple currents in implementation.
  • FIG. 1 is a flow chart of a method for allocating current in multiple cores according to the present invention
  • FIG. 2 is a structural diagram of a distribution system for current flowing in a plurality of cores according to the present invention.
  • FIG. 1 is a flowchart of a method for allocating current in multiple cores according to a first preferred embodiment of the present invention.
  • the method is implemented by an electronic chip.
  • the method is as shown in FIG. 1 and includes the following steps. step:
  • Step S101 Obtain a quantity of threads allocated by each kernel
  • Step S102 Obtain an execution time of each thread.
  • Step S103 assigning a current to each core according to the number of threads and the execution time.
  • the technical solution provided by the specific embodiment of the present invention acquires the number of threads allocated by each core, acquires the execution time of each thread, allocates current to each core according to the number of threads and the execution time, so it has multiple currents in implementation.
  • the foregoing method may further include:
  • the foregoing method may further include:
  • FIG. 2 is a distribution system of current in multiple cores according to a second preferred embodiment of the present invention.
  • the system includes:
  • a quantity unit 201 configured to acquire the number of threads allocated by each kernel
  • a time unit 202 configured to acquire an execution time of each thread
  • the allocating unit 203 is configured to allocate a current to each core according to the number of threads and the execution time.
  • the technical solution provided by the specific embodiment of the present invention acquires the number of threads allocated by each core, acquires the execution time of each thread, allocates current to each core according to the number of threads and the execution time, so it has multiple currents in implementation.
  • the above system may further include:
  • the stopping unit 204 is configured to stop allocating threads to the kernel if the current of the core reaches an upper limit.
  • the above system may further include:
  • the updating unit 205 is configured to dynamically update the thread quantity table of each kernel.
  • Computer readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one location to another.
  • a storage medium may be any available media that can be accessed by a computer.
  • the computer readable medium may include random access memory (Random) Access Memory, RAM), Read-Only Memory (ROM), Electrically Erasable Programmable Read Only Memory (Electrically Erasable Programmable Read-Only Memory, EEPROM), Compact Disc Read-Only Memory, CD-ROM, or other optical disc storage, magnetic storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. Also. Any connection may suitably be a computer readable medium.
  • a disk and a disc include a compact disc (CD), a laser disc, a compact disc, a digital versatile disc (DVD), a floppy disk, and a Blu-ray disc, wherein the disc is usually magnetically copied, and the disc is The laser is used to optically replicate the data. Combinations of the above should also be included within the scope of the computer readable media.

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

L'invention concerne un procédé et un système pour distribuer un courant dans une pluralité de cœurs. Le procédé comprend les étapes suivantes consistant : à acquérir le nombre de fils attribués par chaque cœur (S101) ; à acquérir un temps d'exécution de chacun des fils (S102) ; et à distribuer un courant pour chaque cœur en fonction du nombre de fils et du temps d'exécution (S103). Le procédé et le système présentent l'avantage de réaliser la distribution interne d'un courant.
PCT/CN2016/090882 2016-07-21 2016-07-21 Procédé et système de distribution de courant dans une pluralité de cœurs Ceased WO2018014299A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/CN2016/090882 WO2018014299A1 (fr) 2016-07-21 2016-07-21 Procédé et système de distribution de courant dans une pluralité de cœurs

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2016/090882 WO2018014299A1 (fr) 2016-07-21 2016-07-21 Procédé et système de distribution de courant dans une pluralité de cœurs

Publications (1)

Publication Number Publication Date
WO2018014299A1 true WO2018014299A1 (fr) 2018-01-25

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2016/090882 Ceased WO2018014299A1 (fr) 2016-07-21 2016-07-21 Procédé et système de distribution de courant dans une pluralité de cœurs

Country Status (1)

Country Link
WO (1) WO2018014299A1 (fr)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120287831A1 (en) * 2011-05-11 2012-11-15 Qualcomm Incorporated Reducing power consumption in multi-threaded processor mobile devices
CN103502946A (zh) * 2011-04-05 2014-01-08 高通股份有限公司 用于动态控制到便携式计算装置的多核心处理器中的多个核心的电力的方法和系统
CN104204999A (zh) * 2012-03-13 2014-12-10 英特尔公司 用于按照核心的性能状态的方法和装置
CN105760294A (zh) * 2015-01-06 2016-07-13 联发科技股份有限公司 线程延迟的分析方法及装置
CN106155815A (zh) * 2016-07-21 2016-11-23 张升泽 电流在多个内核中的分配方法及系统

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103502946A (zh) * 2011-04-05 2014-01-08 高通股份有限公司 用于动态控制到便携式计算装置的多核心处理器中的多个核心的电力的方法和系统
US20120287831A1 (en) * 2011-05-11 2012-11-15 Qualcomm Incorporated Reducing power consumption in multi-threaded processor mobile devices
CN104204999A (zh) * 2012-03-13 2014-12-10 英特尔公司 用于按照核心的性能状态的方法和装置
CN105760294A (zh) * 2015-01-06 2016-07-13 联发科技股份有限公司 线程延迟的分析方法及装置
CN106155815A (zh) * 2016-07-21 2016-11-23 张升泽 电流在多个内核中的分配方法及系统

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