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WO2018018451A1 - Procédé et système de répartition de puissance dans une puce électronique - Google Patents

Procédé et système de répartition de puissance dans une puce électronique Download PDF

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Publication number
WO2018018451A1
WO2018018451A1 PCT/CN2016/091849 CN2016091849W WO2018018451A1 WO 2018018451 A1 WO2018018451 A1 WO 2018018451A1 CN 2016091849 W CN2016091849 W CN 2016091849W WO 2018018451 A1 WO2018018451 A1 WO 2018018451A1
Authority
WO
WIPO (PCT)
Prior art keywords
power
core
threads
kernel
reduced
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2016/091849
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English (en)
Chinese (zh)
Inventor
李媛媛
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to PCT/CN2016/091849 priority Critical patent/WO2018018451A1/fr
Publication of WO2018018451A1 publication Critical patent/WO2018018451A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present invention relates to the field of electronics, and in particular, to a power distribution method and system in an electronic chip.
  • Chip English is Chip; Chipset is Chipset.
  • the chip generally refers to the carrier of the integrated circuit, and is also the result of the integrated circuit after being designed, manufactured, packaged, and tested. It is usually an independent whole that can be used immediately.
  • the words "chip” and "integrated circuit” are often mixed. For example, in the common discussion topic, integrated circuit design and chip design say that the chip industry, the integrated circuit industry, and the IC industry are often also meanings. . In fact, these two words are related and different.
  • Integrated circuit entities often exist in the form of chips, because narrowly defined integrated circuits emphasize the circuit itself, such as a phase-shifted oscillator that is simply connected with only five components. When it is still on the drawing, we It can also be called an integrated circuit.
  • this small integrated circuit When we want to use this small integrated circuit for application, it must be a separate piece of real object, or embedded in a larger integrated circuit, relying on the chip to play its role; Focusing on the design and layout of the circuit, the chip emphasizes the integration, production and packaging of the circuit.
  • the generalized integrated circuit when it comes to the industry (different from other industries), can also contain various meanings related to the chip.
  • a power distribution method in an electronic chip is provided, which solves the shortcomings of the prior art that power reduction of a multi-core chip cannot be realized.
  • a power distribution method in an electronic chip comprising the steps of:
  • the power of the core exceeds the power threshold, the number of threads in the kernel is reduced.
  • the method further includes:
  • the reduced thread of the kernel is allocated to run in other kernels.
  • the method further includes:
  • the reduced threads of the kernel are evenly distributed to run in other kernels.
  • a power distribution system in an electronic chip comprising:
  • a detecting unit for detecting the power of each core and the running thread
  • a determining unit configured to determine whether the power of the core exceeds a power threshold
  • a reduction unit that, if the power of the core exceeds a power threshold, reduces the number of threads of the core.
  • system further includes:
  • An allocation unit that allocates the reduced threads of the kernel to other kernels to run.
  • system further includes:
  • a averaging unit that distributes the reduced threads of the kernel evenly to other cores.
  • the technical solution provided by the specific embodiment of the present invention detects the power of each core and the running thread. If the power of the core exceeds the power threshold, the number of threads of the core is reduced, so that it has the advantage of reducing the power of the chip.
  • FIG. 1 is a flowchart of a power distribution method in an electronic chip according to the present invention.
  • FIG. 2 is a structural diagram of a power distribution system in an electronic chip according to the present invention.
  • FIG. 1 is a flowchart of a power distribution method in an electronic chip according to a first preferred embodiment of the present invention. The method is implemented by an electronic chip. The method is as shown in FIG. 1 and includes the following steps:
  • Step S101 detecting the power of each core and the running thread
  • Step S102 Determine whether the power of the core exceeds a power threshold.
  • Step S103 If the power of the core exceeds the power threshold, the number of threads of the kernel is reduced.
  • the technical solution provided by the specific embodiment of the present invention detects the power of each core and the running thread. If the power of the core exceeds the power threshold, the number of threads of the core is reduced, so that it has the advantage of reducing the power of the chip.
  • the foregoing method may further include:
  • the reduced thread of the kernel is allocated to run in other kernels.
  • the foregoing method may further include:
  • the reduced threads of the kernel are evenly distributed to run in other kernels.
  • FIG. 2 is a diagram of a power distribution system in an electronic chip according to a second preferred embodiment of the present invention.
  • the system includes:
  • a detecting unit 201 configured to detect power of each core and a running thread
  • the determining unit 202 is configured to determine whether the power of the core exceeds a power threshold
  • the reducing unit 203 is configured to reduce the number of threads of the kernel if the power of the core exceeds a power threshold.
  • the technical solution provided by the specific embodiment of the present invention detects the power of each core and the running thread. If the power of the core exceeds the power threshold, the number of threads of the core is reduced, so that it has the advantage of reducing the power of the chip.
  • the above system may further include:
  • the allocating unit 204 is configured to allocate the reduced thread of the kernel to run in other kernels.
  • the above system may further include:
  • the averaging unit 205 is configured to distribute the reduced threads of the kernel to other kernels for running.
  • Computer readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one location to another.
  • a storage medium may be any available media that can be accessed by a computer.
  • the computer readable medium may include random access memory (Random) Access Memory, RAM), Read-Only Memory (ROM), Electrically Erasable Programmable Read Only Memory (Electrically Erasable Programmable Read-Only Memory, EEPROM), Compact Disc Read-Only Memory, CD-ROM, or other optical disc storage, magnetic storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. Also. Any connection may suitably be a computer readable medium.
  • a disk and a disc include a compact disc (CD), a laser disc, a compact disc, a digital versatile disc (DVD), a floppy disk, and a Blu-ray disc, wherein the disc is usually magnetically copied, and the disc is The laser is used to optically replicate the data. Combinations of the above should also be included within the scope of the computer readable media.

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Sources (AREA)

Abstract

L'invention concerne un procédé et un système de répartition de puissance dans une puce électronique, qui consiste: à détecter une puissance et des fils de chaque noyau en cours d'exécution (S101); à déterminer si la puissance du noyau dépasse un seuil de puissance (S102); si la puissance du noyau dépasse le seuil de puissance, à diminuer alors le nombre de fils du noyau (S103). Le procédé et le système de l'invention présentent l'avantage de réduire efficacement la puissance.
PCT/CN2016/091849 2016-07-27 2016-07-27 Procédé et système de répartition de puissance dans une puce électronique Ceased WO2018018451A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/CN2016/091849 WO2018018451A1 (fr) 2016-07-27 2016-07-27 Procédé et système de répartition de puissance dans une puce électronique

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2016/091849 WO2018018451A1 (fr) 2016-07-27 2016-07-27 Procédé et système de répartition de puissance dans une puce électronique

Publications (1)

Publication Number Publication Date
WO2018018451A1 true WO2018018451A1 (fr) 2018-02-01

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2016/091849 Ceased WO2018018451A1 (fr) 2016-07-27 2016-07-27 Procédé et système de répartition de puissance dans une puce électronique

Country Status (1)

Country Link
WO (1) WO2018018451A1 (fr)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101076770A (zh) * 2004-09-28 2007-11-21 英特尔公司 根据可用并行数目改变每条指令能量的方法和设备
US7962771B2 (en) * 2007-12-31 2011-06-14 Intel Corporation Method, system, and apparatus for rerouting interrupts in a multi-core processor
CN106201726A (zh) * 2016-07-26 2016-12-07 张升泽 多内核芯片线程分配方法及系统
CN106201725A (zh) * 2016-07-21 2016-12-07 张升泽 多核芯片的功率实现方法及系统
CN106227602A (zh) * 2016-07-26 2016-12-14 张升泽 负载在多核芯片之间的分配方法及系统
CN106227603A (zh) * 2016-07-25 2016-12-14 张升泽 多个内核芯片的功率计算方法及系统

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101076770A (zh) * 2004-09-28 2007-11-21 英特尔公司 根据可用并行数目改变每条指令能量的方法和设备
US7962771B2 (en) * 2007-12-31 2011-06-14 Intel Corporation Method, system, and apparatus for rerouting interrupts in a multi-core processor
CN106201725A (zh) * 2016-07-21 2016-12-07 张升泽 多核芯片的功率实现方法及系统
CN106227603A (zh) * 2016-07-25 2016-12-14 张升泽 多个内核芯片的功率计算方法及系统
CN106201726A (zh) * 2016-07-26 2016-12-07 张升泽 多内核芯片线程分配方法及系统
CN106227602A (zh) * 2016-07-26 2016-12-14 张升泽 负载在多核芯片之间的分配方法及系统

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