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WO2018018492A1 - Procédé et système d'attribution d'un courant dans une pluralité d'intervalles à l'intérieur d'une puce multicœur - Google Patents

Procédé et système d'attribution d'un courant dans une pluralité d'intervalles à l'intérieur d'une puce multicœur Download PDF

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Publication number
WO2018018492A1
WO2018018492A1 PCT/CN2016/092036 CN2016092036W WO2018018492A1 WO 2018018492 A1 WO2018018492 A1 WO 2018018492A1 CN 2016092036 W CN2016092036 W CN 2016092036W WO 2018018492 A1 WO2018018492 A1 WO 2018018492A1
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WO
WIPO (PCT)
Prior art keywords
current
current value
interval
core
intervals
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Ceased
Application number
PCT/CN2016/092036
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English (en)
Chinese (zh)
Inventor
张升泽
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
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Individual
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Filing date
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Application filed by Individual filed Critical Individual
Priority to PCT/CN2016/092036 priority Critical patent/WO2018018492A1/fr
Publication of WO2018018492A1 publication Critical patent/WO2018018492A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs

Definitions

  • the present invention relates to the field of electronics, and in particular, to a multi-interval allocation method and system for currents inside a multi-core chip.
  • Chip English is Chip; Chipset is Chipset.
  • the chip generally refers to the carrier of the integrated circuit, and is also the result of the integrated circuit after being designed, manufactured, packaged, and tested. It is usually an independent whole that can be used immediately.
  • the words "chip” and "integrated circuit” are often mixed. For example, in the common discussion topic, integrated circuit design and chip design say that the chip industry, the integrated circuit industry, and the IC industry are often also meanings. . In fact, these two words are related and different.
  • Integrated circuit entities often exist in the form of chips, because narrowly defined integrated circuits emphasize the circuit itself, such as a phase-shifted oscillator that is simply connected with only five components. When it is still on the drawing, we It can also be called an integrated circuit.
  • this small integrated circuit When we want to use this small integrated circuit for application, it must be a separate piece of real object, or embedded in a larger integrated circuit, relying on the chip to play its role; Focusing on the design and layout of the circuit, the chip emphasizes the integration, production and packaging of the circuit.
  • the generalized integrated circuit when it comes to the industry (different from other industries), can also contain various meanings related to the chip.
  • a multi-interval allocation method for currents in a multi-core chip is provided, which solves the shortcomings of the prior art that cannot implement effective current control of a multi-core chip.
  • a multi-interval allocation method for currents within a multi-core chip comprising the steps of:
  • the method further includes:
  • the method further includes:
  • a multi-interval distribution system for current flow inside a multi-core chip comprising:
  • a dividing unit configured to divide the number of threads into a plurality of thread number intervals, and divide the current value into a plurality of current value intervals according to the current value
  • the current unit is configured to acquire the number of threads corresponding to the current core, obtain a corresponding thread number interval according to the number of the threads, and a current value interval corresponding to the thread number interval, and adjust the current of the core to the current value interval.
  • system further includes:
  • the adjusting unit is configured to acquire a change value of the number of threads, and adjust the current of the core according to the change value.
  • system further includes:
  • a storage unit for recording an operating current value of the core.
  • the technical solution provided by the specific embodiment of the present invention divides the number of threads into a plurality of thread number intervals, divides the current value into a plurality of current value intervals according to the current value, and establishes a mapping relationship between the plurality of current value intervals and the thread number interval. Obtaining the number of threads corresponding to the current core, obtaining a corresponding thread number interval according to the number of the threads, and a current value interval corresponding to the thread number interval, and adjusting the current of the core to the current value interval, so that the current is performed on the current.
  • FIG. 1 is a flow chart of a multi-interval allocation method for currents in a multi-core chip according to the present invention
  • FIG. 2 is a structural diagram of a multi-interval distribution system in which a current is inside a multi-core chip according to the present invention.
  • FIG. 1 is a flowchart of a method for multi-interval allocation of current in a multi-core chip according to a first preferred embodiment of the present invention.
  • the method is implemented by an electronic chip, and the method is as shown in FIG. 1 .
  • Step S101 dividing the number of threads into a plurality of thread number intervals, and dividing the current value into a plurality of current value intervals according to the magnitude of the current value;
  • Step S102 establishing a mapping relationship between a plurality of current value intervals and a thread number interval
  • step S103 the number of threads corresponding to the current core is obtained, and the corresponding thread number interval and the current value interval corresponding to the thread number interval are obtained according to the number of the threads, and the current of the core is adjusted to the current value interval.
  • the technical solution provided by the specific embodiment of the present invention divides the number of threads into a plurality of thread number intervals, divides the current value into a plurality of current value intervals according to the current value, and establishes a mapping relationship between the plurality of current value intervals and the thread number interval. Obtaining the number of threads corresponding to the current core, obtaining a corresponding thread number interval according to the number of the threads, and a current value interval corresponding to the thread number interval, and adjusting the current of the core to the current value interval, so that the current is performed on the current.
  • the foregoing method may further include:
  • the foregoing method may further include:
  • FIG. 2 is a multi-interval distribution system of a current inside a multi-core chip according to a second preferred embodiment of the present invention.
  • the system includes:
  • the dividing unit 201 is configured to divide the number of threads into a plurality of thread number intervals, and divide the current value into a plurality of current value intervals according to the magnitude of the current value;
  • the establishing unit 202 is configured to establish a mapping relationship between the plurality of current value intervals and the thread number interval;
  • the current unit 203 is configured to acquire the number of threads corresponding to the current core, obtain a corresponding thread number interval according to the number of threads, and a current value interval corresponding to the thread number interval, and adjust the current of the core to the current value interval.
  • the technical solution provided by the specific embodiment of the present invention divides the number of threads into a plurality of thread number intervals, divides the current value into a plurality of current value intervals according to the current value, and establishes a mapping relationship between the plurality of current value intervals and the thread number interval. Obtaining the number of threads corresponding to the current core, obtaining a corresponding thread number interval according to the number of the threads, and a current value interval corresponding to the thread number interval, and adjusting the current of the core to the current value interval, so that the current is performed on the current.
  • the above system may further include:
  • the adjusting unit 204 is configured to acquire a change value of the number of threads, and adjust a current of the core according to the change value.
  • the above system may further include:
  • the storage unit 205 is configured to record an operating current value of the core.
  • Computer readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one location to another.
  • a storage medium may be any available media that can be accessed by a computer.
  • the computer readable medium may include random access memory (Random) Access Memory, RAM), Read-Only Memory (ROM), Electrically Erasable Programmable Read Only Memory (Electrically Erasable Programmable Read-Only Memory, EEPROM), Compact Disc Read-Only Memory, CD-ROM, or other optical disc storage, magnetic storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. Also. Any connection may suitably be a computer readable medium.
  • a disk and a disc include a compact disc (CD), a laser disc, a compact disc, a digital versatile disc (DVD), a floppy disk, and a Blu-ray disc, wherein the disc is usually magnetically copied, and the disc is The laser is used to optically replicate the data. Combinations of the above should also be included within the scope of the computer readable media.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

L'invention concerne un procédé et un système d'attribution d'un courant dans une pluralité d'intervalles à l'intérieur d'une puce multicœur. Le procédé comprend les étapes suivantes consistant à : diviser une quantité de fils en une pluralité d'intervalles de quantité de fils et diviser des valeurs de courant en une pluralité d'intervalles de valeurs de courant en fonction de l'intensité des valeurs de courant (S101) ; établir une relation de correspondance entre la pluralité d'intervalles de valeurs de courant et les intervalles de quantité de fils (S102) ; et obtenir la quantité de fils correspondant à un cœur actuel, obtenir en fonction de la quantité des fils l'intervalle de quantité de fils lui correspondant et l'intervalle de valeurs de courant correspondant à l'intervalle de quantité de fils et ajuster le courant du cœur à l'intervalle de valeurs de courant (S103). L'invention présente l'avantage de réguler efficacement le courant.
PCT/CN2016/092036 2016-07-28 2016-07-28 Procédé et système d'attribution d'un courant dans une pluralité d'intervalles à l'intérieur d'une puce multicœur Ceased WO2018018492A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/CN2016/092036 WO2018018492A1 (fr) 2016-07-28 2016-07-28 Procédé et système d'attribution d'un courant dans une pluralité d'intervalles à l'intérieur d'une puce multicœur

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2016/092036 WO2018018492A1 (fr) 2016-07-28 2016-07-28 Procédé et système d'attribution d'un courant dans une pluralité d'intervalles à l'intérieur d'une puce multicœur

Publications (1)

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WO2018018492A1 true WO2018018492A1 (fr) 2018-02-01

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PCT/CN2016/092036 Ceased WO2018018492A1 (fr) 2016-07-28 2016-07-28 Procédé et système d'attribution d'un courant dans une pluralité d'intervalles à l'intérieur d'une puce multicœur

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Country Link
WO (1) WO2018018492A1 (fr)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1534463A (zh) * 2003-02-20 2004-10-06 ���ǵ�����ʽ���� 同步多线程处理器电路以及计算机程序产品及运行方法
CN104583900A (zh) * 2012-10-04 2015-04-29 英特尔公司 在处理器的异质核之间动态切换工作载荷
US9213577B2 (en) * 2013-10-04 2015-12-15 Utah State University Sustainable differentially reliable architecture for dark silicon
US9354943B2 (en) * 2014-03-19 2016-05-31 International Business Machines Corporation Power management for multi-core processing systems
CN106293935A (zh) * 2016-07-28 2017-01-04 张升泽 电流在多核芯片内部的多区间分配方法及系统

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1534463A (zh) * 2003-02-20 2004-10-06 ���ǵ�����ʽ���� 同步多线程处理器电路以及计算机程序产品及运行方法
CN104583900A (zh) * 2012-10-04 2015-04-29 英特尔公司 在处理器的异质核之间动态切换工作载荷
US9213577B2 (en) * 2013-10-04 2015-12-15 Utah State University Sustainable differentially reliable architecture for dark silicon
US9354943B2 (en) * 2014-03-19 2016-05-31 International Business Machines Corporation Power management for multi-core processing systems
CN106293935A (zh) * 2016-07-28 2017-01-04 张升泽 电流在多核芯片内部的多区间分配方法及系统

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