TWI829169B - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

A semiconductor device and a manufacturing thereof. The semiconductor device includes a substrate, a metal oxide semiconductor layer, a first gate dielectric layer, a gate electrode, an interlayer dielectric layer, a first conductive oxide layer, a first electrode, and a second electrode. The first gate dielectric layer is located above the metal oxide semiconductor layer. The gate is located above the first gate dielectric layer and overlapped with the metal oxide semiconductor layer. The interlayer dielectric layer is located above the gate. The interlayer dielectric layer has a first contact hole. The first contact hole is laterally separated from the metal oxide semiconductor layer. The first conductive oxide layer is located under the first contact hole. The first electrode fills the first contact hole and is electrically connected to the metal oxide semiconductor layer through the first conductive oxide layer.

Description

Semiconductor device and manufacturing method thereof

The present invention relates to a semiconductor device and a manufacturing method thereof.

At present, common thin film transistors usually use amorphous silicon semiconductors as channels. Amorphous silicon semiconductors have been widely used in various thin film transistors due to their simple manufacturing process and low cost.

With the advancement of display technology, the resolution of display panels is increasing year by year. In order to shrink thin film transistors in pixel circuits, many manufacturers are committed to developing new semiconductor materials, such as metal oxide semiconductor materials. Metal oxide semiconductor materials have the advantage of high carrier mobility and are therefore beneficial to reducing the size of semiconductor devices.

The present invention provides a semiconductor device and a manufacturing method thereof, which can improve the problem of poor contact between electrodes and metal oxide semiconductor layers.

At least one embodiment of the present invention provides a semiconductor device. The semiconductor device includes a substrate, a metal oxide semiconductor layer, a first gate dielectric layer, a gate electrode, an interlayer dielectric layer, a first conductive oxide layer, a first electrode, and a second electrode. A metal oxide semiconductor layer is located on the substrate. The first gate dielectric layer is located on the metal oxide semiconductor layer. The gate is located on the first gate dielectric layer and overlaps the metal oxide semiconductor layer in a normal direction of the upper surface of the substrate. The interlayer dielectric layer is located above the gate. The interlayer dielectric layer has a first contact hole and a second contact hole. The first contact hole is laterally separated from the metal oxide semiconductor layer. The first conductive oxide layer is located under the first contact hole and connected to the metal oxide semiconductor layer. The first electrode fills the first contact hole and is electrically connected to the metal oxide semiconductor layer through the first conductive oxide layer. The second electrode fills the second contact hole and is electrically connected to the metal oxide semiconductor layer.

At least one embodiment of the present invention provides a method for manufacturing a semiconductor device, including: forming a metal oxide semiconductor layer, a first conductive oxide layer and a first gate dielectric layer on a substrate, wherein the first conductive oxide layer is connected to a metal oxide semiconductor layer, and a first gate dielectric layer is located on the metal oxide semiconductor layer; a gate electrode is formed on the first gate dielectric layer, and the gate electrode overlaps in the normal direction of the upper surface of the substrate A metal oxide semiconductor layer; forming an interlayer dielectric layer on the gate; forming a first contact hole and a second contact hole in the interlayer dielectric layer, and the first conductive oxide layer is located below the first contact hole, wherein the A contact hole is laterally separated from the metal oxide semiconductor layer; a first electrode is formed in the first contact hole, and the first electrode is electrically connected to the metal oxide semiconductor layer through the first conductive oxide layer; a second electrode is formed In the second contact hole, the second electrode is electrically connected to the metal oxide semiconductor layer.

FIG. 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 1 , the semiconductor device 10A includes a substrate 100, a metal oxide semiconductor layer OS, a first gate dielectric layer 120, a gate electrode G, an interlayer dielectric layer 140, a first conductive oxide layer T1, a first electrode S, and Second electrode D. In this embodiment, the semiconductor device 10A further includes a buffer layer 110, a second conductive oxide layer T2, and a second gate dielectric layer 130.

The material of the substrate 100 may be glass, quartz, organic polymer, opaque/reflective material (such as conductive material, metal, wafer, ceramic or other applicable materials) or other applicable materials. If conductive materials or metals are used, an insulating layer (not shown) is covered on the substrate 100 to avoid short circuit problems. In some embodiments, the substrate 100 is a flexible substrate, and the material of the substrate 100 is, for example, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyester (polyester, PES), polymethylmethacrylate (PMMA), polycarbonate (PC), polyimide (PI) or metal foil (Metal Foil) or other flexible materials . The buffer layer 110 is located on the substrate 100. The buffer layer 110 has a single-layer or multi-layer structure, and the material of the buffer layer 110 may include silicon oxide, silicon oxynitride, or other suitable materials or stacked layers of the above materials. In this embodiment, the buffer layer 110 includes a stack of a silicon nitride layer 112 and a silicon oxide layer 114 .

The metal oxide semiconductor layer OS is located on the substrate 100 . In this embodiment, the metal oxide semiconductor layer OS is directly formed on the buffer layer 110 . The materials of the metal oxide semiconductor layer OS include indium gallium tin zinc oxide (IGTZO) or indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), aluminum zinc tin oxide (AZTO), and indium tungsten zinc oxide (IWZO). Quaternary metal compounds or oxides composed of ternary metals including any three of gallium (Ga), zinc (Zn), indium (In), tin (Sn), aluminum (Al), and tungsten (W), or Lanthanide rare earth doped metal oxides (such as Ln-IZO).

The first gate dielectric layer 120 is located on the metal oxide semiconductor layer OS. In this embodiment, the first gate dielectric layer 120 is directly formed on the metal oxide semiconductor layer OS. The first gate dielectric layer 120 has a first opening O1 and a second opening O2 overlapping the metal oxide semiconductor layer OS. In some embodiments, the material of the first gate dielectric layer 120 includes silicon oxide, silicon oxynitride, hafnium oxide or other suitable materials or stacked layers of the above materials.

The first conductive oxide layer T1 and the second conductive oxide layer T2 are located on the first gate dielectric layer 120 and connected to the metal oxide semiconductor layer OS. The first conductive oxide layer T1 and the second conductive oxide layer T2 are respectively filled in the first opening O1 and the second opening O2 and contact the upper surface of the metal oxide semiconductor layer OS. In some embodiments, the materials of the first conductive oxide layer T1 and the second conductive oxide layer T2 include transparent conductive oxides, such as indium tin oxide, indium zinc oxide, aluminum zinc oxide, or at least two of the above. of stacked layers.

In some embodiments, the work functions of the first conductive oxide layer T1 and the second conductive oxide layer T2 are close to the work function of the metal oxide semiconductor layer OS. For example, the energy barriers between the first conductive oxide layer T1 and the metal oxide semiconductor layer OS and between the second conductive oxide layer T2 and the metal oxide semiconductor layer OS are larger than those between the metal electrode (such as a copper electrode) and the metal oxide semiconductor layer OS. The energy barrier between the oxide semiconductor layers OS is low. In some embodiments, there is an ohmic contact between the first conductive oxide layer T1 and the metal oxide semiconductor layer OS and between the second conductive oxide layer T2 and the metal oxide semiconductor layer OS.

The second gate dielectric layer 130 is located on the first gate dielectric layer 120 and covers the first conductive oxide layer T1 and the second conductive oxide layer T2. The first conductive oxide layer T1 and the second conductive oxide layer T2 are located between the second gate dielectric layer 130 and the first gate dielectric layer 110 . In some embodiments, the material of the second gate dielectric layer 130 includes silicon oxide, silicon oxynitride, hafnium oxide or other suitable materials or stacked layers of the above materials.

The gate G is located on the first gate dielectric layer 120 . In this embodiment, the gate G is located on the second gate dielectric layer 130 . The gate G overlaps the metal oxide semiconductor layer OS in the normal direction ND of the upper surface of the substrate 100 . In some embodiments, the material of the gate G may include metals, such as chromium (Cr), gold (Au), silver (Ag), copper (Cu), tin (Sn), lead (Pb), and hafnium (Hf). , tungsten (W), molybdenum (Mo), neodymium (Nd), titanium (Ti), tantalum (Ta), aluminum (Al), zinc (Zn) or alloys of any combination of the above metals or the above metals and/or alloys laminated, but the present invention is not limited to this. The gate G may also use other conductive materials, such as metal nitrides, metal oxides, metal oxynitrides, stacked layers of metal and other conductive materials, or other materials with conductive properties.

The interlayer dielectric layer 140 is located on the gate G and the second gate dielectric layer 130 . In some embodiments, the material of the interlayer dielectric layer 140 includes silicon nitride, silicon oxide, silicon oxynitride, hafnium oxide or other suitable materials or stacked layers of the above materials.

The interlayer dielectric layer 140 has a first contact hole V1 and a second contact hole V2. In this embodiment, the first contact hole V1 and the second contact hole V2 penetrate the interlayer dielectric layer 140 and the second gate dielectric layer 130 . The first contact hole V1 and the second contact hole V2 are laterally separated from the metal oxide semiconductor layer OS. In other words, the first contact hole V1 and the second contact hole V2 do not overlap the metal oxide semiconductor layer OS in the normal direction ND. The first conductive oxide layer T1 and the second conductive oxide layer T2 are respectively located under the first contact hole V1 and the second contact hole V2. The first conductive oxide layer T1 extends from the first contact hole V1 to the first opening O1, and the second conductive oxide layer T2 extends from the second contact hole V2 to the second opening O2.

The first electrode S and the second electrode D fill the first contact hole V1 and the second contact hole V2 respectively. The first electrode S is electrically connected to the metal oxide semiconductor layer OS through the first conductive oxide layer T1. The second electrode D is electrically connected to the metal oxide semiconductor layer OS through the second conductive oxide layer T2. One of the first electrode S and the second electrode D is a drain, and the other is a source.

In some embodiments, the first portion T1a of the first conductive oxide layer T1 extends from the first opening O1 toward the gate G, and the second portion T2a of the second conductive oxide layer T2 extends from the second opening O2 toward the gate G. extend. The first part T1a and the second part T2a overlap the metal oxide semiconductor layer OS in the normal direction ND, thereby shielding the lateral electric field between the gate G and the first electrode S or the gate G and the second electrode D, and thereby The hot carrier effect of the semiconductor device 10A is reduced. In some embodiments, the horizontal distance H1a between the first conductive oxide layer T1 and the gate G is smaller than the horizontal distance H1b between the first opening O1 and the gate G. In some embodiments, the horizontal distance H2b between the second conductive oxide layer T1 and the gate G is smaller than the horizontal distance H2b between the second opening O2 and the gate G.

In some embodiments, the materials of the first electrode S and the second electrode D may include metals, such as chromium, gold, silver, copper, tin, lead, hafnium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc or An alloy of any combination of the above metals or a laminate of the above metals and/or alloys. In this embodiment, compared with the metal oxide semiconductor layer OS, the first conductive oxide layer T1 and the second conductive oxide layer T2 are less likely to react with the first electrode S and the second electrode D, thereby avoiding There is a problem of poor electrical connection between the first electrode S and the metal oxide semiconductor layer OS and between the second electrode D and the metal oxide semiconductor layer OS. For example, if the first electrode S and the second electrode D directly contact the metal oxide semiconductor layer OS, the oxygen element in the metal oxide semiconductor layer OS may diffuse into the first electrode S and the second electrode D, resulting in The first electrode S and the second electrode D are oxidized; or the metal elements in the first electrode S and the second electrode D may diffuse into the metal oxide semiconductor layer OS, causing the contact between the first electrode S and the metal oxide semiconductor layer OS to Gaps appear at the interface and the interface between the second electrode D and the metal oxide semiconductor layer OS.

Based on the above, the first conductive oxide layer T1 and the second conductive oxide layer T2 can avoid electrical connections between the first electrode S and the metal oxide semiconductor layer OS and between the second electrode D and the metal oxide semiconductor layer OS. Bad question.

2A to 2E are schematic cross-sectional views of the manufacturing method of the semiconductor device of FIG. 1 .

Referring to FIGS. 2A to 2C , a metal oxide semiconductor layer OS, a first conductive oxide layer T1 and a second conductive oxide layer T2 are formed on the substrate 100 .

Please refer to FIG. 2A first. A metal oxide semiconductor layer OS is formed on the substrate 100. In this embodiment, a metal oxide semiconductor layer OS is formed on the buffer layer 110 .

Referring to FIG. 2B , a first gate dielectric layer 120 is formed on the metal oxide semiconductor layer OS. The first gate dielectric layer 120 has a first opening O1 and a second opening O2 that overlap and expose the metal oxide semiconductor layer OS. In some embodiments, a method of forming the first gate dielectric layer 120 includes a photolithography etching process.

Referring to FIG. 2C, a first conductive oxide layer T1 and a second conductive oxide layer T2 are formed on the first gate dielectric layer 120, and the first conductive oxide layer T1 and the second conductive oxide layer T2 are respectively located on the first gate dielectric layer 120. An opening O1 and a second opening O2 are provided to connect the upper surface of the metal oxide semiconductor layer OS. Part of the first conductive oxide layer T1 and part of the second conductive oxide layer T2 overlap the metal oxide semiconductor layer OS, and another part of the first conductive oxide layer T1 and another part of the second conductive oxide layer T2 do not overlap the metal oxide layer OS. physical semiconductor layer OS.

In some examples, a method of forming the first conductive oxide layer T1 and the second conductive oxide layer T2 includes: forming a conductive oxide layer (not shown) blanketing the first gate dielectric layer 120; A patterned photoresist (not shown) is formed on the oxide layer; the conductive oxide layer is etched using the patterned photoresist as a mask to form a first conductive oxide layer T1 and a second conductive oxide layer that are separated from each other. T2; Finally, remove the patterned photoresist. In other words, in some embodiments, the first conductive oxide layer T1 and the second conductive oxide layer T2 are the same patterned film layer, and the first conductive oxide layer T1 and the second conductive oxide layer T2 are formed at the same time. .

Referring to FIG. 2D, a second gate dielectric layer 130 is formed on the first conductive oxide layer T1 and the second conductive oxide layer T2. A gate G is formed on the first gate dielectric layer 120 . In this embodiment, the gate G is directly formed on the second gate dielectric layer 130 , and the gate G overlaps the metal oxide semiconductor layer OS in the normal direction ND of the upper surface of the substrate 100 .

In some embodiments, the gate G is used as a mask to perform a doping process on the metal oxide semiconductor layer OS to form a source region, a drain region, and a source region and a drain region in the metal oxide semiconductor layer OS. The channel region between the electrode regions, where the channel region overlaps the gate G, and the source region and the drain region are doped to have a lower resistivity than the channel region. In some embodiments, the doping process includes, for example, a hydrogen plasma process.

Referring to FIG. 2E, an interlayer dielectric layer 140 is formed on the gate G and the second gate dielectric layer 130. A first contact hole V1 and a second contact hole V2 are formed in the interlayer dielectric layer 140 . In this embodiment, the first contact hole V1 and the second contact hole V2 extend through the interlayer dielectric layer 140 and the second gate dielectric layer 130 and expose the upper surface of the first conductive oxide layer T1 and the second gate dielectric layer T1 respectively. The upper surface of the second conductive oxide layer T2. In other words, the first conductive oxide layer T1 and the second conductive oxide layer T2 are respectively located under the first contact hole V1 and the second contact hole V2. In some embodiments, the method of forming the first contact hole V1 and the second contact hole V2 includes: forming a patterned photoresist (not shown) on the interlayer dielectric layer 140; using the patterned photoresist as a mask. The interlayer dielectric layer 140 and the second gate dielectric layer 130 are etched; finally, the patterned photoresist is removed. Since the first contact hole V1 and the second contact hole V2 are laterally separated from the metal oxide semiconductor layer OS, the etching process when etching the interlayer dielectric layer 140 and the second gate dielectric layer 130 will not damage the metal oxide semiconductor layer OS. , thereby improving the process yield of semiconductor devices.

Finally, please return to FIG. 1 . A first electrode S is formed in the first contact hole V1 , and the first electrode S is electrically connected to the metal oxide semiconductor layer OS through the first conductive oxide layer T1 . A second electrode D is formed in the second contact hole V2, and the second electrode D is electrically connected to the metal oxide semiconductor layer OS through the second conductive oxide layer T2. At this point, the semiconductor device 10A is substantially completed.

In some examples, the method of forming the first electrode S and the second electrode D includes: forming a conductive layer (not shown) blanketed on the interlayer dielectric layer 140; forming a patterned photoresist (not shown) on the conductive layer. (drawn); use the patterned photoresist as a mask to etch the conductive layer to form a first electrode S and a second electrode D that are separated from each other; finally, remove the patterned photoresist. In other words, in some embodiments, the first electrode S and the second electrode D are the same patterned film layer, and the first electrode S and the second electrode D are formed at the same time.

FIG. 3 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. It must be noted here that the embodiment of FIG. 3 follows the component numbers and part of the content of the embodiment of FIG. 1 , where the same or similar numbers are used to represent the same or similar elements, and descriptions of the same technical content are omitted. For descriptions of omitted parts, reference may be made to the foregoing embodiments and will not be described again here.

The main difference between the semiconductor device 10B of FIG. 3 and the semiconductor device 10A of FIG. 1 is that the semiconductor device 10B further includes an auxiliary conductive oxide layer T3.

Referring to FIG. 3 , the auxiliary conductive oxide layer T3 is located between the metal oxide semiconductor layer OS and the substrate 100 . The resistivity of the auxiliary conductive oxide layer T3 is lower than the resistivity of the metal oxide semiconductor layer OS. By providing the auxiliary conductive oxide layer T3, the current of the semiconductor device 10B can be increased.

In some embodiments, the material of the auxiliary conductive oxide layer T3 includes a transparent conductive oxide, such as indium tin oxide, indium zinc oxide, aluminum zinc oxide, or a stacked layer of at least two of the above.

FIG. 4 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. It must be noted here that the embodiment of FIG. 4 follows the component numbers and part of the content of the embodiment of FIG. 1 , where the same or similar numbers are used to represent the same or similar elements, and the description of the same technical content is omitted. For descriptions of omitted parts, reference may be made to the foregoing embodiments and will not be described again here.

The main difference between the semiconductor device 10C of FIG. 4 and the semiconductor device 10A of FIG. 1 is that the metal oxide semiconductor layer OS of the semiconductor device 10C contacts the upper surface of the first conductive oxide layer T1 and the upper surface of the second conductive oxide layer T2 .

Referring to FIG. 4 , the first conductive oxide layer T1 and the second conductive oxide layer T2 are located on the buffer layer 110 . The metal oxide semiconductor layer OS is located on the first conductive oxide layer T1 and the second conductive oxide layer T2. In some embodiments, the first conductive oxide layer T1 and the second conductive oxide layer T2 extend below the gate electrode G. In other words, part of the first conductive oxide layer T1 and part of the second conductive oxide layer T2 are located between the substrate 100 and the gate G in the normal direction ND.

The metal oxide semiconductor layer OS extends along the side of the first conductive oxide layer T1 to the upper surface of the first conductive oxide layer T1, and the metal oxide semiconductor layer OS has a break at the side of the first conductive oxide layer T1. Poor GP1. The gate G overlaps the gap GP1 of the metal oxide semiconductor layer OS in the normal direction ND of the upper surface of the substrate 100, thereby reducing the impact of the lateral electric field between the gate G and the first electrode S on the metal oxide semiconductor. The impact of layer OS.

The metal oxide semiconductor layer OS extends along the side of the second conductive oxide layer T2 to the upper surface of the second conductive oxide layer T2, and the metal oxide semiconductor layer OS has a break at the side of the second conductive oxide layer T2. Poor GP2. The gate G overlaps the gap GP2 of the metal oxide semiconductor layer OS in the normal direction ND of the upper surface of the substrate 100, thereby reducing the impact of the lateral electric field between the gate G and the second electrode D on the metal oxide semiconductor. The impact of layer OS.

In this embodiment, the gate G is formed on the first gate dielectric layer 120 , and the first contact hole V1 and the second contact hole V2 penetrate the interlayer dielectric layer 140 and the first gate dielectric layer 120 . The first contact hole V1 and the second contact hole V2 are laterally separated from the metal oxide semiconductor layer OS. In other words, the first contact hole V1 and the second contact hole V2 do not overlap the metal oxide semiconductor layer OS in the normal direction ND.

5A to 5D are schematic cross-sectional views of the manufacturing method of the semiconductor device of FIG. 4 .

Referring to FIGS. 5A and 5B , a metal oxide semiconductor layer OS, a first conductive oxide layer T1 and a second conductive oxide layer T2 are formed on the substrate 100 .

Referring to FIG. 5A , a first conductive oxide layer T1 and a second conductive oxide layer T2 are formed on the substrate 100 . In this embodiment, a first conductive oxide layer T1 and a second conductive oxide layer T2 are formed on the buffer layer 110 .

In some examples, a method of forming the first conductive oxide layer T1 and the second conductive oxide layer T2 includes: forming a conductive oxide layer (not shown) blanketing the buffer layer 110; Form a patterned photoresist (not shown); use the patterned photoresist as a mask to etch the conductive oxide layer to form a first conductive oxide layer T1 and a second conductive oxide layer T2 that are separated from each other; finally, Remove patterned photoresist. In other words, in some embodiments, the first conductive oxide layer T1 and the second conductive oxide layer T2 are the same patterned film layer, and the first conductive oxide layer T1 and the second conductive oxide layer T2 are formed at the same time. .

Referring to FIG. 5B , a metal oxide semiconductor layer OS is formed on the buffer layer 110 , the first conductive oxide layer T1 and the second conductive oxide layer T2 . In this embodiment, the metal oxide semiconductor layer OS fills the gap between the first conductive oxide layer T1 and the second conductive oxide layer T2. The metal oxide semiconductor layer OS contacts the upper surface of the first conductive oxide layer T1 and the upper surface of the second conductive oxide layer T2. Part of the first conductive oxide layer T1 and part of the second conductive oxide layer T2 overlap the metal oxide semiconductor layer OS, and another part of the first conductive oxide layer T1 and another part of the second conductive oxide layer T2 do not overlap the metal oxide layer OS. physical semiconductor layer OS.

Referring to FIG. 5C, a first gate dielectric layer 120 is formed on the metal oxide semiconductor layer OS. The gate G is formed on the first gate dielectric layer 120 , and the gate G overlaps the metal oxide semiconductor layer OS in the normal direction ND of the upper surface of the substrate 100 .

In some embodiments, the gate G is used as a mask to perform a doping process on the metal oxide semiconductor layer OS to form a source region, a drain region, and a source region and a drain region in the metal oxide semiconductor layer OS. The channel region between the electrode regions, where the channel region overlaps the gate G, and the source region and the drain region are doped to have a lower resistivity than the channel region. In some embodiments, the doping process includes, for example, a hydrogen plasma process.

Referring to FIG. 5D , an interlayer dielectric layer 140 is formed on the gate G. A first contact hole V1 and a second contact hole V2 are formed in the interlayer dielectric layer 140 . In this embodiment, the first contact hole V1 and the second contact hole V2 extend through the interlayer dielectric layer 140 and the first gate dielectric layer 120 and expose the upper surface of the first conductive oxide layer T1 and the first gate dielectric layer 120 respectively. The upper surface of the second conductive oxide layer T2. In other words, the first conductive oxide layer T1 and the second conductive oxide layer T2 are respectively located under the first contact hole V1 and the second contact hole V2. In some embodiments, the method of forming the first contact hole V1 and the second contact hole V2 includes: forming a patterned photoresist (not shown) on the interlayer dielectric layer 140; using the patterned photoresist as a mask. The interlayer dielectric layer 140 and the first gate dielectric layer 120 are etched; finally, the patterned photoresist is removed. Since the first contact hole V1 and the second contact hole V2 are laterally separated from the metal oxide semiconductor layer OS, the etching process when etching the interlayer dielectric layer 140 and the first gate dielectric layer 120 will not damage the metal oxide semiconductor layer. OS, thereby improving the process yield of semiconductor devices.

Finally, please return to FIG. 4 . The first electrode S is formed in the first contact hole V1 , and the first electrode S is electrically connected to the metal oxide semiconductor layer OS through the first conductive oxide layer T1 . A second electrode D is formed in the second contact hole V2, and the second electrode D is electrically connected to the metal oxide semiconductor layer OS through the second conductive oxide layer T2. At this point, the semiconductor device 10C is substantially completed.

In some examples, the method of forming the first electrode S and the second electrode D includes: forming a conductive layer (not shown) blanketed on the interlayer dielectric layer 140; forming a patterned photoresist (not shown) on the conductive layer. (drawn); use the patterned photoresist as a mask to etch the conductive layer to form a first electrode S and a second electrode D that are separated from each other; finally, remove the patterned photoresist. In other words, in some embodiments, the first electrode S and the second electrode D are the same patterned film layer, and the first electrode S and the second electrode D are formed at the same time.

FIG. 6 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. It must be noted here that the embodiment of FIG. 6 follows the component numbers and part of the content of the embodiment of FIG. 4 , where the same or similar numbers are used to represent the same or similar elements, and the description of the same technical content is omitted. For descriptions of omitted parts, reference may be made to the foregoing embodiments and will not be described again here.

The main difference between the semiconductor device 10D of FIG. 6 and the semiconductor device 10C of FIG. 4 is that the semiconductor device 10D further includes an auxiliary conductive oxide layer T3.

Referring to FIG. 6 , the auxiliary conductive oxide layer T3 is located between the gate electrode G and the metal oxide semiconductor layer OS. The resistivity of the auxiliary conductive oxide layer T3 is lower than the resistivity of the metal oxide semiconductor layer OS. By providing the auxiliary conductive oxide layer T3, the current level of the semiconductor device 10D can be increased.

In some embodiments, the material of the auxiliary conductive oxide layer T3 includes a transparent conductive oxide, such as indium tin oxide, indium zinc oxide, aluminum zinc oxide, or a stacked layer of at least two of the above.

FIG. 7 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. It must be noted here that the embodiment of FIG. 7 follows the component numbers and part of the content of the embodiment of FIG. 1 , where the same or similar numbers are used to represent the same or similar elements, and descriptions of the same technical content are omitted. For descriptions of omitted parts, reference may be made to the foregoing embodiments and will not be described again here.

The main difference between the semiconductor device 10E of FIG. 7 and the semiconductor device 10A of FIG. 1 is that the metal oxide semiconductor layer OS of the semiconductor device 10E contacts the upper surface of the second conductive oxide layer T2.

Please refer to FIG. 7 . The first conductive oxide layer T1 and the second conductive oxide layer T2 belong to different film layers. The first conductive oxide layer T1 is located between the first gate dielectric layer 120 and the second gate dielectric layer 130 . between the buffer layer 110 and the first gate dielectric layer 120 . The first contact hole V1 penetrates the interlayer dielectric layer 140 and the second gate dielectric layer 130 , and the second contact hole V2 penetrates the interlayer dielectric layer 140 , the second gate dielectric layer 130 and the first gate dielectric layer 120 .

The metal oxide semiconductor layer OS extends along the side of the second conductive oxide layer T2 to the upper surface of the second conductive oxide layer T2, and the metal oxide semiconductor layer OS has a break at the side of the second conductive oxide layer T2. Poor GP2. The gate G overlaps the gap GP2 of the metal oxide semiconductor layer OS in the normal direction ND of the upper surface of the substrate 100, thereby reducing the impact of the lateral electric field between the gate G and the second electrode D on the metal oxide semiconductor. The impact of layer OS.

FIG. 8 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. It must be noted here that the embodiment of FIG. 8 follows the component numbers and part of the content of the embodiment of FIG. 1 , where the same or similar numbers are used to represent the same or similar elements, and the description of the same technical content is omitted. For descriptions of omitted parts, reference may be made to the foregoing embodiments and will not be described again here.

The main difference between the semiconductor device 10F of FIG. 8 and the semiconductor device 10A of FIG. 1 is that the second electrode D of the semiconductor device 10F directly contacts the upper surface of the metal oxide semiconductor layer OS.

Please refer to FIG. 8 . In this embodiment, the first electrode S is connected to the metal oxide semiconductor layer OS through the first conductive oxide layer T1 , and the second electrode D is directly connected to the metal oxide semiconductor layer OS.

10A, 10B, 10C, 10E, 10F: Semiconductor devices 100:Substrate 110: Buffer layer 112: Silicon nitride layer 114: Silicon oxide layer 120: First gate dielectric layer 130: Second gate dielectric layer 140: Interlayer dielectric layer D: second electrode G: gate GP1, GP2: gap H1a, H2a, H1b, H2b: horizontal distance ND: normal direction O1: First opening O2: Second opening OS: metal oxide semiconductor layer S: first electrode T1: first conductive oxide layer T1a:Part 1 T2: Second conductive oxide layer T2a:Part 2 V1: first contact hole V2: Second contact hole

FIG. 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. 2A to 2E are schematic cross-sectional views of the manufacturing method of the semiconductor device of FIG. 1 . FIG. 3 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. FIG. 4 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. 5A to 5D are schematic cross-sectional views of the manufacturing method of the semiconductor device of FIG. 4 . FIG. 6 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. FIG. 7 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. FIG. 8 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

10A:Semiconductor device

100:Substrate

110: Buffer layer

112: Silicon nitride layer

114: Silicon oxide layer

120: First gate dielectric layer

130: Second gate dielectric layer

140: Interlayer dielectric layer

D: second electrode

G: gate

H1a, H2a, H1b, H2b: horizontal distance

ND: normal direction

O1: First opening

O2: Second opening

OS: metal oxide semiconductor layer

S: first electrode

T1: first conductive oxide layer

T1a:Part 1

T2: Second conductive oxide layer

T2a:Part 2

V1: first contact hole

V2: Second contact hole

Claims (10)

A semiconductor device includes: a substrate; a metal oxide semiconductor layer located on the substrate; a first gate dielectric layer located on the metal oxide semiconductor layer, wherein the first gate dielectric layer has an overlapping a first opening on the upper surface of the metal oxide semiconductor layer; a second gate dielectric layer located on the first gate dielectric layer and the first conductive oxide layer; a gate electrode located on the first gate dielectric layer On the two gate dielectric layers, and overlapping the metal oxide semiconductor layer in a normal direction of an upper surface of the substrate, the metal oxide semiconductor layer includes a first doped region, a second a doped region and a channel region located between the first doped region and the second doped region, wherein the channel region overlaps the gate, and the first doped region and the second doped region are doped to have a resistivity lower than that of the channel region; an interlayer dielectric layer located above the gate, wherein the interlayer dielectric layer has a first contact hole and a second contact hole, wherein the first contact The hole and the second contact hole pass through the interlayer dielectric layer and the second gate dielectric layer, and the first contact hole is laterally separated from the metal oxide semiconductor layer; a first conductive oxide layer is located Below the first contact hole and connected to the metal oxide semiconductor layer, the first conductive oxide layer fills the first opening to contact the upper surface of the metal oxide semiconductor layer, and the first conductive oxide layer layer A first portion extends from the first opening to the gate; a first electrode fills the first contact hole and is electrically connected to the metal oxide semiconductor layer through the first conductive oxide layer; and a first electrode The second electrode fills the second contact hole and is electrically connected to the metal oxide semiconductor layer. The semiconductor device of claim 1, further comprising: a second conductive oxide layer located below the second contact hole and connected to the metal oxide semiconductor layer, wherein the second electrode penetrates the second conductive oxide layer and is electrically connected to the metal oxide semiconductor layer. The semiconductor device of claim 1, wherein the first gate dielectric layer has a second opening overlapping the metal oxide semiconductor layer, and the second conductive oxide layer fills the second opening to contact the metal the upper surface of the oxide semiconductor layer. The semiconductor device of claim 1, wherein a horizontal distance between the first conductive oxide layer and the gate is smaller than a horizontal distance between the first opening and the gate. The semiconductor device of claim 1, wherein the metal oxide semiconductor layer contacts the upper surface of the second conductive oxide layer. The semiconductor device of claim 5, wherein the metal oxide semiconductor layer extends along the side of the second conductive oxide layer to the upper surface of the second conductive oxide layer, and the metal oxide semiconductor layer is on the second conductive oxide layer The side surface has a step, and the gate overlaps the step of the metal oxide semiconductor layer in the normal direction of the upper surface of the substrate. The semiconductor device of claim 1, wherein the first conductive oxide layer extends below the gate. The semiconductor device according to claim 1, further comprising: an auxiliary conductive oxide layer located between the gate and the metal oxide semiconductor layer or between the metal oxide semiconductor layer and the substrate. A method of manufacturing a semiconductor device, including: forming a metal oxide semiconductor layer and a first gate dielectric layer on a substrate, wherein the first gate dielectric layer has an upper surface exposing the metal oxide semiconductor layer a first opening; forming a first conductive oxide layer in the first opening of the first gate dielectric layer, and the first conductive oxide layer fills the first opening to contact the metal oxide semiconductor the upper surface of the layer; forming a second gate dielectric layer on the first conductive oxide layer and the first gate dielectric layer; forming a gate electrode on the second gate dielectric layer, and the gate The pole overlaps the metal oxide semiconductor layer in a normal direction of an upper surface of the substrate, and the first part of the first conductive oxide layer extends from the first opening to the gate; to the metal oxide The semiconductor layer undergoes a doping process to form a first doped region, a second doped region and a channel between the first doped region and the second doped region in the metal oxide semiconductor layer. area, where the channel area overlaps the gate pole, and the first doped region and the second doped region are doped to have a resistivity lower than that of the channel region; an interlayer dielectric layer is formed on the gate electrode; in the interlayer dielectric layer A first contact hole and a second contact hole are formed, wherein the first contact hole and the second contact hole pass through the interlayer dielectric layer and the second gate dielectric layer, and the first conductive oxide layer is located Below the first contact hole, wherein the first contact hole is laterally separated from the metal oxide semiconductor layer; a first electrode is formed in the first contact hole, and the first electrode penetrates the first conductive oxide layer and electrically connected to the metal oxide semiconductor layer; and forming a second electrode in the second contact hole, and the second electrode is electrically connected to the metal oxide semiconductor layer. The method of manufacturing a semiconductor device according to claim 9, further comprising: forming a second conductive oxide layer in a second opening of the first gate dielectric layer, wherein the first opening and the second opening overlap. on the metal oxide semiconductor layer; and forming the second gate dielectric layer on the first conductive oxide layer and the second conductive oxide layer.

Images