TWI814340B - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

A semiconductor device includes a substrate, a first gate, a semiconductor layer, a first gate dielectric layer, a second gate dielectric layer, a source electrode, a drain electrode, and a piezoelectric device. The first gate is located on the substrate. The semiconductor channel overlaps the first gate electrode in the direction of the normal line of the top surface of the substrate. The first gate dielectric layer is located between the semiconductor channel and the first gate. The second gate dielectric layer is over the semiconductor channel. The source electrode and the drain electrode are electrically connected to the semiconductor channel. The piezoelectric device is located on the second gate dielectric layer and includes a metal oxide electrode, a piezoelectric material, and a top electrode stacked on each other. The semiconductor channel is located between the metal oxide electrode and the first gate.

Description

Semiconductor device and manufacturing method thereof

The present invention relates to a semiconductor device, and in particular, to a semiconductor device including a piezoelectric device and a manufacturing method thereof.

At present, common thin film transistors usually use amorphous silicon semiconductors as channels. Amorphous silicon semiconductors are widely used in various thin film transistors due to their simple manufacturing process and low cost.

With the advancement of display technology, the resolution of display panels is increasing year by year. In order to shrink thin film transistors in pixel circuits, many manufacturers are committed to developing new semiconductor materials, such as metal oxide semiconductor materials. Among metal oxide semiconductor materials, indium gallium zinc oxide (IGZO) has the advantages of small area and high electron mobility, so it is regarded as an important new semiconductor material.

The present invention provides a semiconductor device that changes the drain current in response to changes in pressure.

The present invention provides a method for manufacturing a semiconductor device, which has the advantages of high process yield and low production cost.

At least one embodiment of the present invention provides a semiconductor device. The semiconductor device includes a substrate, a first gate, a semiconductor layer, a first gate dielectric layer, a second gate dielectric layer, a source, a drain, and a piezoelectric device. The first gate is located on the substrate. The semiconductor layer overlaps the first gate in a normal direction of the top surface of the substrate. The first gate dielectric layer is located between the semiconductor layer and the first gate electrode. The second gate dielectric layer is located on the semiconductor layer. The source electrode and the drain electrode are electrically connected to the semiconductor layer. The piezoelectric device is located on the second gate dielectric layer and includes a metal oxide electrode, a piezoelectric material and a top electrode stacked on each other. The semiconductor layer is located between the metal oxide electrode and the first gate.

At least one embodiment of the present invention provides a method for manufacturing a semiconductor device, including: forming a first gate on a substrate; forming a first gate dielectric layer on the first gate; forming a semiconductor layer on the first gate dielectric. On the electrical layer, the first gate dielectric layer is located between the semiconductor layer and the first gate electrode; a second gate dielectric layer is formed on the semiconductor layer; a source electrode and a drain electrode are formed, wherein the source electrode and the drain electrode are electrically Sexually connecting the semiconductor layer; forming a piezoelectric device on the second gate dielectric layer, wherein the piezoelectric device includes metal oxide electrodes, piezoelectric materials and top electrodes stacked on each other, wherein the semiconductor layer is located between the metal oxide electrode and the first between gates.

FIG. 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 1 , the semiconductor device 10A includes a substrate 100 , a first gate electrode 210 , a semiconductor layer 220 , a first gate dielectric layer 110 , a second gate dielectric layer 120 , a source electrode 232 , a drain electrode 234 and a piezoelectric device 300 .

The material of the substrate 100 may be glass, quartz, organic polymer, opaque/reflective material (such as conductive material, metal, wafer, ceramic or other applicable materials) or other applicable materials. If conductive materials or metals are used, an insulating layer (not shown) is covered on the substrate 100 to avoid short circuit problems.

The first gate 210 is located on the substrate 100 . The material of the first gate 210 is, for example, chromium, gold, silver, copper, tin, lead, hafnium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc and other metals, the above alloys, the above metal oxides, the above metal nitrogen compounds or a combination of the above or other conductive materials. In some embodiments, other conductive layers and insulating layers may also be included between the first gate 210 and the substrate 100 .

The first gate dielectric layer 110 is located on the first gate 210 and covers the first gate 210 . The first gate dielectric layer 110 includes inorganic materials (such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, other suitable materials, or stacked layers of at least two of the above materials), organic materials, or other Suitable materials or a combination of the above.

The semiconductor layer 220 is located on the first gate dielectric layer 110 . The first gate dielectric layer 110 is located between the semiconductor layer 220 and the first gate electrode 210 . The semiconductor layer 220 overlaps the first gate 210 in the normal direction ND of the top surface of the substrate 100 . The material of the semiconductor layer 220 includes, for example, metal oxides, such as indium gallium zinc oxide (IGZO), indium tungsten zinc oxide (IWZO) or other suitable metal oxide semiconductor materials. In this embodiment, the semiconductor layer 220 includes a source region 222 , a drain region 226 , and a channel region 224 located between the source region 222 and the drain region 226 . The source region 222 and the drain region 226 are, for example, hydrogen-doped regions. The channel area 224 overlaps the first gate 210 in the normal direction ND. In this embodiment, part of the source region 222 and part of the drain region 226 also overlap the first gate 210 in the normal direction ND.

The second gate dielectric layer 120 is located on the semiconductor layer 220 and covers the semiconductor layer 220 . The second gate dielectric layer 120 includes inorganic materials (such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, other suitable materials, or stacked layers of at least two of the above materials), organic materials, or other Suitable materials or a combination of the above.

The second gate 240 is located on the second gate dielectric layer 120 and overlaps the channel region 224 of the semiconductor layer 240 in the normal direction ND. The material of the second gate 240 is, for example, chromium, gold, silver, copper, tin, lead, hafnium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc and other metals, the above alloys, the above metal oxides, the above metal nitrogen compounds or a combination of the above or other conductive materials. When the second gate 240 includes an aluminum element, the second gate 240 may act as a hydrogen barrier layer, thereby reducing the probability of hydrogen atoms diffusing into the channel region 224 .

The interlayer dielectric layer 130 is located on the second gate dielectric layer 120 . The interlayer dielectric layer 130 includes an opening that overlaps the channel region 224 of the semiconductor layer 220 and the second gate 240 , and the second gate 240 is located at the bottom of the opening. The two contact holes penetrate the interlayer dielectric layer 130 and the second gate dielectric layer 120 and extend to the source region 222 and the drain region 226 of the semiconductor layer 220 .

The interlayer dielectric layer 130 includes inorganic materials (such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, other suitable materials, or stacked layers of at least two of the above materials), organic materials, or other suitable materials. materials or a combination of the above. In some embodiments, hydrogen is included in the interlayer dielectric layer 130 . In some embodiments, during the manufacturing process of the semiconductor device 10A, the hydrogen element in the interlayer dielectric layer 130 is diffused to the source region 222 and the drain region 226 of the semiconductor layer 220 and the metal oxide electrode 310 through a heat treatment process. However, the present invention is not limited to this. In other embodiments, the hydrogen element is diffused into the source region 222 and the drain region 226 and the metal oxide electrode 310 through a hydrogen plasma process or other doping processes.

The source electrode 232 and the drain electrode 234 are filled in the two contact holes penetrating the interlayer dielectric layer 130 and the second gate dielectric layer 120 to electrically connect the source electrode region 222 and the drain electrode region 226 of the semiconductor layer 220 respectively. The source electrode 232 and the drain electrode 234 are made of, for example, chromium, gold, silver, copper, tin, lead, hafnium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc and other metals, the above alloys, the above metal oxides, the above Metal nitrides or combinations of the above or other conductive materials.

The piezoelectric device 300 is located on the second gate dielectric layer 120 and includes a metal oxide electrode 310, a piezoelectric material 320 and a top electrode 330 stacked on each other.

The metal oxide electrode 310 is filled in the opening of the interlayer dielectric layer 130 to electrically connect the second gate electrode 240 . In this embodiment, the metal oxide electrode 310 directly contacts the second gate 240 . In this embodiment, the width of the bottom of the opening of the interlayer dielectric layer 130 is equal to the width of the metal oxide electrode 310 . It can also be said that the metal oxide electrode 310 fills the entire bottom of the opening of the interlayer dielectric layer 130 . In some embodiments, metal oxide electrode 310 includes fluorine-treated indium gallium zinc oxide. The semiconductor layer 220 is located between the metal oxide electrode 310 and the first gate 210 .

Piezoelectric material 320 is located on metal oxide electrode 310. In some embodiments, piezoelectric material 320 includes a polymer or a composite of a polymer and a ceramic material. For example, the piezoelectric material 320 includes P(VDF-TrFE) or a composite material of P(VDF-TrFE) and lead zirconate titanate (PZT).

Top electrode 330 is located on piezoelectric material 320. In some embodiments, the top electrode 330 and the source electrode 232 are both electrically connected to a reference voltage, such as ground voltage. In some embodiments, the material of the top electrode 330 is, for example, chromium, gold, silver, copper, tin, lead, hafnium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc and other metals, the above alloys, the above metal oxides , the above metal nitride or a combination of the above or other conductive materials. In this embodiment, the sides of the top electrode 330 are aligned with the sides of the piezoelectric material 320, but the invention is not limited thereto. In other embodiments, the sides of top electrode 330 are not aligned with the sides of piezoelectric material 320 .

2A to 2K are schematic cross-sectional views of the manufacturing method of the semiconductor device of FIG. 1 .

Referring to FIG. 2A , a first gate 210 is formed on the substrate 100 . Next, a first gate dielectric layer 110 is formed on the first gate electrode 210 .

Referring to FIG. 2B, a semiconductor layer 220' is formed on the first gate dielectric layer 110, where the first gate dielectric layer 110 is located between the semiconductor layer 220' and the first gate electrode 210. Next, a second gate dielectric layer 120 is formed on the semiconductor layer 220'.

Referring to FIG. 2C , a second gate 240 is formed on the second gate dielectric layer 120 . Next, using the second gate 240 as a mask, a doping process P is performed on the semiconductor layer 220' to form the semiconductor layer 220 including the source region 222, the drain region 226 and the channel region 224. In some embodiments, the doping process P is, for example, a hydrogen plasma process.

In this embodiment, the second gate dielectric layer 120 covers the semiconductor layer 220', but the invention is not limited thereto. In other embodiments, the second gate dielectric layer 120 is patterned so that the second gate dielectric layer 120 exposes the semiconductor layer 220' that does not overlap the second gate electrode 240. In some embodiments, the doping process P is performed on the semiconductor layer 220' after patterning the second gate dielectric layer 120.

Referring to FIG. 2D , an interlayer dielectric layer 130 is formed on the second gate 240 and the second gate dielectric layer 120 . The interlayer dielectric layer 130 covers the second gate 240 .

Referring to FIG. 2E , a first contact hole TH1 and a second contact hole TH2 penetrating the interlayer dielectric layer 130 and the second gate dielectric layer 120 are formed.

Referring to FIG. 2F, a source electrode 232 and a drain electrode 234 are formed. The source electrode 232 and the drain electrode 234 belong to the same patterned conductive layer. The source electrode 232 and the drain electrode 234 are respectively filled in the first contact hole TH1 and the second contact hole TH2 to electrically connect the source electrode region 222 and the drain electrode region 226 of the semiconductor layer 220 .

Referring to FIG. 2G , an opening OP1 is formed in the interlayer dielectric layer 130 , and the opening 1 exposes at least part of the top surface of the second gate 240 . In this embodiment, the opening OP1 is formed in the interlayer dielectric layer 130 after the source electrode 232 and the drain electrode 234 are formed, thereby preventing the second gate electrode 240 from being damaged by the etching process when the source electrode 232 and the drain electrode 234 are formed. the top surface.

Referring to FIGS. 2H to 2K and FIG. 1 , the piezoelectric device 300 is formed on the second gate 240 .

Please refer to FIG. 2H first, forming a metal oxide material layer 310'' in the opening OP1. In this embodiment, the metal oxide material layer 310″ extends outside the opening OP1 and covers the interlayer dielectric layer 130, the source electrode 232 and the drain electrode 234.

Next, please refer to FIG. 2I to perform fluorine treatment on the metal oxide material layer 310''. For example, the metal oxide material layer 310' is treated with fluorine plasma to obtain a fluorine-treated metal oxide material layer 310'.

Next, referring to FIG. 2J, the fluorine-treated metal oxide material layer 310' is patterned to obtain a metal oxide electrode 310. In this embodiment, the fluorine content in the metal oxide electrode 310 is greater than the fluorine content in the semiconductor layer 220 . In some embodiments, the metal oxide electrode 310 is not hydrogen-doped. Therefore, the hydrogen content in the metal oxide electrode 310 is less than the hydrogen content in the source region 222 and the drain region 226 , but this is not the case in the present invention. is limited. In other embodiments, a hydrogen doping process is performed before or after the fluorine treatment. Therefore, the hydrogen content in the metal oxide electrode 310 is greater than or equal to the hydrogen content in the source region 222 and the drain region 226 .

Referring to FIG. 2K , a piezoelectric material 320 is formed on the metal oxide electrode 310 . In this embodiment, since the surface of the metal oxide electrode 310 is treated with fluorine, the diffusion of fluorine during the thermal annealing and crystallization process of the piezoelectric material will form carbon-fluorine bonds (CF, CF ₂ ) in the piezoelectric material. , carbon-fluorine hydrogen bonding (C-FH), so the crystallinity of the piezoelectric material 320 can be improved.

Finally, please return to FIG. 1 to form a top electrode 330 on the piezoelectric material 320. At this point, the semiconductor device 10A is substantially completed.

FIG. 3 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. It must be noted here that the embodiment of FIG. 3 follows the component numbers and part of the content of the embodiment of FIG. 1 , where the same or similar numbers are used to represent the same or similar elements, and descriptions of the same technical content are omitted. For descriptions of omitted parts, reference may be made to the foregoing embodiments and will not be described again here.

The main difference between the semiconductor device 10B of FIG. 3 and the semiconductor device 10A of FIG. 1 is that the width of the metal oxide electrode 310 of the semiconductor device 10B is greater than the width of the bottom of the opening OP1 of the interlayer dielectric layer 130 . The metal oxide electrode 310 extends, for example, along the side of the opening OP1 to the top surface of the interlayer dielectric layer 130 .

FIG. 4 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. It must be noted here that the embodiment of FIG. 4 follows the component numbers and part of the content of the embodiment of FIG. 1 , where the same or similar numbers are used to represent the same or similar elements, and the description of the same technical content is omitted. For descriptions of omitted parts, reference may be made to the foregoing embodiments and will not be described again here.

The main difference between the semiconductor device 10C of FIG. 4 and the semiconductor device 10A of FIG. 1 is that the width of the metal oxide electrode 310 of the semiconductor device 10C is smaller than the width of the bottom of the opening OP1 of the interlayer dielectric layer 130 . For example, the metal oxide electrode 310 does not contact or partially contacts the side surface of the opening OP1 , and the piezoelectric material 320 contacts, for example, part of the top surface of the second gate 240 .

FIG. 5 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. It must be noted here that the embodiment of FIG. 5 follows the component numbers and part of the content of the embodiment of FIG. 1 , where the same or similar numbers are used to represent the same or similar elements, and descriptions of the same technical content are omitted. For descriptions of omitted parts, reference may be made to the foregoing embodiments and will not be described again here.

The main difference between the semiconductor device 10D of FIG. 5 and the semiconductor device 10A of FIG. 1 is that the metal oxide electrode 310 a of the piezoelectric device 300 a of the semiconductor device 10D is directly formed on the second gate dielectric layer 120 . In other words, the semiconductor device 10D does not include the second gate (the second gate 240 of FIG. 1 ). In this embodiment, the metal oxide electrode 310a is, for example, a hydrogen-doped and fluorine-treated metal oxide (such as indium gallium zinc oxide or indium tungsten zinc oxide).

6A to 6I are schematic cross-sectional views of the manufacturing method of the semiconductor device of FIG. 5 .

Figure 6A continues the process of Figure 2B. Referring to FIG. 6A, a metal oxide material layer 310″ is formed on the second gate dielectric layer 120. The metal oxide material layer 310'' overlaps the entire semiconductor layer 220' in the normal direction ND of the top surface of the substrate 100.

Referring to FIG. 6B, the metal oxide material layer 310″ is subjected to fluorine treatment. For example, the metal oxide material layer 310' is treated with fluorine plasma to obtain a fluorine-treated metal oxide material layer 310'. Since the metal oxide material layer 310'' covers the semiconductor layer 220', the probability of fluorine element diffusing into the semiconductor layer 220' can be reduced.

Next, referring to FIG. 6C, the fluorine-treated metal oxide material layer 310' is patterned to obtain a metal oxide electrode 310. The metal oxide electrode 310 is formed on the second gate dielectric layer 120 .

Referring to FIG. 6D, using the metal oxide electrode 310 as a mask, a doping process P is performed on the semiconductor layer 220' to form the semiconductor layer 220 including the source region 222, the drain region 226 and the channel region 224. In some embodiments, the doping process P is, for example, a hydrogen plasma process. In this embodiment, the metal oxide electrode 310 becomes a hydrogen-doped metal oxide electrode 310a after undergoing the doping process P.

In this embodiment, the fluorine content in the hydrogen-doped metal oxide electrode 310 a is greater than the fluorine content in the semiconductor layer 220 .

Referring to FIG. 6E, an interlayer dielectric layer 130 is formed on the metal oxide electrode 310a and the second gate dielectric layer 120. The interlayer dielectric layer 130 covers the metal oxide electrode 310a.

Referring to FIG. 6F , a first contact hole TH1 and a second contact hole TH2 penetrating the interlayer dielectric layer 130 and the second gate dielectric layer 120 are formed. The first contact hole TH1 and the second contact hole TH2 expose the source region 222 and the drain region 226 of the semiconductor layer 220 .

Referring to FIG. 6G , source 232 and drain 234 are formed. The source electrode 232 and the drain electrode 234 belong to the same patterned conductive layer. The source electrode 232 and the drain electrode 234 are respectively filled in the first contact hole TH1 and the second contact hole TH2 to electrically connect the source electrode region 222 and the drain electrode region 226 of the semiconductor layer 220 .

Referring to FIG. 6H, an opening OP1 is formed in the interlayer dielectric layer 130, and the opening OP1 exposes the metal oxide electrode 310a. In this embodiment, the opening OP1 is formed in the interlayer dielectric layer 130 after the source electrode 232 and the drain electrode 234 are formed, thereby preventing the metal oxide electrode 310a from being damaged by the etching process during the formation of the source electrode 232 and the drain electrode 234. , but the present invention is not limited to this. In other embodiments, the first contact hole TH1, the second contact hole TH2 and the opening OP1 are formed through the same etching process.

Referring to FIG. 6I, a piezoelectric material 320 is formed on the metal oxide electrode 310a. In this embodiment, since the surface of the metal oxide electrode 310a is treated with fluorine, the diffusion of fluorine during the thermal annealing and crystallization process of the piezoelectric material will form carbon-fluorine bonds (CF, CF ₂ ) in the piezoelectric material. , carbon-fluorine hydrogen bonding (C-FH), so the crystallinity of the piezoelectric material 320 can be improved.

Finally, please return to FIG. 5 to form a top electrode 330 on the piezoelectric material 320. At this point, the semiconductor device 10D is substantially completed.

FIG. 7 is a graph illustrating voltage changes and drain current changes of the second gate or metal oxide electrode of a semiconductor device according to an embodiment of the present invention. FIG. 8 is a waveform diagram of time and drain current changes of a semiconductor device according to an embodiment of the present invention.

Please refer to Figure 7. The horizontal axis is the voltage V _TG of the second gate or metal oxide electrode, and the vertical axis is the drain current ( _ID ).

When no additional pressure is applied to the piezoelectric device, the voltage-current curve of the semiconductor device conforms to the solid line in Figure 7; when additional pressure is applied to the piezoelectric device, the voltage-current curve of the semiconductor device conforms to the dotted line in Figure 7. When the voltage of the first gate is fixed so that the semiconductor device is in the subthreshold region, and additional pressure is applied to the piezoelectric device, the drain current will decrease from I ₁ to I ₂ , between I ₁ and I ₂ There is a current change ΔI. By measuring the current change ΔI, we can know how much additional pressure the outside world exerts on the piezoelectric device.

In this embodiment, since additional pressure is applied to the piezoelectric device, a positive voltage appears on the side of the piezoelectric material that enters the metal oxide electrode, and a negative voltage appears on the side of the piezoelectric material that enters the top electrode. Therefore, Figure 7 The dotted line in is shifted to the right compared to the solid line, that is, the drain current decreases after applying pressure. The positive and negative voltages generated when additional pressure is applied are related to the polarization direction of the piezoelectric material. Therefore, in other embodiments, after additional pressure is applied to the piezoelectric device, a negative voltage appears on the side of the piezoelectric material that is close to the metal oxide electrode. voltage, and a positive voltage appears on the side of the piezoelectric material that is close to the top electrode. At this time, the dotted line will shift to the left compared to the solid line, that is, the drain current will increase after the pressure is applied.

In summary, the semiconductor device of the present invention changes the drain current in response to changes in pressure. In addition, the semiconductor device of the present invention has the advantages of high process yield and low production cost.

10A, 10B, 10C, 10D: Semiconductor devices 100:Substrate 110: First gate dielectric layer 120: Second gate dielectric layer 130: Interlayer dielectric layer 210: first gate 220’, 220: Semiconductor layer 222: Source region 224: Passage area 226: Drainage area 232:Source 234:Jiji 240: Second gate 300, 300a: Piezoelectric device 310’, 310’’: metal oxide material layer 310, 310a: Metal oxide electrode 320: Piezoelectric materials 330:Top electrode ND: normal direction OP1: Open your mouth P: doping process TH1: first contact hole TH2: Second contact hole

FIG. 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. 2A to 2K are schematic cross-sectional views of the manufacturing method of the semiconductor device of FIG. 1 . FIG. 3 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. FIG. 4 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. FIG. 5 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. 6A to 6I are schematic cross-sectional views of the manufacturing method of the semiconductor device of FIG. 5 . FIG. 7 is a graph illustrating voltage changes and drain current changes of the second gate or metal oxide electrode of a semiconductor device according to an embodiment of the present invention. FIG. 8 is a waveform diagram of time and drain current changes of a semiconductor device according to an embodiment of the present invention.

10A:Semiconductor device

100:Substrate

110: First gate dielectric layer

120: Second gate dielectric layer

130: Interlayer dielectric layer

210: first gate

220: Semiconductor layer

222: Source region

224: Passage area

226: Drainage area

232:Source

234:Jiji

240: Second gate

300: Piezoelectric device

310: Metal oxide electrode

320: Piezoelectric materials

330:Top electrode

ND: normal direction

Claims (10)

A semiconductor device includes: a substrate; a first gate located on the substrate; a semiconductor layer overlapping the first gate in a normal direction on the top surface of the substrate; a first gate An electrical layer is located between the semiconductor layer and the first gate; a second gate dielectric layer is located on the semiconductor layer; a source electrode and a drain electrode are electrically connected to the semiconductor layer; an interlayer dielectric layer a layer located on the second gate dielectric layer, wherein the interlayer dielectric layer includes an opening overlapping the semiconductor layer; and a piezoelectric device located on the second gate dielectric layer and including stacked A metal oxide electrode, a piezoelectric material and a top electrode, wherein the semiconductor layer is located between the metal oxide electrode and the first gate, and the metal oxide electrode fills the opening. The semiconductor device of claim 1, wherein the material of the semiconductor layer includes indium gallium zinc oxide, and the metal oxide electrode includes fluorine-treated indium gallium zinc oxide. The semiconductor device of claim 1, wherein the semiconductor layer includes a hydrogen-doped source region, a hydrogen-doped drain region, and a channel between the source region and the drain region. area, and the metal oxide electrode is hydrogen doped. The semiconductor device of claim 1, further comprising: a second gate overlapping the semiconductor layer in the normal direction, and the metal oxide electrode directly contacts the second gate. The semiconductor device of claim 1, wherein the width of the metal oxide electrode is less than, greater than, or equal to the width of the bottom of the opening of the interlayer dielectric layer. A method of manufacturing a semiconductor device, including: forming a first gate on a substrate; forming a first gate dielectric layer on the first gate; forming a semiconductor layer on the first gate dielectric layer above, wherein the first gate dielectric layer is located between the semiconductor layer and the first gate electrode; a second gate dielectric layer is formed on the semiconductor layer; a source electrode and a drain electrode are formed, wherein the The source electrode and the drain electrode are electrically connected to the semiconductor layer; and a piezoelectric device is formed on the second gate dielectric layer, wherein the piezoelectric device includes a metal oxide electrode stacked on each other, a piezoelectric material and a top electrode, wherein the semiconductor layer is located between the metal oxide electrode and the first gate electrode, wherein an interlayer dielectric layer is formed on the second gate dielectric layer before or after forming the metal oxide electrode, The interlayer dielectric layer includes an opening overlapping the semiconductor layer, and the metal oxide electrode is located in the opening. The manufacturing method of a semiconductor device as claimed in claim 6, wherein the method of forming the piezoelectric device includes: The metal oxide electrode is formed on the second gate dielectric layer; the piezoelectric material is formed on the metal oxide electrode; and the top electrode is formed on the piezoelectric material. The method of manufacturing a semiconductor device as claimed in claim 7, further comprising: after forming the metal oxide electrode, using the metal oxide electrode as a mask to perform a doping process on the semiconductor layer. The method of manufacturing a semiconductor device according to claim 6, further comprising: forming a second gate on the second gate dielectric layer; and forming the piezoelectric device on the second gate. The manufacturing method of a semiconductor device as claimed in claim 9, further comprising: before forming the piezoelectric device, using the second gate as a mask to perform a doping process on the semiconductor layer.

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