TWI812181B - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

A semiconductor device and manufacturing method thereof are provided. The semiconductor device includes a substrate, a thin film transistor and a resistive random-access memory. The thin film transistor is disposed on the substrate and includes a first metal oxide layer. The resistive random-access memory is disposed on the substrate and electrically connected with the thin film transistor. The resistive random-access memory includes a second metal oxide layer. A carrier concentration of the first metal oxide layer is larger than a carrier concentration of the second metal oxide layer.

Description

Semiconductor device and manufacturing method thereof

The present invention relates to a semiconductor device and a manufacturing method thereof, and in particular, to a semiconductor device including a metal oxide layer and a manufacturing method thereof.

Since thin film transistors containing metal oxide semiconductors are easily affected by oxygen, hydrogen and water in the environment, they are prone to performance degradation after long-term use, affecting the electrical properties of the thin film transistors. For example, in a display device including a thin film transistor array, if the performance of some metal oxide semiconductors of the thin film transistor deteriorates, unevenness (Mura) may easily occur in the picture displayed by the display device. Generally speaking, in order to reduce this uneven problem, the pixel circuit will be connected to an external chip, and a large amount of current information will be stored in the external compensation memory for algorithm calculation to calculate the compensation current or voltage, and then feed it back to the pixel in the circuit. However, the circuit design of the external chip is complex and costly.

The present invention provides a semiconductor device, the variable resistance memory of which has Excellent resistance switching performance.

The present invention provides a method for manufacturing a semiconductor device whose variable resistance memory has excellent resistance switching performance.

At least one embodiment of the present invention provides a semiconductor device. Semiconductor devices include substrates, thin film transistors, and variable resistance memories. The thin film transistor is disposed on the substrate and includes a first metal oxide layer. The variable resistance memory is disposed on the substrate and is electrically connected to the thin film transistor, wherein the variable resistance memory includes a second metal oxide layer. The carrier concentration of the first metal oxide layer is greater than the carrier concentration of the second metal oxide layer.

At least one embodiment of the present invention provides a method of manufacturing a semiconductor device. The manufacturing method of a semiconductor device includes providing a substrate, and then forming a thin film transistor and a variable resistance memory on the substrate. The thin film transistor includes a first metal oxide layer, and the variable resistive memory includes a second metal oxide layer. The thin film transistor is electrically connected to the variable resistance memory. The carrier concentration of the first metal oxide layer is greater than the carrier concentration of the second metal oxide layer.

10A, 10B, 10C, 10D, 10E, 10F: semiconductor devices

100:Substrate

102:Buffer layer

110: First metal oxide layer

110a: drain area

110b: Source region

110c: Passage area

120: Gate dielectric layer

130: First patterned conductive layer

140a, 140b, 140c: second metal oxide layer

150: Interlayer dielectric layer

160: Second patterned conductive layer

162a, 162b: Interface oxide layer

a, b, c: nodes

BE: first electrode

Cst: storage capacitor

D: drain

EL: light emitting element

G: Gate/first gate

G’: second gate

ND: direction

O1, O2, O3, O4: opening

P: doping process

PX: pixel circuit

R1, R2, R3: variable resistance memory

Rc: Compensation memory

S: Source

S1: Top surface

S2: side wall

TE: second electrode

T1, T2, T3: thin film transistor

Tdr: drive transistor

Tse: sensing transistor

Tsw: switching transistor

Twr: write transistor

V _data , V _DD , _VR , V _S1 , V _S2 , V _SS , V _sus : voltage

FIG. 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

FIG. 4 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

5A to 5C are schematic cross-sectional views of a manufacturing process of a semiconductor device according to an embodiment of the present invention.

FIG. 6 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

FIG. 7 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

8A to 8C are schematic cross-sectional views of a manufacturing process of a semiconductor device according to an embodiment of the present invention.

FIG. 9 is an equivalent circuit diagram of a pixel circuit according to an embodiment of the present invention.

FIG. 10 is a flow chart of a pixel compensation operation of a display device under the pixel circuit configuration of FIG. 9 according to an embodiment of the present invention.

FIG. 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 1 , the semiconductor device 10A includes a substrate 100 , a thin film transistor T1 and a variable resistance memory R1 . The variable resistance memory R1 and the thin film transistor Body T1 is electrically connected. In this embodiment, the semiconductor device 10A further includes a buffer layer 102 .

The material of the substrate 100 may be glass, quartz, organic polymer, opaque/reflective material (such as conductive material, metal, wafer, ceramic or other applicable materials) or other applicable materials. If conductive material or metal is used, an insulating layer (not shown) is covered on the first substrate 100 to avoid short circuit problems. In some embodiments, the substrate 100 is a flexible substrate, and the material of the substrate 100 is, for example, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyester (polyester, PES), polymethylmethacrylate (PMMA), polycarbonate (PC), polyimide (PI) or metal foil (Metal Foil) or other flexible materials . The buffer layer 102 is located on the substrate 100. The material of the buffer layer 102 may include silicon nitride, silicon oxide, silicon oxynitride or other suitable materials or stacked layers of the above materials, but the invention is not limited thereto.

The thin film transistor T1 is disposed on the substrate 100 . The thin film transistor T1 includes a first metal oxide layer 110, a gate electrode G, a source electrode S and a drain electrode D. The first metal oxide layer 110 is disposed on the substrate 100 and the buffer layer 102. The first metal oxide layer 110 includes a source region 110b, a drain region 110a and a channel region between the source region 110b and the drain region 110a. 110c. The gate G overlaps the first metal oxide layer 110 in the normal direction ND of the top surface of the substrate 100, and a gate dielectric layer 120 is sandwiched between the gate G and the first metal oxide layer 110. The electrical layer 120 covers the first metal oxide layer 110 . The interlayer dielectric layer 150 is disposed on the gate dielectric layer 120 and covers the gate Very G. The materials of the interlayer dielectric layer 150 and the gate dielectric layer 120 are, for example, silicon oxide, silicon nitride, silicon oxynitride or other suitable materials. In some embodiments, the materials of the interlayer dielectric layer 150 and the gate dielectric layer 120 may be hydrogen-free oxides, thereby preventing hydrogen atoms in the interlayer dielectric layer 150 and the gate dielectric layer 120 from diffusing during the manufacturing process. into the first metal oxide layer 110 . The openings O1 and O2 penetrate the interlayer dielectric layer 150 and the gate dielectric layer 120 and overlap the source region 110b and the drain region 110a respectively. The source S and the drain D are located on the interlayer dielectric layer 150 and fill the openings O1 and O2 respectively to be electrically connected to the source region 110b and the drain region 110a.

Although in this embodiment, the thin film transistor T1 is a top gate type thin film transistor as an example, the invention is not limited to this. In other embodiments, the thin film transistor T1 may also be a bottom gate type or other type of thin film transistor.

The variable resistance memory R1 includes a first electrode BE, a second metal oxide layer 140a and a second electrode TE. The first electrode BE is disposed on the gate dielectric layer 120, the second metal oxide layer 140a is disposed on the first electrode BE, and the second electrode TE is disposed on the second metal oxide layer 140a. In other words, the second metal oxide layer 140a is located between the first electrode BE and the second electrode TE, and the first electrode BE is closer to the substrate 100 than the second electrode TE. The interlayer dielectric layer 150 covers the second metal oxide layer 140a and the first electrode BE. The opening O3 penetrates the interlayer dielectric layer 150 and overlaps a portion of the second metal oxide layer 140a. The second electrode TE fills the opening O3 to be electrically connected to the second metal oxide layer 140a. The second electrode TE may be directly connected to the source S of the thin film transistor T1.

In this embodiment, the carrier concentration of the first metal oxide layer 110 is greater than The carrier concentration of the second metal oxide layer 140a is such that the variable resistive memory R1 has excellent resistance switching performance, such as endurance and data retention. In some embodiments, the oxygen content (oxygen vacancy) concentration of the first metal oxide layer 110 and the second metal oxide layer 140a is adjusted by adjusting the oxygen content (oxygen vacancy) concentration in the first metal oxide layer 110 and the second metal oxide layer 140a. carrier concentration. In this embodiment, the oxygen content of the first metal oxide layer 110 is less than the oxygen content of the second metal oxide layer 140a. For example, the oxygen content of the first metal oxide layer 110 may be between 10% and 50%, and the oxygen content of the second metal oxide layer 140a may be between 30% and 70%. In some embodiments, the thickness of the first metal oxide layer 110 may be between 10 nm and 50 nm, and the thickness of the second metal oxide layer 140a may be between 5 nm and 50 nm. In some embodiments, the thickness of the first metal oxide layer 110 is greater than the thickness of the second metal oxide layer 140a.

In one embodiment, the materials of the first metal oxide layer 110 and the second metal oxide layer 140a include indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), aluminum zinc tin oxide (AZTO), indium oxide Quaternary metal compounds such as tungsten zinc (IWZO) or ternary metals containing any three of gallium (Ga), zinc (Zn), indium (In), tin (Sn), aluminum (Al), and tungsten (W) composed of oxides. In some embodiments, the first metal oxide layer 110 and the second metal oxide layer 140a include materials with the same or different compositions.

In this embodiment, the material of the first electrode BE may be an inactive metal that is not easily oxidized and has a relatively high work function, such as tungsten, molybdenum, platinum, palladium, gold, molybdenum/aluminum/molybdenum, or other metals thereof. In combination, the material of the second electrode TE can be an active metal that is easier to oxidize and has a lower work function, such as titanium, titanium nitride, aluminum, copper, Titanium/aluminum/titanium, titanium/copper or combinations thereof. In this way, the interface oxide layer 162a can be formed between the second electrode TE and the second metal oxide layer 140a. In some embodiments, there is a Schottky contact between the first electrode BE and the second metal oxide layer 140a, and there is an ohmic contact between the second electrode TE and the second metal oxide layer 140a. In other embodiments, the material of the first electrode BE and the material of the second electrode TE can be used interchangeably. For example, the material of the first electrode BE is an active metal, while the material of the second electrode TE is an inactive metal. The present invention does not use This is the limit.

In one embodiment, the material of the gate G may be the same as the material of the first electrode BE, and the material of the source S and the drain D may be the same as the material of the second electrode TE, but the invention is not limited thereto. In other embodiments, the material of the gate G may be different from the material of the first electrode BE, and the materials of the source S and the drain D may be different from the material of the second electrode TE.

In one embodiment, the projected area of the second metal oxide layer 140a on the substrate 100 is substantially the same as the area of the top surface S1 of the first electrode BE, but the invention is not limited thereto. In other embodiments, the projected area of the second metal oxide layer 140a on the substrate 100 may be different from the area of the top surface S1 of the first electrode BE.

In this embodiment, the semiconductor device 10A includes an electrically connected thin film transistor T1 and a variable resistance memory R1, and the carrier concentration of the first metal oxide layer 110 of the thin film transistor T1 is greater than that of the variable resistance memory R1. The carrier concentration of the second metal oxide layer 140a of the memory R1 enables the variable resistance memory R1 to have excellent resistance switching performance. In some embodiments, the semiconductor device 10A can be disposed in the pixel circuit, thereby simplifying the overall system, reducing costs, and improving display quality.

FIG. 2 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. It must be noted here that the embodiment of FIG. 2 follows the component numbers and part of the content of the embodiment of FIG. 1 , where the same or similar numbers are used to represent the same or similar elements, and the description of the same technical content is omitted. For descriptions of omitted parts, reference may be made to the foregoing embodiments and will not be described again here.

Please refer to FIG. 2. The main difference between the semiconductor device 10B of FIG. 2 and the semiconductor device 10A of FIG. 1 is that the variable resistance memory R1 of the semiconductor device 10B includes a first electrode BE, a second metal oxide layer 140b and a second Electrode TE. The second metal oxide layer 140b is located between the first electrode BE and the second electrode TE, and the first electrode BE is closer to the substrate 100 than the second electrode TE. The second metal oxide layer 140b completely covers the top surface S1 and the sidewall S2 of the first electrode BE. In other words, the projected area of the second metal oxide layer 140b on the substrate 100 is larger than the area of the top surface S1 of the first electrode BE. In some embodiments, the first electrode BE is not in direct contact with the interlayer dielectric layer 150 .

FIG. 3 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. It must be noted here that the embodiment of FIG. 3 follows the component numbers and part of the content of the embodiment of FIG. 1 , where the same or similar numbers are used to represent the same or similar elements, and descriptions of the same technical content are omitted. For descriptions of omitted parts, reference may be made to the foregoing embodiments and will not be described again here.

Please refer to FIG. 3. The main difference between the semiconductor device 10C of FIG. 3 and the semiconductor device 10A of FIG. 1 is that the variable resistance memory R1 of the semiconductor device 10C includes a first electrode BE, a second metal oxide layer 140c and a second Electrode TE. No. The two-metal oxide layer 140c is located between the first electrode BE and the second electrode TE. The first electrode BE is closer to the substrate 100 than the second electrode TE. The second metal oxide layer 140c partially covers the top surface S1 of the first electrode BE, so that part of the top surface S1 of the first electrode BE does not overlap the second metal oxide layer 140c. In other words, the projected area of the second metal oxide layer 140c on the substrate 100 is smaller than the area of the top surface S1 of the first electrode BE.

FIG. 4 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. It must be noted here that the embodiment of FIG. 4 follows the component numbers and part of the content of the embodiment of FIG. 1 , where the same or similar numbers are used to represent the same or similar elements, and the description of the same technical content is omitted. For descriptions of omitted parts, reference may be made to the foregoing embodiments and will not be described again here.

Please refer to FIG. 4. The main difference between the semiconductor device 10D of FIG. 4 and the semiconductor device 10A of FIG. 1 is that the variable resistance memory R2 of the semiconductor device 10D includes a first electrode BE, a second metal oxide layer 140a and a second Electrode TE. The second metal oxide layer 140a is located between the first electrode BE and the second electrode TE. The first electrode BE is closer to the substrate 100 than the second electrode TE. The material of the first electrode BE is an active metal, such as titanium, titanium nitride, aluminum, copper, titanium/aluminum/titanium, titanium/copper or a combination thereof, and the material of the second electrode TE is an inactive metal, such as tungsten, Molybdenum, platinum, palladium, gold, molybdenum/aluminum/molybdenum or combinations thereof. In this way, the interface oxide layer 162b can be formed between the first electrode BE and the second metal oxide layer 140a. In some embodiments, there is a Schottky contact between the second electrode TE and the second metal oxide layer 140a, and there is an ohmic contact between the first electrode BE and the second metal oxide layer 140a.

5A to 5C are schematic cross-sectional views of a manufacturing process of a semiconductor device according to an embodiment of the present invention.

Referring to FIGS. 5A to 5C , a substrate 100 is provided, and a thin film transistor T1 and a variable resistive memory R1 are formed on the substrate 100 . For example, as shown in FIG. 5A , the buffer layer 102 can be formed on the substrate 100 first, and then the first metal oxide layer 110 can be formed on the buffer layer 102 .

Then, as shown in FIG. 5B , a gate dielectric layer 120 is formed on the first metal oxide layer 110 to cover the first metal oxide layer 110 . Subsequently, a first patterned conductive layer 130 is formed on the gate dielectric layer 120. The first patterned conductive layer 130 may include the gate electrode G and the first electrode BE. In other words, the material of the gate G and the first electrode BE may be the same. The first metal oxide layer 110 overlaps the gate G in the normal direction ND of the top surface of the substrate 100 . Next, a self-aligned process is used to perform a doping process P on the first metal oxide layer 110 that does not overlap the gate G, so as to form the source region 110b and the drain region 110a in the first metal oxide layer 110. The portion of the first metal oxide layer 110 overlapping the gate G forms the channel region 110c. In some embodiments, the doping process P includes a hydrogen plasma process.

Afterwards, as shown in FIG. 5C , a second metal oxide layer 140a is formed on the first electrode BE. The second metal oxide layer 140a may completely cover the top surface S1 of the first electrode BE, but the present invention is not limited thereto. In other embodiments, the second metal oxide layer 140a may also completely cover the top surface S1 and sidewall S2 of the first electrode BE. Alternatively, the second metal oxide layer 140a may only partially cover the top surface S1 of the first electrode BE.

Then, referring to FIG. 1 , an interlayer dielectric layer 150 is formed on the gate dielectric layer 120 to cover the gate electrode G, the second metal oxide layer 140 a and the first electrode BE. In some embodiments, the interlayer dielectric layer 150 is an insulating layer that does not contain hydrogen, thereby preventing hydrogen atoms in the interlayer dielectric layer 150 from diffusing into the first metal oxide layer 110 and the second metal oxide layer 140a.

Openings O1 and O2 are formed through the interlayer dielectric layer 150 and the gate dielectric layer 120 to respectively expose the source region 110b and the drain region 110a of the first metal oxide layer 110, and are formed through the interlayer dielectric layer 150. Open O3 to expose the second metal oxide layer 140a. In some embodiments, the openings O1, O2, and O3 are formed in one etching process, and the etching of the openings O1, O2, and O3 stops at the metal oxide layer. After that, a second patterned conductive layer 160 is formed on the interlayer dielectric layer 150 and filled in the openings O1, O2, and O3. The second patterned conductive layer 160 may include a source electrode S, a drain electrode D, and a second electrode TE. The source electrode S and the drain electrode D are filled in the openings O1 and O2 to be electrically connected to the first metal oxide layer 110, and the second electrode TE is filled in the opening O3 to be electrically connected to the second metal oxide layer 140a. In some embodiments, the source S is directly connected to the second electrode TE.

In one embodiment, during the process of forming the second patterned conductive layer 160, an interface oxide layer 162a may be formed between the second electrode TE and the second metal oxide layer 140a, but the invention is not limited thereto. . In other embodiments, after the second metal oxide layer 140a is formed, an interface oxide layer may be formed between the first electrode BE and the second metal oxide layer 140a (as shown in FIG. 4).

After the above process, the fabrication of the semiconductor device 10A can be substantially completed.

FIG. 6 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. It must be noted here that the embodiment of FIG. 6 follows the component numbers and part of the content of the embodiment of FIG. 1 , where the same or similar numbers are used to represent the same or similar elements, and the description of the same technical content is omitted. For descriptions of omitted parts, reference may be made to the foregoing embodiments and will not be described again here.

Please refer to FIG. 6 . The main difference between the semiconductor device 10E of FIG. 6 and the semiconductor device 10A of FIG. 1 is that the thin film transistor T2 of the semiconductor device 10E is a dual-gate thin film transistor. The thin film transistor T2 includes a first metal oxide layer 110, a first gate G, a source S, a drain D and a second gate G'. The first metal oxide layer 110 is disposed between the first gate G and the second gate G'.

In this embodiment, the current in the first metal oxide layer 110 is controlled by the first gate G and the second gate G', so that the thin film transistor T2 can allow a larger current to pass through.

FIG. 7 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. It must be noted here that the embodiment of FIG. 7 follows the component numbers and part of the content of the embodiment of FIG. 1 , where the same or similar numbers are used to represent the same or similar elements, and descriptions of the same technical content are omitted. For descriptions of omitted parts, reference may be made to the foregoing embodiments and will not be described again here.

Please refer to FIG. 7 . The main difference between the semiconductor device 10F of FIG. 7 and the semiconductor device 10A of FIG. 1 is that the thin film transistor T3 of the semiconductor device 10F is a bottom gate type thin film transistor.

Referring to FIG. 7, the semiconductor device 10F includes a substrate 100, a thin film transistor T3 and the variable resistance memory R3. The variable resistance memory R3 is electrically connected to the thin film transistor T3. In this embodiment, the semiconductor device 10F further includes a buffer layer 102 .

The thin film transistor T3 is disposed on the substrate 100 . The thin film transistor T3 includes a first metal oxide layer 110, a gate electrode G, a source electrode S and a drain electrode D. The gate G is disposed on the substrate 100 and the buffer layer 102 . The gate dielectric layer 120 is disposed on the buffer layer 102 and covers the gate electrode G. The first metal oxide layer 110 is disposed on the gate dielectric layer 120 , and the gate G overlaps the first metal oxide layer 110 in the normal direction ND of the top surface of the substrate 100 . The source S and the drain D are respectively disposed on two ends of the first metal oxide layer 110 to be electrically connected to the first metal oxide layer 110 . In some embodiments, an ohmic contact layer (not shown) is further included between the source S and the first metal oxide layer 110 and between the drain D and the first metal oxide layer 110 , but this is not the case in the present invention. is limited.

The variable resistance memory R3 includes a first electrode BE, a second metal oxide layer 140a and a second electrode TE. The first electrode BE is disposed on the buffer layer 102, the second metal oxide layer 140a is disposed on the first electrode BE, and the second electrode TE is disposed on the second metal oxide layer 140a. In other words, the second metal oxide layer 140a is located between the first electrode BE and the second electrode TE, and the first electrode BE is closer to the substrate 100 than the second electrode TE. The gate dielectric layer 120 covers the sidewalls of the first electrode BE and part of the top surface and sidewalls of the second metal oxide layer 140a. The opening O4 penetrates the gate dielectric layer 120 and overlaps a portion of the second metal oxide layer 140a. The second electrode TE fills the opening O4 to be electrically connected to the second metal oxide layer 140a. The second electrode TE can be connected with The source S of the thin film transistor T3 is directly connected. An interface oxide layer 162a may be formed between the second electrode TE and the second metal oxide layer 140a. In this embodiment, the carrier concentration of the first metal oxide layer 110 is greater than the carrier concentration of the second metal oxide layer 140a, so that the variable resistance memory R3 has excellent resistance switching performance.

8A to 8C are schematic cross-sectional views of a manufacturing process of a semiconductor device according to an embodiment of the present invention.

Referring to FIGS. 8A to 8C , a substrate 100 is provided, and a thin film transistor T3 and a variable resistive memory R3 are formed on the substrate 100 . For example, as shown in FIG. 8A , the buffer layer 102 can be formed on the substrate 100 first, and then the first patterned conductive layer 130 can be formed on the buffer layer 102 . The first patterned conductive layer 130 can include the gate electrode G. and the first electrode BE. In other words, the material of the gate G and the first electrode BE may be the same. Then, a second metal oxide layer 140a is formed on the first electrode BE. The second metal oxide layer 140a may completely cover the top surface S1 of the first electrode BE, but the present invention is not limited thereto. In other embodiments, the second metal oxide layer 140a may also completely cover the top surface S1 and sidewall S2 of the first electrode BE. Alternatively, the second metal oxide layer 140a may only partially cover the top surface S1 of the first electrode BE.

Afterwards, as shown in FIG. 8B , a gate dielectric layer 120 is formed on the first patterned conductive layer 130 to cover the gate G, the first electrode BE and the second metal oxide layer 140 a. Then, an opening O4 is formed through the gate dielectric layer 120 to expose the second metal oxide layer 140a.

After that, as shown in FIG. 8C , a first metal oxide layer 110 is formed on the gate dielectric. On top of the electrical layer 120 , a portion of the first metal oxide layer 110 overlaps the gate G in the normal direction ND of the top surface of the substrate 100 .

In this embodiment, the doping process may not be performed on the first metal oxide layer 110 so that the subsequently formed thin film transistor is a junctionless transistor.

Then, as shown in FIG. 7 , a second patterned conductive layer 160 is formed on the gate dielectric layer 120 . The second patterned conductive layer 160 may include a source electrode S, a drain electrode D, and a second electrode TE. The source S and the drain D are directly connected to both ends of the first metal oxide layer 110 respectively, and the second electrode TE fills the opening O4 to be electrically connected to the second metal oxide layer 140a. The source S is directly connected to the second electrode TE. In one embodiment, the step of forming the second patterned conductive layer 160 is, for example, conformally forming a conductive material layer (not shown) on the first metal oxide layer 110 and the gate dielectric layer 120, and then etching The process removes part of the conductive material layer to form the second patterned conductive layer 160. During the etching process, the surface of the first metal oxide layer 110 may also be partially removed. That is to say, the semiconductor device 10F of this embodiment may be a back channel etching (BCE) type thin film transistor.

In one embodiment, during the process of forming the second patterned conductive layer 160, an interface oxide layer 162a may be formed between the second electrode TE and the second metal oxide layer 140a, but the invention is not limited thereto. . In other embodiments, after the second metal oxide layer 140a is formed, an interface oxide layer may be formed between the first electrode BE and the second metal oxide layer 140a.

After the above process, the fabrication of the semiconductor device 10F can be substantially completed.

FIG. 9 is an equivalent circuit diagram of a pixel circuit according to an embodiment of the present invention.

Referring to FIG. 9 , the pixel circuit PX may include a switching transistor Tsw, a compensation memory Rc, a writing transistor Twr, a storage capacitor Cst, a driving transistor Tdr, a sensing transistor Tse, and a light-emitting element EL.

The gate of the switching transistor Tsw is electrically connected to the voltage V _S1 (for example, the scan line voltage), the drain of the switching transistor Tsw is electrically connected to the voltage V _data (for example, the data line voltage), and the source of the switching transistor Tsw The electrode is electrically connected to one end of the compensation memory Rc (for example, the second electrode TE). The switching transistor Tsw and the compensation memory Rc can be, for example, the thin film transistors T1, T2, and T3 and the variable resistance memories R1, R2, and R3 in any of the aforementioned embodiments. Their structures can be understood with reference to the aforementioned embodiments. The other end of the compensation memory Rc (eg, the first electrode BE) may be electrically connected to the first node a. The voltage V _S1 is used to control the switching of the switching transistor Tsw, and the compensation memory Rc is used to compensate for the voltage offset generated by the driving transistor Tdr under long-term operation.

The gate of the writing transistor Twr is electrically connected to the voltage _VR , the drain of the writing transistor Twr is electrically connected to the first node a, and the source of the writing transistor Twr is connected to the voltage V _com . The write transistor Twr can be used to write pixel compensation information, and the voltage _VR is used to control the switch of the write transistor Twr.

One end of the storage capacitor Cst is electrically connected to the second node b, and the other end of the storage capacitor Cst is electrically connected to the third node c. The first node a and the second node b are electrically connected.

The gate of the driving transistor Tdr is electrically connected to the second node b, the drain of the driving transistor Tdr is electrically connected to the voltage V _DD , and the source of the driving transistor Tdr is electrically connected to the third node c. Since the gate of the driving transistor Tdr is electrically connected to the storage capacitor Cst, even if the switching transistor Tsw is turned off, the driving transistor Tdr can still continue to conduct for a short period of time.

The gate of the sensing transistor Tse is electrically connected to the voltage V _S2 , the drain of the sensing transistor Tse is electrically connected to the third node c, and the source of the sensing transistor Tse is electrically connected to the voltage V _sus . The voltage V _S2 is used to control the switch of the sensing transistor Tse to transmit the driving current information to an external chip (not shown) through the sensing transistor Tse.

One end of the light-emitting element EL is electrically connected to the third node c, and the other end of the light-emitting element EL is electrically connected to the voltage V _SS . The brightness of the light-emitting element EL will change due to the different magnitude of the driving current passing through the driving transistor Tdr. The light-emitting element EL is, for example, a micro-light-emitting diode, an organic light-emitting diode or other light-emitting elements.

FIG. 10 is a flow chart of a pixel compensation operation of a display device under the pixel circuit configuration of FIG. 9 according to an embodiment of the present invention.

The following is a brief description of the pixel compensation operation method of the display device under the setting of the pixel circuit PX. Please refer to Figure 9 and Figure 10 at the same time. First, the display device is in a closed state, allowing the pixel circuit PX to perform gray level sensing in the background. The grayscale sensing method is, for example, turning on the driving transistor Tdr and the sensing transistor Tse, so that the driving current passing through the driving transistor Tdr can be transmitted to the external chip through the sensing transistor Tse. In some embodiments, during the grayscale sensing process, the write transistor Twr is in an off state.

Then, the external chip creates the corresponding model through signal processing and calculation. Then the corresponding compensation information is calculated. After that, the compensation information is written into the pixel circuit PX. For example, the writing transistor Twr and the switching transistor Tsw are turned on, so that the compensation information calculated by the external chip is written into the compensation memory Rc in the pixel circuit PX by controlling the switching transistor Tsw and the writing transistor Twr. Specifically, the resistance of the compensation memory Rc changes due to the voltage difference between the first electrode BE and the second electrode TE. When the voltage difference between the first electrode BE and the second electrode TE is large, more carrier channels will be generated in the second metal oxide layer between the first electrode BE and the second electrode TE, causing the compensation memory to Body Rc is in a low resistance state. When the voltage difference between the first electrode BE and the second electrode TE is small, fewer carrier channels will be generated in the second metal oxide layer between the first electrode BE and the second electrode TE, so that the compensation memory Rc in a high resistance state. In some embodiments, the compensation memory Rc has a plurality of different resistance states (for example, a state with a resistance of 10E2 ohm, a state with a resistance of 10E3 ohm, a state with a resistance of 10E4 ohm, a state with a resistance of 10E5 ohm). Therefore, it can pass through The voltage difference between the first electrode BE and the second electrode TE is adjusted to change the resistance of the compensation memory Rc. In some embodiments, when the compensation information is written into the pixel circuit PX, the sensing transistor Tse is in an off state.

Next, turn on the display device. Since the compensation data has been written into the compensation memory Rc, the current reaching the gate of the driving transistor Tdr through the compensation memory Rc can be changed, thereby adjusting the size of the driving current through the driving transistor Tdr to achieve pixel compensation. Function. In some embodiments, when the display device is turned on, the writing transistor Twr and the sensing transistor Tse are in an off state. By arranging the compensation memory Rc in the pixel circuit PX, the present invention does not need to be installed in an external chip. Compensation memory is installed to simplify the overall system and reduce costs.

10A:Semiconductor device 100:Substrate 102:Buffer layer 110: First metal oxide layer 110a: drain area 110b: Source region 110c: Passage area 120: Gate dielectric layer 130: First patterned conductive layer 140a: Second metal oxide layer 150: Interlayer dielectric layer 162a: Interface oxide layer BE: first electrode D: drain G: gate ND: direction O1, O2, O3: opening R1: Variable resistance memory S: source S1: Top surface S2: side wall TE: second electrode T1: thin film transistor

Claims (12)

A semiconductor device includes: a substrate; a thin film transistor disposed on the substrate, wherein the thin film transistor includes a first metal oxide layer; and a variable resistance memory disposed on the substrate , and is electrically connected to the thin film transistor, wherein the variable resistance memory includes a second metal oxide layer, wherein the carrier concentration of the first metal oxide layer is greater than the carrier concentration of the second metal oxide layer. sub-concentration, wherein the materials of the first metal oxide layer and the second metal oxide layer include indium gallium zinc oxide, and the oxygen content of the first metal oxide layer is less than the oxygen content of the second metal oxide layer. The semiconductor device of claim 1, wherein the variable resistance memory further includes a first electrode and a second electrode, and the second metal oxide layer is located between the first electrode and the second electrode. , and the first electrode is closer to the substrate than the second electrode, wherein the material of the first electrode includes tungsten, molybdenum, platinum, palladium, gold, molybdenum/aluminum/molybdenum or a combination thereof, and the material of the second electrode Includes titanium, titanium nitride, aluminum, copper, titanium/aluminum/titanium, titanium/copper or combinations thereof. The semiconductor device according to claim 2, further comprising: an interface oxide layer located between the second electrode and the second metal oxide layer. The semiconductor device of claim 1, wherein the variable resistance memory further includes a first electrode and a second electrode, and the second metal oxide layer is located between the first electrode and the second electrode. , and the first electrode is closer to the substrate than the second electrode, wherein the material of the first electrode includes titanium, titanium nitride, aluminum, copper, titanium/aluminum/titanium, titanium/copper or a combination thereof, and the second electrode Materials of the electrodes include tungsten, molybdenum, platinum, palladium, gold, molybdenum/aluminum/molybdenum, or combinations thereof. The semiconductor device of claim 4, further comprising: an interface oxide layer located between the first electrode and the second metal oxide layer. The semiconductor device of claim 1, wherein the thin film transistor further includes: a gate overlapping the first metal oxide layer, wherein a gate dielectric layer is disposed between the gate and the first metal oxide. between layers; and a source electrode and a drain electrode, respectively electrically connected to the first metal oxide layer, wherein the source electrode is electrically connected to the variable resistance memory. The semiconductor device of claim 6, further comprising: an interlayer dielectric layer disposed on the gate dielectric layer, and the interlayer dielectric layer covers the gate electrode, the first metal oxide layer and the third Two metal oxide layers, wherein the materials of the interlayer dielectric layer and the gate dielectric layer are hydrogen-free oxides. A method of manufacturing a semiconductor device, including: providing a substrate; forming a thin film transistor and a variable resistance memory on the substrate, wherein the thin film transistor includes a first metal oxide layer, and the variable resistance memory includes a second metal oxide layer, wherein the thin film transistor is electrically connected to the variable resistance memory, and the third The carrier concentration of a metal oxide layer is greater than the carrier concentration of the second metal oxide layer, wherein the materials of the first metal oxide layer and the second metal oxide layer include indium gallium zinc oxide, and the first The oxygen content of the metal oxide layer is less than the oxygen content of the second metal oxide layer. The manufacturing method of a semiconductor device according to claim 8, wherein the step of forming the thin film transistor and the variable resistance memory on the substrate includes: forming the first metal oxide layer on the substrate; forming A gate dielectric layer is formed on the first metal oxide layer; a first patterned conductive layer is formed on the gate dielectric layer, wherein the first patterned conductive layer includes a gate and a first electrode , and the first metal oxide layer overlaps the gate in the normal direction of the top surface of the substrate; forming the second metal oxide layer on the first electrode; forming an interlayer dielectric layer on the gate on the dielectric layer and covering the gate and the second metal oxide layer; forming a second patterned conductive layer on the interlayer dielectric layer, wherein the second patterned conductive layer includes a source electrode, a drain electrode and a second electrode, wherein the source electrode and the drain electrode are electrically connected to the first metal oxide layer, and the second electrode is electrically connected to the second metal oxide layer. The method of manufacturing a semiconductor device according to claim 9, wherein during the formation of the second patterned conductive layer, an interface oxide layer is formed between the second electrode and the second metal oxide layer. The method of manufacturing a semiconductor device according to claim 9, wherein after forming the second metal oxide layer, an interface oxide layer is formed between the first electrode and the second metal oxide layer. The manufacturing method of a semiconductor device according to claim 8, wherein the step of forming the thin film transistor and the variable resistance memory on the substrate includes: forming a first patterned conductive layer on the substrate, wherein The first patterned conductive layer includes a gate and a first electrode; forming the second metal oxide layer on the first electrode; forming a gate dielectric layer on the first patterned conductive layer; forming The first metal oxide layer is on the gate dielectric layer, and the first metal oxide layer overlaps the gate electrode in the normal direction of the top surface of the substrate; forming a second patterned conductive layer on On the gate dielectric layer, the second patterned conductive layer includes a source electrode, a drain electrode and a second electrode, wherein the source electrode and the drain electrode are electrically connected to the first metal oxide layer, And the second electrode is electrically connected to the second metal oxide layer.

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