TWI880669B - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

A semiconductor device includes a first electrode, a first isolation structure, a second electrode, a second isolation structure, a third electrode, an oxide semiconductor structure, a native oxide layer, a gate dielectric layer and a gate electrode. The first electrode, the first isolation structure, the second electrode, the second isolation structure and the third electrode are stacked in sequence. The second electrode includes at least one of hafnium, titanium, beryllium, aluminum, silicon, and calcium. The oxide semiconductor structure extends from the top surface of the third electrode to the top surface of the first electrode, and contacts a side surface of the first isolation structure and a side surface of the second isolation structure. The native oxide layer includes an oxide of at least one of hafnium, titanium, beryllium, aluminum, silicon, manganese, chromium, vanadium and calcium, and is laterally located between the second electrode and the oxide semiconductor structure.

Description

Semiconductor device and method for manufacturing the same

The present invention relates to a semiconductor device and a method for manufacturing the same.

With the rapid development of technology, the resolution of display devices has been increasing year by year. In order to manufacture higher resolution display devices, it is urgent to reduce the size of semiconductor components in the device, such as the size of thin film transistors. Generally, the structure of thin film transistors includes a gate, a semiconductor channel layer, a source, and a drain. Among them, the function of the gate is to control the carriers in the semiconductor channel layer, thereby determining whether the current can flow between the source and the drain.

In order to reduce the size of thin film transistors, the channel length and/or channel width of the semiconductor channel layer must be reduced. However, such size reduction also brings a series of challenges. Reducing the size of the semiconductor channel layer may lead to insufficient on current of the thin film transistor, or even fail to meet the external quantum efficiency (EQE) requirements of the light-emitting diode. Therefore, there is an urgent need for a method that can maintain or even increase the on current of semiconductor devices while reducing the size of semiconductor devices.

The present invention provides a semiconductor device and a manufacturing method thereof, which have the advantage of high driving current.

At least one embodiment of the present invention provides a semiconductor device, which includes a first electrode, a first isolation structure, a second electrode, a second isolation structure, a third electrode, an oxide semiconductor structure, a native oxide layer, a gate dielectric layer, and a gate. The first isolation structure is located on the first electrode. The second electrode is located on the first isolation structure. The second electrode includes at least one of cobalt, titanium, curium, aluminum, silicon, manganese, chromium, vanadium, and calcium. The second isolation structure is located on the second electrode. The third electrode is located on the second isolation structure. The first electrode, the first isolation structure, the second electrode, the second isolation structure, and the third electrode are stacked in sequence. The oxide semiconductor structure extends from the top surface of the third electrode to the top surface of the first electrode, and contacts the side surface of the first isolation structure and the side surface of the second isolation structure. The native oxide layer includes an oxide of at least one of cobalt, titanium, curium, aluminum, silicon, manganese, chromium, vanadium and calcium, and is laterally located between the second electrode and the oxide semiconductor structure. The gate dielectric layer is located on the oxide semiconductor structure. The gate is located on the gate dielectric layer.

At least one embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising the following steps: forming a first isolation material layer on a first electrode; forming a first electrode material layer on the first isolation material layer, wherein the first electrode material layer includes at least one of bismuth, titanium, beryllium, aluminum, silicon, manganese, chromium, vanadium and calcium; forming a second isolation material layer on the first electrode material layer; forming a second electrode material layer on the second isolation material layer; and forming a patterned photoresist layer on the second electrode material layer. Perform one or more etching processes to pattern the second electrode material layer, the second isolation material layer, the first electrode material layer and the first isolation material layer to form a third electrode, a second isolation structure, a second electrode and a first isolation structure, respectively, wherein the first electrode, the first isolation structure, the second electrode, the second isolation structure and the third electrode are stacked in sequence. Form an oxide semiconductor structure on the third electrode, and the oxide semiconductor structure extends from the top surface of the third electrode to the top surface of the first electrode. Diffusion of oxygen elements in the oxide semiconductor structure into the second electrode to form a native oxide layer on the second electrode. Form a gate dielectric layer on the oxide semiconductor structure. A gate is formed on the gate dielectric layer.

10A, 10B, 10C, 10D, 10E: Semiconductor devices

100: Substrate

110,110C: First isolation structure

110m, 110Cm: first isolation material layer

110s,120s: Side

120,120C: Second isolation structure

120m, 120Cm: Second isolation material layer

120C’: Intermediate isolation layer

140,140C: Native oxide layer

150: Gate dielectric layer

210: First electrode

210t,230t:Top

220,220C: Second electrode

220m, 220Cm: first electrode material layer

230,230C: Third electrode

230m, 230Cm: Second electrode material layer

240: Gate

300,300C,300D: oxide semiconductor structure

302,312: First channel area

304,314: Conductive area

306,316: Second channel area

310D: First semiconductor layer

320D: Second semiconductor layer

330D: The third semiconductor layer

H1: First through hole

H2: Second through hole

PR: Patterned photoresist layer

t1,t2,t3,t4,t5: thickness

FIG1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

Figures 2A to 2G are cross-sectional schematic diagrams of a method for manufacturing the semiconductor device of Figure 1.

FIG3A is a schematic top view of a semiconductor device according to an embodiment of the present invention.

FIG3B is a schematic cross-sectional view along line A-A’ of FIG3A .

FIG4 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

Figures 5A to 5H are cross-sectional schematic diagrams of a method for manufacturing the semiconductor device of Figure 4.

FIG6 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

FIG7 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

FIG8A is a schematic cross-sectional view of a simulation structure of a semiconductor device according to an embodiment of the present invention.

Figure 8B is a partial enlarged view of the virtual frame position in Figure 8A.

FIG9A and FIG9B are data diagrams of gate voltage (Vg) and current (Id) of the simulation structure of the semiconductor device of FIG8A and FIG8B.

FIG10A is a schematic cross-sectional view of a simulation structure of a semiconductor device according to an embodiment of the present invention.

Figure 10B is a partial enlarged view of the virtual frame position in Figure 10A.

FIG. 11A and FIG. 11B are data diagrams of gate voltage (Vg) and current (Id) of the simulation structure of the semiconductor device of FIG. 10A and FIG. 10B.

FIG1 is a cross-sectional schematic diagram of a semiconductor device 10A according to an embodiment of the present invention. Referring to FIG1 , the semiconductor device 10A includes a first electrode 210, a first isolation structure 110, a second electrode 220, a second isolation structure 120, a third electrode 230, an oxide semiconductor structure 300, a native oxide layer 140, a gate dielectric layer 150, and a gate 240.

In this embodiment, the first electrode 210, the first isolation structure 110, the second electrode 220, the second isolation structure 120, the third electrode 230, the oxide semiconductor structure 300, the gate dielectric layer 150 and the gate 240 are sequentially stacked on the substrate 100. By designing the stacking structure, the effective channel length of the oxide semiconductor structure 300 can be reduced, and the size of the semiconductor device 10A can be reduced.

The substrate 100 is, for example, a rigid substrate, and its material may be glass, quartz, organic polymer or opaque/reflective material (e.g., conductive material, metal, wafer, ceramic or other applicable material) or other applicable materials. However, the present invention is not limited thereto. In other embodiments, the substrate 100 may also be a flexible substrate or a stretchable substrate. For example, the materials of the flexible substrate and the stretchable substrate include polyimide (PI), polydimethylsiloxane (PDMS), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyester (PES), polymethylmethacrylate (PMMA), polycarbonate (PC), polyurethane PU or other suitable materials.

The first electrode 210 is located on the substrate 100. In the present embodiment, the first electrode 210 directly contacts the top surface of the substrate 100, but the present invention is not limited thereto. In other embodiments, a buffer layer (not shown) may be additionally included between the first electrode 210 and the substrate 100. The buffer layer may include, for example, silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride or other suitable materials or a combination of the foregoing materials or a stack of the foregoing materials. In some embodiments, the buffer layer is used, for example, as a hydrogen barrier layer and/or a metal ion barrier layer. In some embodiments, the first electrode 210 may have a single-layer structure or a multi-layer structure.

The first isolation structure 110 is located on the first electrode 210. The first isolation structure 110 partially overlaps the first electrode 210. Specifically, a portion of the top surface 210t of the first electrode 210 is covered by the first isolation structure 110, while another portion of the top surface 210t is not covered by the first isolation structure 110. In some embodiments, the thickness t1 of the first isolation structure 110 is 30 nanometers to 300 nanometers.

The second electrode 220 is located on the first isolation structure 110. The material of the second electrode 220 includes at least one of uranium, titanium, curium, aluminum, silicon, manganese, chromium, vanadium and calcium. In some embodiments, when the material of the second electrode 220 includes silicon, the second electrode 220 is optionally subjected to a doping process so that the second electrode 220 includes doped silicon. In some embodiments, the thickness t2 of the second electrode 220 is 10 nanometers to 100 nanometers. In some embodiments, the second electrode 220 includes a conductive material and can be used as a bottom gate, but the present invention is not limited thereto. In other embodiments, the second electrode 220 includes an insulating material. In some embodiments, the second electrode 220 is a floating electrode (or a virtual electrode).

The second isolation structure 120 is located on the second electrode 220. The second electrode 220 is sandwiched between the first isolation structure 110 and the second isolation structure 120. In some embodiments, the thickness t3 of the second isolation structure 120 is 30 nanometers to 300 nanometers. In this embodiment, the thickness t2 of the second electrode 220 is less than the thickness t1 of the first isolation structure 110 and the thickness t3 of the second isolation structure 120, but the present invention is not limited thereto. In other embodiments, the thickness t2 of the second electrode 220 is greater than or equal to the thickness t1 of the first isolation structure 110 and the thickness t3 of the second isolation structure 120.

In some embodiments, the materials of the first isolation structure 110 and the second isolation structure 120 include, for example, organic insulating materials, silicon oxide, silicon oxynitride, silicon nitride, aluminum oxide, einsteinium oxide, zirconium oxide or other suitable materials or combinations of the foregoing materials. In some embodiments, the materials of the first isolation structure 110 and the second isolation structure 120 include oxides (e.g., silicon oxide) and can be used as oxygen storage/oxygen replenishing layers, thereby adjusting the oxygen concentration in the oxide semiconductor structure 300 during the manufacturing process. In some embodiments, the first isolation structure 110 and the second isolation structure 120 can each have a single-layer structure or a multi-layer structure. When the first isolation structure 110 and the second isolation structure 120 each have a multi-layer structure, an oxide layer (such as a silicon oxide layer) and a nitride layer (such as a silicon nitride layer) can be used in combination to optimize the performance of the semiconductor device 10A. For example, the oxide layer can be used as an oxygen storage/oxygen replenishment layer, and the nitride layer can be used as a hydrogen barrier layer or a metal ion barrier layer.

The third electrode 230 is located on the second isolation structure 120. In some embodiments, the side surface of the third electrode 230 is aligned with the side surface 120s of the second isolation structure 120. In some embodiments, the third electrode 230 may have a single-layer structure or a multi-layer structure.

The oxide semiconductor structure 300 extends from the top surface 230t of the third electrode 230 to the top surface 210t of the first electrode 210 and contacts the side surface 110s of the first isolation structure 110 and the side surface 120s of the second isolation structure 120.

In some embodiments, the material of the oxide semiconductor structure 300 includes an oxide containing two or more of gallium (Ga), zinc (Zn), indium (In), tin (Sn), aluminum (Al), and tungsten (W) (e.g., metal oxides such as indium gallium zinc tin oxide (IGZTO), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), aluminum zinc tin oxide (AZTO), indium tungsten zinc oxide (IWZO), indium gallium oxide (InGO), and indium tungsten oxide (InWO)) or a rare earth doped metal oxide (e.g., Ln-IZO) or other suitable metal oxides or a combination of the above materials. The oxide semiconductor structure 300 has a single-layer structure or a multi-layer structure. In some embodiments, the thickness t4 of the oxide semiconductor structure 300 on the side surface 110s and the side surface 120s is 10 nm to 100 nm.

A native oxide layer 140 is included between the oxide semiconductor structure 300 and the second electrode 220. The native oxide layer 140 includes an oxide of at least one of cobalt, titanium, curium, aluminum, silicon, manganese, chromium, vanadium, and calcium, and is laterally located between the second electrode 220 and the oxide semiconductor structure 300. In some embodiments, the second electrode 220 is used as an oxygen absorption layer, and during the process of manufacturing the semiconductor device 10A, oxygen elements in the oxide semiconductor structure 300 diffuse into the second electrode 220, and the second electrode 220 is oxidized to form the native oxide layer 140. The standard Gibbs free energy of formation of the material of the native oxide layer 140 is lower than the standard Gibbs free energy of formation of the material of the oxide semiconductor structure 300, thus facilitating the spontaneous formation of the native oxide layer 140 during the process of manufacturing the semiconductor device 10A. In some embodiments, the standard Gibbs free energy of formation of the material of the native oxide layer 140 is lower than -1000 KJ mol ^-1 , for example, -1000 KJ mol ^-1 to -2000 KJ mol ^-1 . In some embodiments, the thickness t5 of the native oxide layer 140 is 10 nm to 100 nm.

During the process of forming the native oxide layer 140, the material of the second electrode 220 is a reducing agent, and absorbs part of the oxygen in the oxide semiconductor structure 300 to form a conductive region 304 in the oxide semiconductor structure 300. After the native oxide layer 140 is formed, the oxide semiconductor structure 300 includes a first channel region 302, a conductive region 304 (also known as an n+ doped region), and a second channel region 306. The first channel region 302, the conductive region 304, and the second channel region 306 contact the first isolation structure 110, the native oxide layer 140, and the second isolation structure 120, respectively. The conductive region 304 is sandwiched between the first channel region 302 and the second channel region 306. In some embodiments, the oxygen concentration of the conductive region 304 is lower than the oxygen concentration of the first channel region 302 and the oxygen concentration of the second channel region 306, and the carrier concentration of the conductive region 304 is higher than the carrier concentration of the first channel region 302 and the carrier concentration of the second channel region 306. The resistivity of the conductive region 304 is lower than the resistivity of the first channel region 302 and the resistivity of the second channel region 306.

In some embodiments, the material of the first electrode 210 and the third electrode 230 is different from the material of the second electrode 220. For example, compared with the material of the second electrode 220, the materials of the first electrode 210 and the third electrode 230 are less likely to react with the oxygen element in the oxide semiconductor structure 300 to form a native oxide layer (for example, the standard Gibbs free energy of formation of the formed native oxide layer is higher than the standard Gibbs free energy of formation of the material of the oxide semiconductor structure 300 or the native oxide layer 140). Therefore, no native oxide layer will be formed at the interface between the oxide semiconductor structure 300 and the first electrode 210 and at the interface between the oxide semiconductor structure 300 and the third electrode 230 (or only a native oxide layer thinner than the native oxide layer 140 will be formed), and the oxide semiconductor structure 300 will not be electrically separated from the native oxide layer of the first electrode 210 or the third electrode 230). Based on this, a native oxide layer 140 that can electrically insulate the oxide semiconductor structure 300 from the second electrode 220 can be formed while maintaining the electrical connection between the oxide semiconductor structure 300 and the first electrode 210 and the electrical connection between the oxide semiconductor structure 300 and the third electrode 230.

In some embodiments, the materials of the first electrode 210 and the third electrode 230 include materials with large free energy such as tin, copper, molybdenum, nickel, or conductive oxides (such as indium tin oxide or other conductive oxide materials with free energy similar to that of the oxide semiconductor structure 300) or other suitable materials. In some embodiments, one of the first electrode 210 and the third electrode 230 is used as a source, and the other is used as a drain.

The gate dielectric layer 150 is located on the oxide semiconductor structure 300. In some embodiments, the material of the gate dielectric layer 150 includes silicon oxide, silicon oxynitride, silicon nitride, aluminum oxide, vanadium oxide, zirconium oxide or other suitable materials or a combination of the foregoing materials.

The gate 240 is located on the gate dielectric layer 150 and overlaps the oxide semiconductor structure 300. In some embodiments, the conductive region 304 and the native oxide layer 140 are laterally located between the gate 240 and the second electrode 220. In some embodiments, the gate 240 is electrically connected to the second electrode 220 using other conductive connection layers (not shown) or conductive vias (not shown), and the second electrode 220 and the gate 240 can be used as a bottom gate and a top gate, respectively, but the present invention is not limited thereto. In other embodiments, the second electrode 220 includes an insulating material, and the second electrode 220 is electrically separated from the gate 240.

In some embodiments, the material of the gate 240 includes, for example, metals such as chromium, gold, silver, copper, tin, lead, uranium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, nickel, alloys of the above metals, oxides of the above metals, nitrides of the above metals, or combinations thereof or other conductive materials. The gate 240 may have a single-layer structure or a multi-layer structure.

2A to 2G are cross-sectional schematic diagrams of a method for manufacturing the semiconductor device 10A of FIG. 1. Referring to FIG. 2A, a first isolation material layer 110m is formed on a first electrode 210. A first electrode material layer 220m is formed on the first isolation material layer 110m, wherein the first electrode material layer 220m includes at least one of cobalt, titanium, beryllium, aluminum, silicon, manganese, chromium, vanadium and calcium. A second isolation material layer 120m is formed on the first electrode material layer 220m. A second electrode material layer 230m is formed on the second isolation material layer 120m. A patterned photoresist layer PR is formed on the second electrode material layer 230m.

Referring to FIG. 2B and FIG. 2C , one or more etching processes are performed to pattern the second electrode material layer 230m, the second isolation material layer 120m, the first electrode material layer 220m, and the first isolation material layer 110m to form the third electrode 230, the second isolation structure 120, the second electrode 220, and the first isolation structure 110, respectively. The first electrode 210, the first isolation structure 110, the second electrode 220, the second isolation structure 120, and the third electrode 230 are stacked in sequence. In some embodiments, the one or more etching processes include dry etching, wet etching, or a combination thereof.

In this embodiment, the side surface 110s of the first isolation structure 110, the side surface of the second electrode 220, the side surface 120s of the second isolation structure 120, and the side surface of the third electrode 230 are aligned with each other.

Please refer to Figure 2D to remove the patterned photoresist layer PR.

Referring to FIG. 2E , an oxide semiconductor structure 300 is formed on the third electrode 230 , and the oxide semiconductor structure 300 extends from the top surface 230t of the third electrode 230 to the top surface 210t of the first electrode 210 .

Please refer to FIG. 2F , the oxygen element in the oxide semiconductor structure 300 is diffused into the second electrode 220 to form a native oxide layer 140 on the second electrode 220. The native oxide layer 140 is formed at the interface between the second electrode 220 and the oxide semiconductor structure 300. While forming the native oxide layer 140, a conductive region 304 with a higher carrier concentration is formed in the oxide semiconductor structure 300. The conductive region 304 connects the first channel region 302 and the second channel region 306.

In some embodiments, the native oxide layer 140 and the conductive region 304 are spontaneously formed during the deposition of the oxide semiconductor structure 300, but the present invention is not limited thereto. In other embodiments, additional heat treatment processes are performed to promote the diffusion of oxygen in the oxide semiconductor structure 300 into the second electrode 220.

Referring to FIG. 2G , a gate dielectric layer 150 is formed on the oxide semiconductor structure 300. In this embodiment, before forming the gate dielectric layer 150, a native oxide layer 140 has been formed between the oxide semiconductor structure 300 and the second electrode 220, but the present invention is not limited thereto. In other embodiments, after forming the gate dielectric layer 150 or during the process of forming the gate dielectric layer 150, oxygen in the oxide semiconductor structure 300 is diffused into the second electrode 220 to form the native oxide layer 140 and the conductive region 304.

In some embodiments, the materials of the first isolation structure 110 and the second isolation structure 120 include oxide (e.g., silicon oxide). In some embodiments, after forming the gate dielectric layer 150, an additional heat treatment process is performed to diffuse the oxygen elements in the first isolation structure 110 and the second isolation structure 120 into the oxide semiconductor structure 300 (e.g., diffuse into the first channel region 302 and the second channel region 306), thereby reducing the oxygen vacancy concentration in the first channel region 302 and the second channel region 306, thereby increasing the resistivity of the first channel region 302 and the second channel region 306, and reducing the leakage problem between the first electrode 210 and the third electrode 230.

Finally, please return to FIG. 1 to form a gate 240 on the gate dielectric layer 150. At this point, the semiconductor device 10A is substantially completed.

FIG3A is a schematic top view of a semiconductor device 10B according to an embodiment of the present invention. FIG3B is a schematic cross-sectional view along line A-A' of FIG3A. It must be noted that the embodiments of FIG3A and FIG3B use the component numbers and partial contents of the embodiments of FIG1 to FIG2G, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, which will not be elaborated here.

Please refer to FIG. 3A and FIG. 3B. In this embodiment, the first isolation structure 110 includes a first through hole H1, and the second isolation structure 120 includes a second through hole H2. The first through hole H1 overlaps the second through hole H2. The semiconductor structure 300 is filled in the first through hole H1 and the second through hole H2. In this embodiment, the native oxide layer 140 has a ring structure and surrounds the conductive region 304 of the semiconductor structure 300.

In this embodiment, the second electrode 220 includes a conductive material or an insulating material, and the second electrode 220 is a floating electrode (or a virtual electrode). In other words, no signal line is used to directly provide a voltage to the second electrode 220.

FIG. 4 is a cross-sectional schematic diagram of a semiconductor device 10C according to an embodiment of the present invention. It must be noted that the embodiment of FIG. 4 uses the component numbers and partial contents of the embodiments of FIG. 1 to FIG. 2G, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, which will not be elaborated here.

The main difference between the semiconductor device 10C of FIG. 4 and the semiconductor device 10A of FIG. 1 is that in the semiconductor device 10A, the side surface of the second electrode 220 is aligned with the side surface 120s of the second isolation structure 120. However, in the semiconductor device 10C, the side surface of the second electrode 220C exceeds the side surface 120s of the second isolation structure 120.

Referring to FIG. 4 , in the semiconductor device 10C, the first electrode 210, the first isolation structure 110C, the second electrode 220C, the second isolation structure 120C, the third electrode 230C, the oxide semiconductor structure 300C, the gate dielectric layer 150 and the gate 240 are sequentially stacked on the substrate 100. The second electrode 220C extends beyond the side surface 120s of the second isolation structure 120C.

The conductive region 304 of the oxide semiconductor structure 300C is located between the top surface of the second electrode 220C and the gate dielectric layer 150 and between the side surface of the second electrode 220C and the gate dielectric layer 150. The native oxide layer 140C is formed on the top surface of the second electrode 220C and the side surface of the second electrode 220C.

In this embodiment, the thickness t5 of the native oxide layer 140C is less than the thickness t2 of the second electrode 220C, and the native oxide layer 140C has a stepped structure, but the present invention is not limited thereto. In other embodiments, the thickness t5 of the native oxide layer 140C is equal to the thickness t2 of the second electrode 220C.

5A to 5H are cross-sectional schematic diagrams of a method for manufacturing the semiconductor device 10C of FIG4. Referring to FIG5A, a first isolation material layer 110Cm is formed on the first electrode 210. A first electrode material layer 220Cm is formed on the first isolation material layer 110Cm, wherein the first electrode material layer 220Cm includes at least one of cobalt, titanium, beryllium, aluminum, silicon, manganese, chromium, vanadium and calcium. A second isolation material layer 120Cm is formed on the first electrode material layer 220Cm. A second electrode material layer 230Cm is formed on the second isolation material layer 120Cm. A patterned photoresist layer PR is formed on the second electrode material layer 230cm.

Please refer to Figures 5B to 5E, perform one or more etching processes to pattern the second electrode material layer 230Cm, the second isolation material layer 120Cm, the first electrode material layer 220Cm and the first isolation material layer 110Cm to form the third electrode 230C, the second isolation structure 120C, the second electrode 220C and the first isolation structure 110C respectively. The first electrode 210, the first isolation structure 110C, the second electrode 220C, the second isolation structure 120C and the third electrode 230C are stacked in sequence.

First, a first etching process is performed on the second electrode material layer 230Cm using the patterned photoresist layer PR as a mask to form a third electrode 230C, as shown in FIG5B. In some embodiments, the first etching process includes a wet etching process, and after performing the first etching process, the side surface of the third electrode 230C is retracted to the side surface of the patterned photoresist layer PR.

Next, referring to FIG. 5C , a second etching process is performed on the second isolation material layer 120Cm using the patterned photoresist layer PR and the third electrode 230C as a mask to form an intermediate isolation layer 120C’. In some embodiments, the second etching process includes a dry etching process. Since the side surface of the third electrode 230C is inwardly oriented to the side surface of the patterned photoresist layer PR, the width of the intermediate isolation layer 120C’ formed is greater than the width of the third electrode 230C.

Next, please refer to FIG. 5D , the first electrode material layer 220Cm is subjected to a third etching process using the patterned photoresist layer PR, the third electrode 230C, and the intermediate isolation layer 120C' as a mask to form the second electrode 220C. In some embodiments, the third etching process includes a dry etching process, and since the side surface of the third electrode 230C is inwardly oriented to the side surface of the patterned photoresist layer PR, the width of the formed second electrode 220C is greater than the width of the third electrode 230C.

Finally, referring to FIG. 5E , the patterned photoresist layer PR is removed, and the third electrode 230C and the second electrode 220C are used as masks to perform a fourth etching process on the intermediate isolation layer 120C' and the first isolation material layer 110Cm to form the second isolation structure 120C and the first isolation structure 110C. In some embodiments, the fourth etching process includes a dry etching process. In this embodiment, the side surface of the third electrode 230C is aligned with the side surface 120s of the second isolation structure 120C, and the side surface of the second electrode 220C is aligned with the side surface 110s of the first isolation structure 110C.

Referring to FIG. 5F , an oxide semiconductor structure 300C is formed on the third electrode 230C, and the oxide semiconductor structure 300C extends from the top surface 230t of the third electrode 230C to the top surface 210t of the first electrode 210.

Please refer to FIG. 5G , the oxygen element in the oxide semiconductor structure 300C is diffused into the second electrode 220C to form a native oxide layer 140C on the second electrode 220C. The native oxide layer 140C is formed at the interface between the second electrode 220C and the oxide semiconductor structure 300C. While forming the native oxide layer 140C, a conductive region 304 with a lower oxygen concentration is formed in the oxide semiconductor structure 300C. The conductive region 304 connects the first channel region 302 and the second channel region 306.

In some embodiments, during the process of depositing the oxide semiconductor structure 300C, the native oxide layer 140C and the conductive region 304 are spontaneously formed, but the present invention is not limited thereto. In other embodiments, additional heat treatment processes are performed to promote the diffusion of oxygen in the oxide semiconductor structure 300C into the second electrode 220C.

Referring to FIG. 5H , a gate dielectric layer 150 is formed on the oxide semiconductor structure 300C. In this embodiment, before forming the gate dielectric layer 150, a native oxide layer 140C has been formed between the oxide semiconductor structure 300C and the second electrode 220C, but the present invention is not limited thereto. In other embodiments, after forming the gate dielectric layer 150 or during the process of forming the gate dielectric layer 150, oxygen in the oxide semiconductor structure 300C is diffused into the second electrode 220C to form the native oxide layer 140C and the conductive region 304.

Finally, please return to FIG. 4 to form a gate 240 on the gate dielectric layer 150. At this point, the semiconductor device 10C is substantially completed.

FIG6 is a cross-sectional schematic diagram of a semiconductor device 10D according to an embodiment of the present invention. It must be noted that the embodiment of FIG6 uses the component numbers and partial contents of the embodiments of FIG4 to FIG5H, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, which will not be elaborated here.

Referring to FIG. 6 , in this embodiment, the first isolation structure 110C includes a first through hole H1, and the second isolation structure 120C includes a second through hole H2. The first through hole H1 overlaps the second through hole H2. The semiconductor structure 300C is filled in the first through hole H1 and the second through hole H2. In this embodiment, the native oxide layer 140C has a ring-shaped structure and surrounds the conductive region 304 of the semiconductor structure 300C.

FIG. 7 is a cross-sectional schematic diagram of a semiconductor device 10E according to an embodiment of the present invention. It must be noted that the embodiment of FIG. 7 uses the component numbers and partial contents of the embodiments of FIG. 4 to FIG. 5H, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, which will not be elaborated here.

The main difference between the semiconductor device 10E of FIG. 7 and the semiconductor device 10C of FIG. 4 is that in the semiconductor device 10C, the semiconductor structure 300C has a single-layer structure. However, in the semiconductor device 10E, the semiconductor structure 300D has a multi-layer structure.

The semiconductor structure 300D includes a first semiconductor layer 310D, a second semiconductor layer 320D, and a third semiconductor layer 330D. The first semiconductor layer 310D, the second semiconductor layer 320D, and the third semiconductor layer 330D include the same or different semiconductor materials. In some embodiments, there is a native oxide layer 140C between the first semiconductor layer 310D and the second electrode 220C, and the first semiconductor layer 310D includes a first channel region 312, a conductive region 314, and a second channel region 316. The first channel region 312, the conductive region 314, and the second channel region 316 contact the first isolation structure 110C, the native oxide layer 140C, and the second isolation structure 120C, respectively. The conductive region 314 is sandwiched between the first channel region 312 and the second channel region 316. In some embodiments, the oxygen concentration of the conductive region 314 is lower than the oxygen concentration of the first channel region 312 and the oxygen concentration of the second channel region 316, and the carrier concentration of the conductive region 314 is higher than the carrier concentration of the first channel region 312 and the carrier concentration of the second channel region 316. The resistivity of the conductive region 314 is lower than the resistivity of the first channel region 312 and the resistivity of the second channel region 316.

In some embodiments, during the process of manufacturing the semiconductor device 10E, the oxygen elements in the first semiconductor layer 310D diffuse toward the second electrode 220C to form the native oxide layer 140C and the conductive region 314. In some embodiments, the oxygen elements in the second semiconductor layer 320D and the third semiconductor layer 330D do not diffuse toward the second electrode 220C, but the present invention is not limited thereto. In other embodiments, the oxygen elements in the second semiconductor layer 320D and the third semiconductor layer 330D also diffuse toward the second electrode 220C.

FIG8A is a cross-sectional schematic diagram of a simulation structure of a semiconductor device according to an embodiment of the present invention. FIG8B is a partial enlarged view of the virtual frame position of FIG8A. FIG9A and FIG9B are data diagrams of gate voltage (Vg) and current (Id) of the simulation structure of the semiconductor device of FIG8A and FIG8B, wherein during the simulation, a gate voltage (Vg) is applied to the gate 240, the second electrode 220 is a floating electrode, the voltage difference between the first electrode 210 and the third electrode 230 is 5V, and the current between the first electrode 210 and the third electrode 230 is Id. The simulated structure of the semiconductor device in FIG8A and FIG8B is similar to the structure of the semiconductor device 10A in FIG1 .

In FIG. 9A and FIG. 9B , the semiconductor devices of the first embodiment, the second embodiment and the third embodiment have similar structures (such as the structures shown in FIG. 8A and FIG. 8B ). In the first embodiment, the second embodiment and the third embodiment, the material of the semiconductor structure 300 includes indium gallium zinc oxide, wherein the carrier concentration of the first channel region 302 and the second channel region 306 is 1e16 to 1e18 cm ^-3 , and the carrier concentration of the conductive region 304 is 5e18 to 1e22 cm ^-3 . The difference between the first embodiment, the second embodiment and the third embodiment is that the carrier concentration of the conductive region 304 is different, wherein the carrier concentration of the conductive region 304 of the third embodiment is the largest, while the carrier concentration of the conductive region 304 of the first embodiment is the smallest.

As can be seen from Figures 9A and 9B, increasing the carrier concentration of the conductive region 304 helps to increase the drive current (Ion) of the semiconductor device and can reduce the critical voltage (Vth) of the gate.

FIG10A is a cross-sectional schematic diagram of a simulation structure of a semiconductor device of an embodiment of the present invention. FIG10B is a partial enlarged view of the virtual frame position of FIG10A. FIG11A and FIG11B are data diagrams of gate voltage (Vg) and current (Id) of the simulation structure of the semiconductor device of FIG10A and FIG10B, wherein during the simulation, a gate voltage (Vg) is applied to the gate 240, and the second electrode 220C is a floating electrode, the voltage difference between the first electrode 210 and the third electrode 230 is 5V, and the current between the first electrode 210 and the third electrode 230 is Id.

In FIG. 11A and FIG. 11B , the semiconductor devices of the fourth embodiment, the fifth embodiment and the sixth embodiment have similar structures (such as the structure shown in FIG. 10 ). In the fourth embodiment, the fifth embodiment and the sixth embodiment, the material of the semiconductor structure 300C includes indium gallium zinc oxide, wherein the carrier concentration of the first channel region 302 and the second channel region 306 is 1e16 to 1e18 cm ^-3 , and the carrier concentration of the conductive region 304 is 5e18 to 1e22 cm ^-3 . The difference between the fourth embodiment, the fifth embodiment and the sixth embodiment is that the carrier concentration of the conductive region 304 is different, wherein the carrier concentration of the conductive region 304 of the sixth embodiment is the largest, while the carrier concentration of the conductive region 304 of the fourth embodiment is the smallest.

It can be seen from Figures 11A and 11B that increasing the carrier concentration of the conductive region 304 helps to increase the drive current (Ion) of the semiconductor device and can reduce the critical voltage (Vth) of the gate.

In summary, in the semiconductor device of the present invention, the second electrode can absorb oxygen elements in the oxide semiconductor structure, thereby forming a native oxide layer between the second electrode and the oxide semiconductor structure. Through such a setting, the carrier concentration of the conductive region in the oxide semiconductor structure can be increased, thereby increasing the driving current of the semiconductor device.

10A: Semiconductor devices

100: Substrate

110: First isolation structure

110s,120s: Side

120: Second isolation structure

140: Native oxide layer

150: Gate dielectric layer

210: First electrode

210t,230t:Top

220: Second electrode

230: Third electrode

240: Gate

300: Oxide semiconductor structure

302: First channel area

304: Conductive area

306: Second channel area

t1,t2,t3,t4,t5: thickness

Claims (10)

A semiconductor device comprises: a first electrode; a first isolation structure located on the first electrode; a second electrode located on the first isolation structure, wherein the second electrode comprises at least one of niobium, titanium, beryllium, aluminum, silicon, manganese, chromium, vanadium and calcium; a second isolation structure located on the second electrode; a third electrode located on the second isolation structure, wherein the first electrode, the first isolation structure, the second electrode, the second isolation structure and the third electrode are stacked in sequence; An oxide semiconductor structure extending from the top surface of the third electrode to the top surface of the first electrode and contacting the side surface of the first isolation structure and the side surface of the second isolation structure; A native oxide layer including an oxide of at least one of cobalt, titanium, curium, aluminum, silicon, manganese, chromium, vanadium and calcium and laterally disposed between the second electrode and the oxide semiconductor structure; A gate dielectric layer disposed on the oxide semiconductor structure; and A gate electrode disposed on the gate dielectric layer. A semiconductor device as described in claim 1, wherein the thickness of the second electrode is less than the thickness of the first isolation structure and the thickness of the second isolation structure. A semiconductor device as described in claim 1, wherein the oxide semiconductor structure includes a first channel region, a conductive region and a second channel region, the first channel region, the conductive region and the second channel region respectively contact the first isolation structure, the native oxide layer and the second isolation structure, wherein the conductive region is sandwiched between the first channel region and the second channel region, and the resistivity of the conductive region is lower than the resistivity of the first channel region and the resistivity of the second channel region. A semiconductor device as described in claim 1, wherein the second electrode extends beyond the side surface of the second isolation structure, and the native oxide layer is formed on the top surface of the second electrode and the side surface of the second electrode. A semiconductor device as described in claim 1, wherein the second electrode is a floating electrode. A semiconductor device as described in claim 1, wherein the gate is electrically connected to the second electrode. A semiconductor device as described in claim 1, wherein the second electrode comprises doped silicon. A method for manufacturing a semiconductor device, comprising: forming a first isolation material layer on a first electrode; forming a first electrode material layer on the first isolation material layer, wherein the first electrode material layer includes at least one of niobium, titanium, beryllium, aluminum, silicon, manganese, chromium, vanadium and calcium; forming a second isolation material layer on the first electrode material layer; forming a second electrode material layer on the second isolation material layer; forming a patterned photoresist layer on the second electrode material layer; Perform one or more etching processes to pattern the second electrode material layer, the second isolation material layer, the first electrode material layer and the first isolation material layer to form a third electrode, a second isolation structure, a second electrode and a first isolation structure respectively, wherein the first electrode, the first isolation structure, the second electrode, the second isolation structure and the third electrode are stacked in sequence; Form an oxide semiconductor structure on the third electrode, and the oxide semiconductor structure extends from the top surface of the third electrode to the top surface of the first electrode; Diffusion of oxygen elements in the oxide semiconductor structure into the second electrode to form a native oxide layer on the second electrode; Forming a gate dielectric layer on the oxide semiconductor structure; and Forming a gate electrode on the gate dielectric layer. The method for manufacturing a semiconductor device as described in claim 8, wherein the method for performing the one or more etching processes to pattern the second electrode material layer, the second isolation material layer, the first electrode material layer and the first isolation material layer comprises: Performing a first etching process on the second electrode material layer using the patterned photoresist layer as a mask to form the third electrode; Performing a second etching process on the second isolation material layer using the patterned photoresist layer and the third electrode as masks to form an intermediate isolation layer; Performing a third etching process on the first electrode material layer with the patterned photoresist layer, the third electrode and the intermediate isolation layer as masks to form the second electrode; Removing the patterned photoresist layer; Performing a fourth etching process on the intermediate isolation layer and the first isolation material layer with the third electrode and the second electrode as masks to form the second isolation structure and the first isolation structure respectively. A method for manufacturing a semiconductor device as described in claim 9, wherein after performing the first etching process, a side surface of the third electrode is retracted toward a side surface of the patterned photoresist layer.