TWI869085B - Semiconductor device - Google Patents

Abstract

A semiconductor device includes a first source/drain, a first insulation structure, a second source/drain, a semiconductor structure, a gate dielectric layer and a gate. The first insulation structure is located on the first source/drain. The first source/drain, the first insulation structure and the second source/drain are stacked sequentially in a first direction. The semiconductor structure extends from the second source/drain along a first side surface of the first insulation structure to a top surface of the first source/drain. A first portion of the semiconductor structure contacts the first source/drain and has a first thickness. A second portion of the semiconductor structure contacts the second source/drain and has a second thickness. The second thickness is different from the first thickness.

Description

Semiconductor Devices

The present invention relates to a semiconductor device.

At present, common thin film transistors usually use amorphous silicon semiconductors as channel materials. Amorphous silicon semiconductors are widely used in various thin film transistors because of their simple process and low cost. With the continuous advancement of display technology, the resolution of display panels is also increasing year by year. In order to reduce the size of thin film transistors in pixel circuits, many manufacturers are committed to developing new high carrier mobility semiconductor materials, such as metal oxide semiconductor materials.

The present invention provides a semiconductor device that can improve the negative effects brought by hot carrier effect.

At least one embodiment of the present invention provides a semiconductor device, which includes a first source/drain, a first insulating structure, a second source/drain, a semiconductor structure, a gate dielectric layer, and a gate. The first insulating structure is located on the first source/drain. The second source/drain is located on the top surface of the first insulating structure. The first source/drain, the first insulating structure, and the second source/drain are stacked in sequence in a first direction. The first source/drain and the second source/drain are separated from each other by the first insulating structure. The semiconductor structure extends from the second source/drain along the first side of the first insulating structure to the top of the first source/drain. The first portion of the semiconductor structure contacts the first source/drain and has a first thickness. The second portion of the semiconductor structure contacts the second source/drain and has a second thickness. The second thickness is different from the first thickness. A gate dielectric layer is located on the semiconductor structure. The gate is located on the gate dielectric layer, and the gate overlaps the first side of the first insulating structure in a first direction.

FIG. 1A is a schematic top view of a semiconductor device 1 according to an embodiment of the present invention. FIG. 1B is a schematic cross-sectional view along line A-A' of FIG. 1A. Referring to FIG. 1 , the semiconductor device 1 includes a first source/drain 210, a first insulating structure 310, a second source/drain 220, a semiconductor structure 230, a gate dielectric layer 120, and a gate 240. In this embodiment, the semiconductor device 1 further includes a substrate 100 and a buffer layer 110.

The substrate 100 is, for example, a rigid substrate, and its material may be glass, quartz, organic polymer or opaque/reflective material (e.g., conductive material, metal, wafer, ceramic or other applicable material) or other applicable materials. However, the present invention is not limited thereto, and in other embodiments, the substrate 100 may also be a flexible substrate or a stretchable substrate. For example, the materials of the flexible substrate and the stretchable substrate include polyimide (PI), polydimethylsiloxane (PDMS), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyester (PES), polymethylmethacrylate (PMMA), polycarbonate (PC), polyurethane PU or other suitable materials.

The buffer layer 110 is located on the substrate 100. In some embodiments, the material of the buffer layer includes silicon oxide, silicon nitride, silicon oxynitride, organic insulating material or other suitable materials or a combination of the above materials. In some embodiments, the buffer layer 110 includes a single layer or a multi-layer structure.

The first source/drain 210 is located on the buffer layer 110. In some embodiments, the first source/drain 210 includes metal, metal oxide, metal nitride or a combination thereof. In some embodiments, the first source/drain 210 includes a transparent conductive material or an opaque conductive material. In some embodiments, the first source/drain 210 includes a single layer or a multi-layer structure.

The first insulating structure 310 is located on the first source/drain 210 and has a first through hole 310h overlapping the first source/drain 210, wherein the first through hole 312 exposes a first side surface 312. In some embodiments, the first insulating structure 310 further includes a second side surface 314. The first side surface 312 is, for example, an inner side wall of the first insulating structure 310, and the second side surface 314 is, for example, an outer side wall of the first insulating structure 310.

In some embodiments, the first insulating structure 310 includes an insulating material containing oxygen, such as silicon oxide, silicon oxynitride, or other suitable materials. In some embodiments, the first insulating structure 310 includes a single layer or a multi-layer structure. In some embodiments, the thickness Z1 of the first insulating structure 310 is 100 nm to 1000 nm.

The second source/drain 220 is located on the top surface 316 of the first insulating structure 310. The first source/drain 210, the first insulating structure 310 and the second source/drain 220 are stacked in sequence in the first direction D1. The first insulating structure 310 is located between the first source/drain 210 and the second source/drain 220, and the first source/drain 210 and the second source/drain 220 are separated from each other by the first insulating structure 310.

In some embodiments, the second source/drain 220 includes metal, metal oxide, metal nitride or a combination thereof. In some embodiments, the second source/drain 220 includes a transparent conductive material or an opaque conductive material. In some embodiments, the second source/drain 220 includes a single layer or a multi-layer structure.

In this embodiment, the second source/drain 220 has a first opening 220h, wherein the first opening 220h overlaps the first through hole 310h of the first insulating structure 310. In some embodiments, the shape of the vertical projection of the second source/drain 220 on the substrate 100 is substantially equal to the shape of the vertical projection of the first insulating structure 310 on the substrate 100.

The semiconductor structure 230 extends from the top surface 226 of the second source/drain 220 along the first side surface 312 of the first insulating structure 310 to the top surface 216 of the first source/drain 210. Specifically, the semiconductor structure 230 fills the first opening 220h of the second source/drain 220 and the first through hole 310h of the first insulating structure 310, and contacts the first source/drain 210 at the bottom of the first through hole 310h.

The first portion P1 of the semiconductor structure 230 contacts the first source/drain 210 and has a first thickness t1. The second portion P2 of the semiconductor structure 230 contacts the second source/drain 220 and has a second thickness t2. The second thickness t2 is different from the first thickness t1.

In this embodiment, the semiconductor structure 230 includes a first semiconductor layer 232, a second semiconductor layer 234, and a third semiconductor layer 236. The first semiconductor layer 232 contacts the second source/drain 220 and does not contact the first source/drain 210. The second semiconductor layer 234 and the third semiconductor layer 236 extend from above the second source/drain 220 to the first source/drain 210. The second semiconductor layer 234 contacts the first source/drain 210 and does not contact the second source/drain 220.

The first portion P1 of the semiconductor structure 230 is formed by stacking the second semiconductor layer 234 and the third semiconductor layer 236, and the first thickness t1 includes the thickness of the second semiconductor layer 234 and the thickness of the third semiconductor layer 236. The second semiconductor layer 234 contacts the first side surface 312 of the first insulating structure 310.

The second portion P2 of the semiconductor structure 230 is formed by stacking the first semiconductor layer 232, the second semiconductor layer 234, and the third semiconductor layer 236, and the second thickness t2 includes the thickness of the first semiconductor layer 232, the thickness of the second semiconductor layer 234, and the thickness of the third semiconductor layer 236. In some embodiments, the second portion P2 is annular and surrounds the first opening 220h.

In this embodiment, the semiconductor structure 230 further includes a first channel region CH1 located between the first portion P1 and the second portion P2. The first channel region CH1 connects the first portion P1 and the second portion P2 and is located on the first side surface 312 of the first insulating structure 310. The first channel region CH1 is formed by stacking the second semiconductor layer 234 and the third semiconductor layer 236.

In some embodiments, the materials of the first semiconductor layer 232, the second semiconductor layer 234, and the third semiconductor layer 236 include oxides of three or more of gallium (Ga), zinc (Zn), indium (In), tin (Sn), aluminum (Al), and tungsten (W) (for example, metal oxides such as indium gallium tin zinc oxide (IGTZO), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), aluminum zinc tin oxide (AZTO), and indium tungsten zinc oxide (IWZO)) or nitride-doped metal oxides (for example, Ln-IZO) or other suitable metal oxides or combinations of the above materials. The first semiconductor layer 232, the second semiconductor layer 234, and the third semiconductor layer 236 include the same or different materials. In some embodiments, the first semiconductor layer 232, the second semiconductor layer 234, and the third semiconductor layer 236 include the same metal element but have different oxygen concentrations.

The gate dielectric layer 120 is located on the semiconductor structure 230. In some embodiments, the gate dielectric layer 120 is conformal to the top surface 226 of the second source/drain 220 and the top surface 316 of the first insulating structure 310, and fills the first opening 220h of the second source/drain 220 and the first through hole 310h of the first insulating structure 310. In some embodiments, the gate dielectric layer 120 contacts the second side surface 314 of the first insulating structure 310. In some embodiments, the gate dielectric layer 120 contacts the first source/drain 210 and the buffer layer 110.

In some embodiments, the material of the gate dielectric layer 120 includes silicon oxide, silicon nitride, silicon oxynitride, tantalum oxide or other suitable materials or combinations thereof.

The gate 240 is located on the gate dielectric layer 120. The gate 240 overlaps the first side surface 312 of the first insulating structure 310 in the first direction D1. In this embodiment, a portion of the gate 240 is filled into the first opening 220h of the second source/drain 220 and the first through hole 310h of the first insulating structure 310, so that at least a portion of the gate dielectric layer 120 is located between the first channel region CH1 and the gate 240 in the second direction D2. The second direction D2 is approximately perpendicular to the first direction D1. The first portion P1 of the semiconductor structure 230 is located between the gate 240 and the first source/drain 210 in the first direction D1, and the second portion P2 of the semiconductor structure 230 is located between the gate 240 and the second source/drain 220 in the first direction D1.

In some embodiments, the gate 240 includes metal, metal oxide, metal nitride or a combination thereof. In some embodiments, the gate 240 includes a transparent conductive material or an opaque conductive material. In some embodiments, the gate 240 includes a single-layer or multi-layer structure.

In the present embodiment, the second thickness t2 of the second portion P2 is greater than the first thickness t1 of the first portion P1, thereby making the second portion P2 have a larger equivalent resistivity. In some embodiments, the first semiconductor layer 232, the second semiconductor layer 234, and the third semiconductor layer 236 contain the same metal element, however, the equivalent resistivity of the second portion P2 can be further increased by making the oxygen concentration of the first semiconductor layer 232 and the oxygen concentration of the third semiconductor layer 236 higher than the oxygen concentration of the second semiconductor layer 234. For example, the equivalent resistivity of the first portion P1 can be between 1*E-4 ohm•cm and 6*E-4 ohm•cm, and the equivalent resistivity of the second portion P2 can be between 3*E-4 ohm•cm and 10*E-4 ohm•cm.

In other embodiments, the first insulating structure 310 is used to supplement oxygen to the second semiconductor layer 234, thereby increasing the oxygen concentration of the second semiconductor layer 234 in the first channel region CH1, and even making the oxygen concentration of the second semiconductor layer 234 higher than the oxygen concentration of the first semiconductor layer 232 and the oxygen concentration of the third semiconductor layer 236, thereby avoiding the generation of short-channel effects.

In this embodiment, the first source/drain 210 is used as a source, and the second source/drain 220 is used as a drain. By making the drain contact the second portion P2 with a larger second thickness t2, the hot carrier effect caused by the electric field between the gate 240 and the drain can be improved. In some embodiments, the second source/drain 220 includes a Schottky contact or an Ohmic contact with the second portion P2.

2A to 5A are top views of a method for manufacturing the semiconductor device 1 of FIG. 1A. FIG. 2B to 5B are cross-sectional views along the line A-A' of FIG. 2A to 5A, respectively. Referring to FIG. 2A and FIG. 2B, a buffer layer 110 is formed on a substrate 100. A first source/drain 210 is formed on the buffer layer 110.

3A and 3B, a first insulating structure 310 and a second source/drain 220 are formed. In some embodiments, an insulating material layer is formed on the first source/drain 210. A conductive layer is formed on the insulating material layer. The conductive layer is patterned to form the second source/drain 220. The insulating material layer is etched using the second source/drain 220 as a mask to form the first insulating structure 310. In some embodiments, the etching process used to form the first insulating structure 310 includes a dry etching process, so that the first side surface 312 and the second side surface 314 of the first insulating structure 310 are nearly vertical sides and aligned with the second source/drain 220. In other embodiments, the etching process used to form the first insulating structure 310 includes a wet etching process. In this case, the first side surface 312 and the second side surface 314 of the first insulating structure 310 may have an undercut problem.

Next, referring to FIG. 4A and FIG. 4B , a first semiconductor layer 232 is formed on the second source/drain 220. In some embodiments, a first semiconductor material layer is first deposited on the entire surface. Then, the first semiconductor material layer is patterned to form the first semiconductor layer 232. The composition of the obtained first semiconductor layer 232 can be adjusted by the process parameters when depositing the first semiconductor material layer.

Referring to FIG. 5A and FIG. 5B , a second semiconductor layer 234 and a third semiconductor layer 236 are formed. The second semiconductor layer 234 and the third semiconductor layer 236 extend from above the second source/drain 220 to the first through hole 310h. In some embodiments, the first semiconductor material layer and the second semiconductor material layer are first deposited on the entire surface. Then, the first semiconductor material layer is patterned and the second semiconductor material layer is deposited to form the second semiconductor layer 234 and the third semiconductor layer 236. The composition of the obtained second semiconductor layer 234 and the third semiconductor layer 236 can be adjusted by the process parameters when depositing the first semiconductor material layer and the second semiconductor material layer.

Finally, returning to FIG. 1A and FIG. 1B , a gate dielectric layer 120 is formed on the third semiconductor layer 236 , and a gate 240 is formed on the gate dielectric layer 120 .

FIG6 is a cross-sectional schematic diagram of a semiconductor device 2 according to another embodiment of the present invention. It should be noted that the embodiment of FIG6 uses the component numbers and partial contents of the embodiments of FIG1A to FIG5B, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can refer to the aforementioned embodiments, and will not be repeated here.

The main difference between the semiconductor device 2 of FIG. 6 and the semiconductor device 1 of FIG. 1B is that the first insulating structure 310 and the second source/drain 220 of the semiconductor device 2 have different shapes. In the present embodiment, the first insulating structure 310 and the second source/drain 220 are patterned by, for example, different mask patterns. In the present embodiment, the gate dielectric layer 120 does not contact the first source/drain 210 and the buffer layer 110.

FIG7 is a cross-sectional schematic diagram of a semiconductor device 3 according to another embodiment of the present invention. It should be noted that the embodiment of FIG6 uses the component numbers and partial contents of the embodiments of FIG1A to FIG5B, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can refer to the aforementioned embodiments, and will not be repeated here.

The main difference between the semiconductor device 3 of FIG. 7 and the semiconductor device 1 of FIG. 1B is that in the semiconductor structure 230a of the semiconductor device 3, the thickness t1 of the first portion P1 is greater than the thickness t2 of the second portion P2.

In the present embodiment, the first semiconductor layer 232 contacts the first source/drain 210 and does not contact the second source/drain 220. The second semiconductor layer 234 contacts the second source/drain 220 and does not contact the first source/drain 210. In the present embodiment, the first source/drain 210 is used as a drain, and the second source/drain 220 is used as a source. By making the drain contact the first portion P1 having a larger first thickness t1, the hot carrier effect caused by the electric field between the gate 240 and the drain can be improved. In some embodiments, a Schottky contact or an Ohmic contact is formed between the first source/drain 210 and the first portion P1.

FIG8A is a schematic top view of a semiconductor device 4 according to an embodiment of the present invention. FIG8B is a schematic cross-sectional view along line A-A' of FIG1A. It should be noted that the embodiments of FIG8A and FIG8B use the component numbers and partial contents of the embodiments of FIG1A to FIG5B, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.

The main difference between the semiconductor device 4 of FIG. 8B and the semiconductor device 1 of FIG. 1B is that the semiconductor device 4 further includes a second insulating structure 320 and a third source/drain 250.

8A and 8B , the first source/drain 210 , the first insulating structure 310 , the second source/drain 220 , the second insulating structure 320 , and the third source/drain 250 are sequentially stacked in the first direction D1 .

The second insulating structure 320 is located on the second source/drain 220 and has a second through hole 320h overlapping the first through hole 310h, wherein the second through hole 320h exposes a first side surface 322. In some embodiments, the second insulating structure 320 further includes a second side surface 324. The first side surface 322 is, for example, an inner side wall of the second insulating structure 320, and the second side surface 324 is, for example, an outer side wall of the second insulating structure 320. The width of the second through hole 320h is greater than the width of the first through hole 310h.

In some embodiments, the second insulating structure 320 includes an insulating material containing oxygen, such as silicon oxide, silicon oxynitride, or other suitable materials. In some embodiments, the second insulating structure 320 includes a single layer or a multi-layer structure. In some embodiments, the thickness Z2 of the second insulating structure 320 is 100 nm to 1000 nm.

The third source/drain 250 is located on the top surface 326 of the second insulating structure 320. The second insulating structure 320 is located between the second source/drain 220 and the third source/drain 250, and the second source/drain 220 and the third source/drain 250 are separated from each other by the second insulating structure 320.

In some embodiments, the third source/drain 250 includes metal, metal oxide, metal nitride or a combination thereof. In some embodiments, the third source/drain 250 includes a transparent conductive material or an opaque conductive material. In some embodiments, the third source/drain 250 includes a single layer or a multi-layer structure.

In this embodiment, the third source/drain 250 has a second opening 250h, wherein the second opening 250h overlaps the second through hole 320h of the second insulating structure 320. In some embodiments, the shape of the vertical projection of the third source/drain 250 on the substrate 100 is substantially equal to the shape of the vertical projection of the second insulating structure 320 on the substrate 100.

The semiconductor structure 230 b extends from the top surface 256 of the third source/drain 250 to the second source/drain 220 along the first side surface 322 of the second insulating structure 320 , and then extends from the second source/drain 220 to the first source/drain 210 along the first side surface 312 of the first insulating structure 310 . Specifically, the semiconductor structure 230b fills the second opening 250h of the third source/drain 250, the second through hole 320h of the second insulating structure 320, the first opening 220h of the second source/drain 220, and the first through hole 310h of the first insulating structure 310, and contacts the first source/drain 210 at the bottom of the first through hole 310h. The semiconductor structure 230b contacts the side surface of the second source/drain 220 (i.e., the side wall of the first opening 220h). In some embodiments, the semiconductor structure 230b contacts a portion of the top surface 226 of the second source/drain 220.

The first portion P1 of the semiconductor structure 230b contacts the first source/drain 210 and has a first thickness t1. The second portion P2 of the semiconductor structure 230b contacts the second source/drain 220 and has a second thickness t2. The third portion P3 of the semiconductor structure 230b contacts the third source/drain 250 and has a third thickness t3. The third thickness t3 and the first thickness t1 are different from the second thickness t2.

In this embodiment, the semiconductor structure 230b includes a first semiconductor layer 232, a second semiconductor layer 234, and a third semiconductor layer 236. The first semiconductor layer 232 contacts the first source/drain 210 and the third source/drain 250, and does not contact the second source/drain 220. The second semiconductor layer 234 and the third semiconductor layer 236 extend from above the third source/drain 250 to the first source/drain 210. The second semiconductor layer 234 contacts the second source/drain 220, and does not contact the first source/drain 210 and the third source/drain 250.

The first portion P1 and the third portion P3 of the semiconductor structure 230b are stacked by a first semiconductor layer 232, a second semiconductor layer 234, and a third semiconductor layer 236, and the first thickness t1 and the third thickness t3 include the thickness of the first semiconductor layer 232, the thickness of the second semiconductor layer 234, and the thickness of the third semiconductor layer 236. In this embodiment, the first semiconductor layer 232 includes a first contact portion 232A and a second contact portion 232B separated from each other. The first portion P1 of the semiconductor structure 230b is composed of a stack of the first contact portion 232A, the second semiconductor layer 234 and the third semiconductor layer 236, and the third portion P3 of the semiconductor structure 230b is composed of a stack of the second contact portion 232B, the second semiconductor layer 234 and the third semiconductor layer 236.

The second portion P2 of the semiconductor structure 230b is formed by stacking the second semiconductor layer 234 and the third semiconductor layer 236, and the second thickness t2 includes the thickness of the second semiconductor layer 234 and the thickness of the third semiconductor layer 236. The second semiconductor layer 234 contacts the first side surface 312 of the first insulating structure 310 and the first side surface 322 of the second insulating structure 320. In some embodiments, the second portion P2 and the third portion P3 are ring-shaped.

In this embodiment, the semiconductor structure 23b further includes a first channel region CH1 located between the first portion P1 and the second portion P2 and a second channel region CH2 located between the second portion P2 and the third portion P3. The first channel region CH1 connects the first portion P1 and the second portion P2 and is located on the first side surface 312 of the first insulating structure 310. The first channel region CH1 is formed by stacking the second semiconductor layer 234 and the third semiconductor layer 236. The second channel region CH2 connects the second portion P2 and the third portion P3 and is located on the first side surface 322 of the second insulating structure 320. The second channel region CH2 is formed by stacking the second semiconductor layer 234 and the third semiconductor layer 236.

The gate dielectric layer 120 is located on the semiconductor structure 230 b. In some embodiments, the gate dielectric layer 120 conforms to the top surface 256 of the third source/drain 250 and the top surface 326 of the second insulating structure 320, and fills the second opening 250 h of the third source/drain 250, the second through hole 320 h of the second insulating structure 320, the first opening 220 h of the second source/drain 220, and the first through hole 310 h of the first insulating structure 310. In some embodiments, the gate dielectric layer 120 contacts the second side surface 314 of the first insulating structure 310 and the second side surface 324 of the second insulating structure 320.

The gate 240 is located on the gate dielectric layer 120. The gate 240 overlaps the first side surface 312 of the first insulating structure 310 and the first side surface 322 of the second insulating structure 320 in the first direction D1. In the present embodiment, a portion of the gate 240 is filled in the second opening 250h of the third source/drain 250 and the second through hole 320h of the second insulating structure 320, so that at least a portion of the gate dielectric layer 120 is located between the second channel region CH2 and the gate 240 in the second direction D2. The third portion P3 of the semiconductor structure 230b is located between the gate 240 and the third source/drain 250 in the first direction D1.

In the present embodiment, the first thickness t1 of the first portion P1 and the third thickness t3 of the third portion P3 are greater than the second thickness t2 of the second portion P2, thereby making the first portion P1 and the third portion P3 have a larger equivalent resistivity. In some embodiments, the first semiconductor layer 232, the second semiconductor layer 234, and the third semiconductor layer 236 include the same metal element, however, by making the oxygen concentration of the first semiconductor layer 232 and the oxygen concentration of the third semiconductor layer 236 higher than the oxygen concentration of the second semiconductor layer 234, the equivalent resistivity of the first portion P1 and the third portion P3 can be further improved. In other embodiments, the first insulating structure 310 and the second insulating structure 320 are used to supplement oxygen to the second semiconductor layer 234, thereby increasing the oxygen concentration of the second semiconductor layer 234 in the first channel region CH1 and the second channel region CH2, and even making the oxygen concentration of the second semiconductor layer 234 higher than the oxygen concentration of the first semiconductor layer 232 and the oxygen concentration of the third semiconductor layer 236, thereby avoiding the generation of short-channel effects.

In this embodiment, the second source/drain 220 is used as a source, and the first source/drain 210 and the third source/drain 210 are used as drains. By making the drain contact the first portion P1 with a larger first thickness t1 and the third portion P3 with a larger third thickness t3, respectively, the hot carrier effect caused by the electric field between the gate 240 and the drain can be improved. In some embodiments, the first source/drain 210 includes a Schottky contact or an Ohmic contact with the first portion P1. In some embodiments, the third source/drain 250 includes a Schottky contact or an Ohmic contact with the third portion P3.

9A to 12A are top views of a method for manufacturing the semiconductor device 4 of FIG. 9A. FIG. 9B to 12B are cross-sectional views along line A-A' of FIG. 9A to 12A, respectively. Referring to FIG. 9A and FIG. 9B, a first insulating structure 310 and a second source/drain 220 are formed.

Next, referring to FIG. 10A and FIG. 10B , a second insulating structure 320 and a third source/drain 250 are formed. In some embodiments, an insulating material layer is formed on the second source/drain 220 and covers the first insulating structure 310. A conductive layer is formed on the insulating material layer. The conductive layer is patterned to form the third source/drain 250. The insulating material layer is etched using the third source/drain 250 as a mask to form the second insulating structure 320. In some embodiments, the etching process used to form the second insulating structure 320 includes a dry etching process, so that the first side surface 322 and the second side surface 324 of the second insulating structure 320 are nearly vertical sides and aligned with the third source/drain 250. In other embodiments, the etching process used to form the second insulating structure 320 includes a wet etching process. In this case, the first side surface 322 and the second side surface 324 of the second insulating structure 320 may have a problem of undercutting.

Next, referring to FIG. 11A and FIG. 11B , a first semiconductor layer 232 is formed on the first source/drain 210 and the third source/drain 250 .

12A and 12B , a second semiconductor layer 234 and a third semiconductor layer 236 are formed. The second semiconductor layer 234 and the third semiconductor layer 236 extend from above the third source/drain 250 into the first through hole 310h and the second through hole 320h.

Finally, returning to FIG. 8A and FIG. 8B , a gate dielectric layer 120 is formed on the third semiconductor layer 236 , and a gate 240 is formed on the gate dielectric layer 120 .

FIG13 is a cross-sectional schematic diagram of a semiconductor device 5 according to another embodiment of the present invention. It should be noted that the embodiment of FIG13 uses the component numbers and partial contents of the embodiments of FIG8A to FIG12B, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can refer to the aforementioned embodiments, and will not be repeated here.

The main difference between the semiconductor device 5 of FIG. 13 and the semiconductor device 4 of FIG. 8B is that the first insulating structure 310 and the second source/drain 220 of the semiconductor device 5 have different shapes, and the second insulating structure 320 and the third source/drain 250 have different shapes. In the present embodiment, the first insulating structure 310 and the second source/drain 220 are patterned by, for example, different mask patterns, and the second insulating structure 320 and the third source/drain 250 are patterned by, for example, different mask patterns. In the present embodiment, the gate dielectric layer 120 does not contact the first source/drain 210 and the buffer layer 110.

FIG14 is a cross-sectional schematic diagram of a semiconductor device 6 according to another embodiment of the present invention. It should be noted that the embodiment of FIG14 uses the component numbers and partial contents of the embodiments of FIG8A to FIG12B, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can refer to the aforementioned embodiments, and will not be repeated here.

The main difference between the semiconductor device 6 of FIG. 14 and the semiconductor device 4 of FIG. 8B is that in the semiconductor structure 230c of the semiconductor device 6, the thickness t2 of the second portion P2 is greater than the thickness t1 of the first portion P1 and the thickness t3 of the third portion P3.

In the present embodiment, the first semiconductor layer 232 contacts the second source/drain 220 and does not contact the first source/drain 210 and the third source/drain 250. The second semiconductor layer 234 contacts the first source/drain 210 and the third source/drain 250 and does not contact the second source/drain 220. In the present embodiment, the second source/drain 220 is used as a drain, and the first source/drain 210 and the third source/drain 250 are used as sources. By making the drain contact the second portion P2 having a larger second thickness t2, the hot carrier effect caused by the electric field between the gate 240 and the drain can be improved.

FIG15 is a cross-sectional schematic diagram of a semiconductor device 7 according to another embodiment of the present invention. It should be noted that the embodiment of FIG15 uses the component numbers and partial contents of the embodiments of FIG8A to FIG12B, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can refer to the aforementioned embodiments, and will not be repeated here.

The main difference between the semiconductor device 7 of FIG. 15 and the semiconductor device 4 of FIG. 8B is that in the semiconductor structure 230d of the semiconductor device 7, the thickness t2 of the second portion P2 and the thickness t3 of the third portion P3 are greater than the thickness t1 of the first portion P1.

In the present embodiment, the first semiconductor layer 232 contacts the second source/drain 220 and the third source/drain 250 and does not contact the first source/drain 210. The second semiconductor layer 234 contacts the first source/drain 210 and does not contact the second source/drain 220 and the third source/drain 250. In the present embodiment, the first source/drain 210 and the second source/drain 220 can be regarded as the source and drain of the first thin film transistor, and the second source/drain 220 and the third source/drain 250 can be regarded as the source and drain of the second thin film transistor. In other words, the second source/drain 220 can be used as the drain of the first thin film transistor and the source of the second thin film transistor at the same time. In this embodiment, the hot carrier effect of the semiconductor device 7 can be improved through the design of the semiconductor structure 230d.

In some embodiments, the semiconductor device of any of the aforementioned embodiments may be disposed in a display device, and may be arbitrarily combined in a display area and a peripheral area of the display device.

1, 2, 3, 4, 5, 6, 7: semiconductor device 100: substrate 110: buffer layer 120: gate dielectric layer 210: first source/drain 216, 226, 316, 326: top surface 220: second source/drain 220h: first opening 230, 230a, 230b, 230c, 230d: semiconductor structure 232: first semiconductor layer 232A: first contact 232B: second contact 234: second semiconductor layer 236: third semiconductor layer 240: gate 250: third source/drain 250h: second opening 310: first insulating structure 310h: first through hole 312, 322: first side 314, 324: second side 320: second insulating structure 320h: second through hole CH1: first channel region CH2: second channel region D1: first direction D2: second direction P1: first part P2: second part P3: third part t1: first thickness t2: second thickness t3: third thickness Z1, Z2: thickness

FIG. 1A is a schematic top view of a semiconductor device according to an embodiment of the present invention. FIG. 1B is a schematic cross-sectional view along line A-A’ of FIG. 1A. FIG. 2A to FIG. 5A are schematic top views of a method for manufacturing the semiconductor device of FIG. 1A. FIG. 2B to FIG. 5B are schematic cross-sectional views along line A-A’ of FIG. 2A to FIG. 5A, respectively. FIG. 6 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention. FIG. 7 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention. FIG. 8A is a schematic top view of a semiconductor device according to an embodiment of the present invention. FIG. 8B is a schematic cross-sectional view along line A-A’ of FIG. 1A. FIG. 9A to FIG. 12A are schematic top views of a method for manufacturing the semiconductor device of FIG. 9A. FIG. 9B to FIG. 12B are schematic cross-sectional views along the line A-A' of FIG. 9A to FIG. 12A, respectively. FIG. 13 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention. FIG. 14 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention. FIG. 15 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention.

1:Semiconductor devices

100: Substrate

110: Buffer layer

120: Gate dielectric layer

210: First source/drain

216,226,316: Top

220: Second source/drain

220h: First opening

230:Semiconductor structure

232: First semiconductor layer

234: Second semiconductor layer

236: Third semiconductor layer

240: Gate

310: First insulation structure

310h: First through hole

312: First side

314: Second side

CH1: First channel area

D1: First direction

D2: Second direction

P1: Part 1

P2: Part 2

t1: first thickness

t2: Second thickness

Z1:Thickness

Claims (9)

A semiconductor device includes: a first source/drain; a first insulating structure located on the first source/drain; and a second source/drain located on the top surface of the first insulating structure, wherein the first source/drain, the first insulating structure and the second source/drain are stacked in sequence in a first direction, and the first source/drain and the second source/drain are connected to each other. The second source/drain are separated from each other by the first insulating structure; a semiconductor structure extends from the second source/drain along the first side of the first insulating structure to the top of the first source/drain, wherein a first portion of the semiconductor structure contacts the first source/drain and has a first thickness, and a second portion of the semiconductor structure contacts the second source/drain and has a second thickness, the second thickness is different from the first thickness, wherein the semiconductor structure is made of semiconductor material, wherein the semiconductor structure includes: a first semiconductor layer, a second semiconductor layer and a third semiconductor layer, wherein the first semiconductor layer contacts the first source/drain and the second source/drain. and not contacting the other of the first source/drain and the second source/drain, wherein the second semiconductor layer contacts the first side of the first insulating structure; a gate dielectric layer located on the semiconductor structure; and a gate located on the gate dielectric layer, the gate overlapping the first side of the first insulating structure in the first direction. A semiconductor device as described in claim 1, wherein the first semiconductor layer contacts the second source/drain and does not contact the first source/drain, the first portion of the semiconductor structure is formed by stacking the second semiconductor layer and the third semiconductor layer, and the second portion of the semiconductor structure is formed by stacking the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer, wherein the first portion of the semiconductor structure is located between the gate and the first source/drain in the first direction, and the second portion of the semiconductor structure is located between the gate and the second source/drain in the first direction. A semiconductor device as described in claim 1, wherein the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer include the same metal element, and the oxygen concentration of the second semiconductor layer is different from the oxygen concentration of the first semiconductor layer and the oxygen concentration of the third semiconductor layer. The semiconductor device as described in claim 1 further includes: a second insulating structure; a third source/drain, wherein the first source/drain, the first insulating structure, the second source/drain, the second insulating structure and the third source/drain are stacked in sequence in the first direction, wherein a third portion of the semiconductor structure contacts the third source/drain and has a third thickness, and the third thickness and the first thickness are different from the second thickness. A semiconductor device as described in claim 4, wherein the first portion of the semiconductor structure and the third portion of the semiconductor structure are formed by stacking the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer, and the second portion of the semiconductor structure is formed by stacking the second semiconductor layer and the third semiconductor layer. A semiconductor device as described in claim 5, wherein the first semiconductor layer includes a first contact portion and a second contact portion separated from each other, wherein the first portion of the semiconductor structure is composed of a stack of the first contact portion, the second semiconductor layer, and the third semiconductor layer, and the third portion of the semiconductor structure is composed of a stack of the second contact portion, the second semiconductor layer, and the third semiconductor layer. The semiconductor device as described in claim 1 further includes: a second insulating structure; a third source/drain, wherein the first source/drain, the first insulating structure, the second source/drain, the second insulating structure and the third source/drain are stacked in sequence in the first direction, wherein a third portion of the semiconductor structure contacts the third source/drain and has a third thickness, and the third thickness and the second thickness are greater than the first thickness. A semiconductor device as described in claim 7, wherein the first semiconductor layer extends continuously from the third source/drain to the second source/drain, and the first semiconductor layer does not contact the first source/drain. A semiconductor device as described in claim 1, wherein the first insulating structure includes a through hole, the through hole exposes the first side surface, and wherein the first insulating structure further includes a second side surface, and the gate dielectric layer contacts the second side surface.

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