TWI841954B - Active device substrate and manufacturing method thereof - Google Patents

Abstract

An active device substrate includes a substrate, a first semiconductor device and a second semiconductor device. The first semiconductor device and the second semiconductor device are disposed above the substrate. The first semiconductor device includes a first gate, a first semiconductor layer, a first source and a first drain. A first gate dielectric structure is sandwiched between the first gate and the first semiconductor layer. The first gate dielectric structure includes a stack of a portion of a gate dielectric layer and a portion of a ferroelectric material layer. The second semiconductor device is electrically connected to the first semiconductor device and includes a second gate, a second semiconductor layer, a second source and a second drain. Another part of the ferroelectric material layer is sandwiched between the second gate and the second semiconductor layer.

Description

Active element substrate and manufacturing method thereof

The present invention relates to an active component substrate and a manufacturing method thereof.

Since thin film transistors containing metal oxide semiconductors are easily affected by oxygen, hydrogen and water in the environment, their performance is prone to degradation after long-term use, affecting the electrical properties of the thin film transistors. For example, in a display device containing a thin film transistor array, if the metal oxide semiconductors of some thin film transistors have performance degradation, it is easy to cause unevenness (Mura) in the picture displayed by the display device. Generally speaking, in order to reduce this uneven problem, the pixel circuit is connected to an external chip, and a large amount of current information is stored through an external compensation memory. The above-mentioned current information is calculated by an algorithm to obtain a compensation current or voltage, and then the compensation current or voltage is fed back to the pixel circuit. However, the circuit design of the external chip is complex and costly.

The present invention provides an active component substrate that can save the production cost of external memory.

The present invention provides a method for manufacturing an active component substrate, which can save the production cost of external memory.

At least one embodiment of the present invention provides an active element substrate. The active element substrate includes a substrate, a first semiconductor element and a second semiconductor element. The first semiconductor element and the second semiconductor element are arranged on the substrate. The first semiconductor element includes a first gate, a first semiconductor layer, a first source and a first drain. A gate dielectric structure is sandwiched between the first gate and the first semiconductor layer. The gate dielectric structure includes a stack of a portion of the gate dielectric layer and a portion of the ferroelectric material layer. The first source and the first drain are electrically connected to the first semiconductor layer. The second semiconductor element is electrically connected to the first semiconductor element and includes a second gate, a second semiconductor layer, a second source and a second drain. Another portion of the ferroelectric material layer is sandwiched between the second gate and the second semiconductor layer. The second source and the second drain are electrically connected to the second semiconductor layer.

At least one embodiment of the present invention provides a method for manufacturing an active element substrate, comprising: forming a first semiconductor layer and a second semiconductor layer on a substrate; forming a gate dielectric layer on the first semiconductor layer; forming a ferroelectric material layer on the gate dielectric layer and the second semiconductor layer; forming a first gate and a second gate on the ferroelectric material layer, wherein the gate dielectric layer is located between the first gate and the first semiconductor layer, and the ferroelectric material layer is located between the first gate and the first semiconductor layer and between the second gate and the second semiconductor layer; forming a first source and a first drain electrically connected to the first semiconductor layer; forming a second source and a second drain electrically connected to the second semiconductor layer.

10,20: Active component substrate

100: Substrate

102: Buffer layer

112,112’: first semiconductor layer

112a: First source region

112b: First channel area

112c: First drain region

114,114’: Second semiconductor layer

114a: Second source region

114b: Second channel area

114c: Second drain region

116,116’: The third semiconductor layer

116a: The third source region

116b: Third channel area

116c: The third drain area

120: Gate dielectric layer

122: First gate dielectric pattern

124: Second gate dielectric pattern

140: Ferroelectric material layer

142: The first ferroelectric material pattern

144: Second ferroelectric material pattern

150: Interlayer dielectric layer

a:First node

b: Second node

c: The third node

Cst: Storage capacitor

D1: First drain

D2: Second drain

D3: Third drain

EL: light emitting element

G1: First gate

G2: Second gate

G3: The third gate

GI: Gate dielectric structure

ND: Normal direction

O1,O2,O3,O4,O5,O6,OP: Open

PX: Pixel circuit

S1: First source

S2: Second source

S3: The third source

T1: First semiconductor element

T2: Second semiconductor element

T3: The third semiconductor element

_VS1 , V _data , V _DD , _VS2 , V _sus , V _SS : voltage

Figure 1 is a schematic cross-sectional view of an active element substrate according to an embodiment of the present invention.

Figures 2A to 2F are cross-sectional schematic diagrams of the manufacturing method of the active element substrate of Figure 1.

Figure 3 is a schematic cross-sectional view of an active element substrate according to an embodiment of the present invention.

Figures 4A to 4D are cross-sectional schematic diagrams of the manufacturing method of the active element substrate of Figure 3.

Figure 5 is a schematic diagram of an equivalent circuit of a pixel circuit according to an embodiment of the present invention.

FIG6 is a flowchart of a pixel compensation operation of a display device according to an embodiment of the present invention under the pixel circuit setting of FIG5.

Figure 1 is a schematic cross-sectional view of an active element substrate according to an embodiment of the present invention.

Referring to FIG. 1 , the active element substrate 10 includes a substrate 100, a first semiconductor element T1, and a second semiconductor element T2. In this embodiment, the active element substrate 10 further includes a third semiconductor element T3 and a buffer layer 102. In some embodiments, the second semiconductor element T2 is electrically connected to the first semiconductor element T1 through a conductive member not shown in the figure. In some embodiments, the second semiconductor element T2 is electrically connected to the third semiconductor element T3 through a conductive member not shown in the figure. In some embodiments, the third semiconductor element T3 is electrically connected to the first semiconductor element T1 through a conductive member not shown in the figure.

The material of the substrate 100 may be glass, quartz, organic polymer, or opaque/reflective material (e.g., conductive material, metal, wafer, ceramic, or other applicable material) or other applicable materials. If a conductive material or metal is used, an insulating layer (not shown) is covered on the substrate 100 to avoid short circuit problems. In some embodiments, the substrate 100 is a flexible substrate, and the material of the substrate 100 is, for example, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyester (PES), polymethylmethacrylate (PMMA), polycarbonate (PC), polyimide (PI), metal foil, or other flexible materials. The buffer layer 102 is located on the substrate 100. The material of the buffer layer 102 may include silicon nitride, silicon oxide, silicon oxynitride or other suitable materials or stacked layers of the above materials, but the present invention is not limited thereto.

The first semiconductor element T1, the second semiconductor element T2 and the third semiconductor element T3 are disposed on the substrate 100 and the buffer layer 102. The first semiconductor element T1 includes a first gate G1, a first semiconductor layer 112, a first source S1 and a first drain D1. The second semiconductor element T2 includes a second gate G2, a second semiconductor layer 114, a second source S2 and a second drain D2. The third semiconductor element T3 includes a third gate G3, a third semiconductor layer 116, a third source S3 and a third drain D3.

The first semiconductor layer 112, the second semiconductor layer 114 and the third semiconductor layer 116 are disposed on the substrate 100 and the buffer layer 102. The first semiconductor layer 112 includes a first source region 112a, a first drain region 112c and a first channel region 112b located between the first source region 112a and the first drain region 112c. The second semiconductor layer 114 includes a second source region 114a, a second drain region 114c and a second channel region 114b located between the second source region 114a and the second drain region 114c. The third semiconductor layer 116 includes a third source region 116a, a third drain region 116c, and a third channel region 116b located between the third source region 116a and the third drain region 116c.

The first gate G1 overlaps the first channel region 112b of the first semiconductor layer 112 in the normal direction ND of the top surface of the substrate 100, and a gate dielectric structure GI is sandwiched between the first gate G1 and the first semiconductor layer 112. The gate dielectric structure includes a stack of a portion of the gate dielectric layer 120 and a portion of the ferroelectric material layer 140. The gate dielectric layer 120 covers the upper surface and sidewalls of the first semiconductor layer 112, and the ferroelectric material layer 140 is located on the upper surface of the gate dielectric layer 120.

The second gate G2 overlaps the second channel region 114b of the second semiconductor layer 114 in the normal direction ND of the top surface of the substrate 100, and another portion of the ferroelectric material layer 140 is sandwiched between the second gate G2 and the second semiconductor layer 114. The gate dielectric layer 120 covers the sidewalls of the second semiconductor layer 116, and the ferroelectric material layer 140 contacts the upper surface of the second semiconductor layer 114. In some embodiments, the ferroelectric material layer 140 extends continuously from between the first gate G1 and the gate dielectric layer 120 to between the second gate G2 and the second semiconductor layer 114.

The third gate G3 overlaps the third channel region 116b of the third semiconductor layer 116 in the normal direction ND of the top surface of the substrate 100, and another part of the gate dielectric layer 120 is sandwiched between the third gate G3 and the third semiconductor layer 116. The gate dielectric layer 120 covers the upper surface and sidewalls of the third semiconductor layer 116.

In some embodiments, the distance between the first gate G1 and the first semiconductor layer 112 is greater than the distance between the second gate G2 and the second semiconductor layer 114 and the distance between the third gate G3 and the third semiconductor layer 116.

In one embodiment, the materials of the first semiconductor layer 112, the second semiconductor layer 114, and the third semiconductor layer 116 include single crystal silicon, polycrystalline silicon, microcrystalline silicon, organic semiconductor materials, metal oxide semiconductor materials (for example, quaternary metal compounds such as indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), aluminum zinc tin oxide (AZTO), indium tungsten zinc oxide (IWZO), or oxides composed of ternary metals including any three of gallium (Ga), zinc (Zn), indium (In), tin (Sn), aluminum (Al), and tungsten (W)) or other suitable materials. In some embodiments, the first semiconductor layer 112, the second semiconductor layer 114, and the third semiconductor layer 116 include materials with the same or different compositions. In some embodiments, the first semiconductor layer 112, the second semiconductor layer 114, and the third semiconductor layer 116 include the same or different thicknesses.

In one embodiment, the materials of the first gate G1, the second gate G2 and the third gate G3 may include metals, such as chromium (Cr), gold (Au), silver (Ag), copper (Cu), tin (Sn), lead (Pb), tungsten (W), molybdenum (Mo), neodymium (Nd), titanium (Ti), tantalum (Ta), aluminum (Al), zinc (Zn) or alloys of any combination of the above metals or stacked layers of the above metals and/or alloys, but the present invention is not limited thereto. The first gate G1, the second gate G2 and the third gate G3 may also use other conductive materials, such as metal nitrides, metal oxides, metal oxynitrides, stacked layers of metals and other conductive materials, or other materials with conductive properties. In some embodiments, the first gate G1, the second gate G2, and the third gate G3 include materials of the same or different compositions. In some embodiments, the first gate G1, the second gate G2, and the third gate G3 include the same or different thicknesses.

In some embodiments, the material of the gate dielectric layer 120 is, for example, silicon oxide, silicon nitride, silicon oxynitride, or other suitable materials. In some embodiments, the thickness of the gate dielectric layer 120 is 50 nanometers to 100 nanometers.

In some embodiments, the material of the ferroelectric material layer 140 includes Ni _x Mg _y Zn _0.98-y O or Hf _z Zr _1-z O ₂ , wherein x is 0.01 to 0.05, y is 0.05 to 0.15, and z is 0.4 to 0.6. In some embodiments, the thickness of the ferroelectric material layer 140 is 5 nm to 50 nm.

The interlayer dielectric layer 150 is disposed on the first gate G1, the second gate G2, the third gate G3, the ferroelectric material layer 140 and the gate dielectric layer 120, and covers the first gate G1, the second gate G2, the third gate G3, the ferroelectric material layer 140 and the gate dielectric layer 120. The material of the interlayer dielectric layer 150 is, for example, silicon oxide, silicon nitride, silicon oxynitride or other suitable materials.

The openings O1 and O2 in the interlayer dielectric layer 150, the ferroelectric material layer 140, and the gate dielectric layer 120 overlap the first source region 112a and the first drain region 112c, respectively. The first source S1 and the first drain D1 are located on the interlayer dielectric layer 150, and are filled in the openings O1 and O2, respectively, to be electrically connected to the first source region 112a and the first drain region 112c of the first semiconductor layer 112.

The openings O3 and O4 in the interlayer dielectric layer 150, the ferroelectric material layer 140, and the gate dielectric layer 120 overlap the second source region 114a and the second drain region 114c, respectively. The second source S2 and the second drain D2 are located on the interlayer dielectric layer 150, and are filled in the openings O3 and O4, respectively, to be electrically connected to the second source region 114a and the second drain region 114c of the second semiconductor layer 114.

It should be noted that, although in FIG. 1 , the ferroelectric material layer 140 is divided into multiple blocks by the first source S1, the first drain D1, the second source S2, and the second drain D2, the ferroelectric material layer 140 is actually a continuous structure. In other words, the ferroelectric material layer 140 surrounds the first source S1, the first drain D1, the second source S2, and the second drain D2, and the first source S1, the first drain D1, the second source S2, and the second drain D2 pass through the ferroelectric material layer 140.

The openings O5 and O6 in the interlayer dielectric layer 150 and the gate dielectric layer 120 overlap the third source region 116a and the third drain region 116c, respectively. The third source S3 and the third drain D3 are located on the interlayer dielectric layer 150, and are filled in the openings O5 and O6, respectively, to be electrically connected to the third source region 116a and the third drain region 116c of the third semiconductor layer 116.

In one embodiment, the materials of the first source S1, the first drain D1, the second source S2, the second drain D2, the third source S3 and the third drain D3 may include metals, such as chromium, gold, silver, copper, tin, lead, uranium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc or alloys of any combination of the above metals or stacked layers of the above metals and/or alloys, but the present invention is not limited thereto. The first source S1, the first drain D1, the second source S2, the second drain D2, the third source S3 and the third drain D3 may also use other conductive materials, such as metal nitrides, metal oxides, metal oxynitrides, stacked layers of metals and other conductive materials, or other materials with conductive properties. In some embodiments, the first source S1, the first drain D1, the second source S2, the second drain D2, the third source S3, and the third drain D3 include materials of the same or different compositions. In some embodiments, the first source S1, the first drain D1, the second source S2, the second drain D2, the third source S3, and the third drain D3 include the same or different thicknesses.

Based on the above, the gate dielectric structure GI between the first gate G1 of the first semiconductor element T1 and the first semiconductor layer 112 includes the gate dielectric layer 120 and the ferroelectric material layer 140. Therefore, the sub-threshold swing of the first semiconductor element T1 can be made less than 60mV/dec by the negative capacitor effect, and the hysteresis effect of the ferroelectric material layer 140 between the first gate G1 and the first semiconductor layer 112 can be reduced. In addition, since the ferroelectric material layer 140 is sandwiched between the second gate G2 of the second semiconductor element T2 and the second semiconductor layer 116, the second semiconductor element T2 can not only serve as a driving element, but also has the function of storing current information or voltage information. Finally, the gate dielectric layer 120 is sandwiched between the third gate G3 of the third semiconductor element T3 and the third semiconductor layer 116, which can provide a stable forward or reverse current.

Figures 2A to 2F are cross-sectional schematic diagrams of the manufacturing method of the active element substrate 10 of Figure 1.

2A , a first semiconductor layer 112 ′, a second semiconductor layer 114 ′, and a third semiconductor layer 116 ′ are formed on a substrate 100. In this embodiment, the first semiconductor layer 112 ′, the second semiconductor layer 114 ′, and the third semiconductor layer 116 ′ are formed on a buffer layer 102. In some embodiments, the method for forming the first semiconductor layer 112', the second semiconductor layer 114' and the third semiconductor layer 116' includes the following steps: first, a blanket semiconductor material layer (not shown) is formed on the substrate 110 and the buffer layer 102; then, a patterned photoresist (not shown) is formed on the semiconductor material layer by a lithography process; then, the patterned photoresist is used as a mask to perform a wet or dry etching process on the semiconductor material layer to form the first semiconductor layer 112', the second semiconductor layer 114' and the third semiconductor layer 116'; thereafter, the patterned photoresist is removed. In other words, the first semiconductor layer 112', the second semiconductor layer 114' and the third semiconductor layer 116' are formed at the same time, for example.

Referring to FIG. 2B , a gate dielectric layer 120 is formed on the first semiconductor layer 112’ and the third semiconductor layer 116’. In some embodiments, the method for forming the gate dielectric layer 120 includes the following steps: first, a blanket dielectric material layer (not shown) is formed on the first semiconductor layer 112', the second semiconductor layer 114', the third semiconductor layer 116' and the buffer layer 102; then, a patterned photoresist (not shown) is formed on the dielectric material layer by a lithography process; then, the patterned photoresist is used as a mask to perform a wet or dry etching process on the dielectric material layer to form a gate dielectric layer 120 including an opening OP, wherein the opening OP exposes the second semiconductor layer 114'; thereafter, the patterned photoresist is removed. In some embodiments, the length of the opening OP is less than the length of the second semiconductor layer 114', and the gate dielectric layer 120 covers the sidewalls and a portion of the surface of the second semiconductor layer 114'. In some embodiments, the length of the opening OP is greater than the length of the second semiconductor layer 114', and the gate dielectric layer 120 does not contact the second semiconductor layer 114'. In some embodiments, the material of the gate dielectric layer 120 may be a hydrogen-free oxide, thereby preventing hydrogen atoms in the gate dielectric layer 120 from diffusing into the first semiconductor layer 112', the second semiconductor layer 114', and the third semiconductor layer 116' during the manufacturing process.

2C , a ferroelectric material layer 140 is formed on the gate dielectric layer 120 and the second semiconductor layer 114′. The ferroelectric material layer 140 is filled into the opening OP of the gate dielectric layer 120 to contact the second semiconductor layer 114′. In some embodiments, the method of forming the ferroelectric material layer 140 includes the following steps: first, a blanket ferroelectric material layer (not shown) is formed on the gate dielectric layer 120 and the second semiconductor layer 114'; then, a patterned photoresist (not shown) is formed on the ferroelectric material layer by a lithography process; then, the ferroelectric material layer is subjected to a wet or dry etching process using the patterned photoresist as a mask to form the ferroelectric material layer 140 that does not overlap the third semiconductor layer 116'; then, the patterned photoresist is removed.

2D , a first gate G1 and a second gate G2 are formed on the ferroelectric material layer 140, and a third gate G3 is formed on the gate dielectric layer 120. The gate dielectric layer 120 is located between the first gate G1 and the first semiconductor layer 112 and between the third gate G3 and the third semiconductor layer 116, and the ferroelectric material layer 140 is located between the first gate G1 and the first semiconductor layer 112 and between the second gate G2 and the second semiconductor layer 114. In some embodiments, the method for forming the first gate G1, the second gate G2, and the third gate G3 includes the following steps: first, a blanket conductive material layer (not shown) is formed on the gate dielectric layer 120 and the ferroelectric material layer 140; then, a patterned photoresist (not shown) is formed on the conductive material layer by a lithography process; then, the conductive material layer is subjected to a wet or dry etching process using the patterned photoresist as a mask to form the first gate G1, the second gate G2, and the third gate G3; then, the patterned photoresist is removed. In other words, the first gate G1, the second gate G2, and the third gate G3 are formed at the same time, for example.

Next, the first gate G1, the second gate G2 and the third gate G3 are used as masks to perform a doping process P on the first semiconductor layer 112', the second semiconductor layer 114' and the third semiconductor layer 116' to form a first semiconductor layer 112 including a first source region 112a, a first channel region 112b and a first drain region 112c, a second semiconductor layer 114 including a second source region 114a, a second channel region 114b and a second drain region 114c, and a third semiconductor layer 116 including a third source region 116a, a third channel region 116b and a third drain region 116c. In some embodiments, the doping process P includes a hydrogen plasma process or an ion implantation process.

2E , an interlayer dielectric layer 150 is formed on the gate dielectric layer 120 and the ferroelectric material layer 140. In some embodiments, the interlayer dielectric layer 150 is an insulating layer that does not contain hydrogen, thereby preventing hydrogen atoms in the interlayer dielectric layer 150 from diffusing into the first semiconductor layer 112, the second semiconductor layer 114, and the third semiconductor layer 116, but the present invention is not limited thereto. In some embodiments, the interlayer dielectric layer 150 contains hydrogen atoms, so the hydrogen atoms can be diffused into the first semiconductor layer 112, the second semiconductor layer 114, and the third semiconductor layer 116 by heat treatment to adjust the resistivity of the first semiconductor layer 112, the second semiconductor layer 114, and the third semiconductor layer 116. In some embodiments, when the first semiconductor layer 112, the second semiconductor layer 114, and the third semiconductor layer 116 are doped using the hydrogen atoms in the interlayer dielectric layer 150, the doping process P of FIG. 2D can be omitted.

Referring to FIG. 2F , the method for forming openings O1, O2, O3, O4, O5, and O6 includes the following steps: first, using a lithography process to form a patterned photoresist (not shown) on the interlayer dielectric layer 150; then, using the patterned photoresist as a mask to perform a wet or dry etching process to form openings O1, O2, O3, O4, O5, and O6 in the interlayer dielectric layer 150, the ferroelectric material layer 140, and the gate dielectric layer 120; then, removing the patterned photoresist.

Openings O1 and O2 penetrate the interlayer dielectric layer 150, the ferroelectric material layer 140, and the gate dielectric layer 120 to expose the first source region 112a and the first drain region 112c of the first semiconductor layer 112, respectively. Openings O3 and O4 penetrate the interlayer dielectric layer 150, the ferroelectric material layer 140, and the gate dielectric layer 120 to expose the second source region 114a and the second drain region 114c of the second semiconductor layer 114, respectively. Openings O5 and O6 penetrate the interlayer dielectric layer 150 and the gate dielectric layer 120 to expose the third source region 116a and the third drain region 116c of the third semiconductor layer 116, respectively.

Finally, please return to FIG. 1 to form a first source S1, a first drain D1, a second source S2, a second drain D2, a third source S3, and a third drain D3 on the interlayer dielectric layer 150. The first source S1 and the first drain D1 are filled into the openings O1 and O2, respectively. The second source S2 and the second drain D2 are filled into the openings O3 and O4, respectively. The third source S3 and the third drain D3 are filled into the openings O5 and O6, respectively. In some embodiments, the method of forming the first source S1, the first drain D1, the second source S2, the second drain D2, the third source S3 and the third drain D3 includes the following steps: first, forming a blanket conductive material layer (not shown) on the interlayer dielectric layer 150; then, forming a patterned photoresist (not shown) on the conductive material layer by a lithography process; then, using the patterned photoresist as a mask, performing a wet or dry etching process on the conductive material layer to form the first source S1, the first drain D1, the second source S2, the second drain D2, the third source S3 and the third drain D3; and then, removing the patterned photoresist. In other words, the first source S1, the first drain D1, the second source S2, the second drain D2, the third source S3 and the third drain D3 are formed at the same time, for example.

After the above process, the production of the active element substrate 10 can be basically completed.

FIG3 is a schematic cross-sectional view of an active element substrate 20 according to an embodiment of the present invention. It must be noted that the embodiment of FIG3 uses the component numbers and some contents of the embodiment of FIG1, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, which will not be elaborated here.

The main difference between the active device substrate 20 of FIG. 3 and the active device substrate 10 of FIG. 1 is that the gate dielectric layer 120 of the active device substrate 20 is aligned with the first channel region 112b and the third channel region 116b, and the ferroelectric material layer 140 is aligned with the first channel region 112b and the second channel region 114b.

Referring to FIG. 3 , the gate dielectric layer 120 includes a first gate dielectric pattern 122 and a second gate dielectric pattern 124, wherein the first gate dielectric pattern 122 and the second gate dielectric pattern 124 are separated from each other. The ferroelectric material layer 140 includes a first ferroelectric material pattern 142 and a second ferroelectric material pattern 144, wherein the first ferroelectric material pattern 142 and the second ferroelectric material pattern 144 are separated from each other.

The first gate dielectric pattern 122 and the first ferroelectric material pattern 142 overlap the first gate G1 and the first channel region 112b in the normal direction ND of the top surface of the substrate 100, and the first gate dielectric pattern 122 and the first ferroelectric material pattern 142 are located between the first gate G1 and the first channel region 112b, and form a gate dielectric structure GI. The sidewalls of the first gate dielectric pattern 122 and the sidewalls of the first ferroelectric material pattern 142 are aligned with the sidewalls of the first gate G1.

The second ferroelectric material pattern 144 overlaps the second gate G2 and the second channel region 114b in the normal direction ND of the top surface of the substrate 100, and the second ferroelectric material pattern 144 is located between the second gate G2 and the second channel region 114b. The sidewall of the second ferroelectric material pattern 144 is aligned with the sidewall of the second gate G2.

The second gate dielectric pattern 124 overlaps the third gate G3 and the third channel region 116b in the normal direction ND of the top surface of the substrate 100, and the second gate dielectric pattern 124 is located between the third gate G3 and the third channel region 116b. The sidewall of the second gate dielectric pattern 124 is aligned with the sidewall of the third gate G3.

In this embodiment, the gate dielectric layer 120 and the ferroelectric material layer 140 do not overlap the first source region 112a, the first drain region 112c, the second source region 114a, the second drain region 114c, the third source region 116a, and the third drain region 116c. The material layer 140 affects the doping concentration of the first source region 112a, the first drain region 112c, the second source region 114a, the second drain region 114c, the third source region 116a and the third drain region 116c, and can also avoid the negative impact of the doping process on the gate dielectric layer 120 and the ferroelectric material layer 140.

Figures 4A to 4D are cross-sectional schematic diagrams of the manufacturing method of the active element substrate of Figure 3.

Please refer to FIG. 4A , continuing the step of FIG. 2C , a first gate G1 and a second gate G2 are formed on the ferroelectric material layer 140, and a third gate G3 is formed on the gate dielectric layer 120. Then, the gate dielectric layer 120 and the ferroelectric material layer 140 are patterned using the first gate G1, the second gate G2 and the third gate G3 as masks to form a first gate dielectric pattern 122, a second gate dielectric pattern 124, a first ferroelectric material pattern 142 and a second ferroelectric material pattern 144.

Next, please refer to Figure 4B. With the first gate G1, the second gate G2 and the third gate G3 as masks, a doping process P is performed on the first semiconductor layer 112', the second semiconductor layer 114' and the third semiconductor layer 116' to form a first semiconductor layer 112 including a first source region 112a, a first channel region 112b and a first drain region 112c, a second semiconductor layer 114 including a second source region 114a, a second channel region 114b and a second drain region 114c, and a third semiconductor layer 116 including a third source region 116a, a third channel region 116b and a third drain region 116c. In some embodiments, the doping process P includes a hydrogen plasma process or an ion implantation process.

4C , an interlayer dielectric layer 150 is formed on the gate dielectric layer 120 and the ferroelectric material layer 140. The interlayer dielectric layer 150 contacts the first source region 112a, the first drain region 112c, the second source region 114a, the second drain region 114c, the third source region 116a, and the third drain region 116c. In some embodiments, the interlayer dielectric layer 150 contains hydrogen atoms, and thus, the hydrogen atoms can be diffused into the first semiconductor layer 112, the second semiconductor layer 114, and the third semiconductor layer 116 by heat treatment to adjust the resistivity of the first semiconductor layer 112, the second semiconductor layer 114, and the third semiconductor layer 116. In some embodiments, the doping process is performed by hydrogen atoms in the interlayer dielectric layer 150, so the doping process P of FIG. 4B can be omitted.

Please refer to FIG. 4D , openings O1, O2, O3, O4, O5, and O6 are formed in the interlayer dielectric layer 150.

Finally, please return to FIG. 3 to form a first source S1, a first drain D1, a second source S2, a second drain D2, a third source S3, and a third drain D3 on the interlayer dielectric layer 150. The first source S1 and the first drain D1 are filled into the openings O1 and O2, respectively, to be electrically connected to the first source region 112a and the first drain region 112c of the first semiconductor layer 112. The second source S2 and the second drain D2 are filled into the openings O3 and O4, respectively, to be electrically connected to the second source region 114a and the second drain region 114c of the second semiconductor layer 114. The third source S3 and the third drain D3 are filled into the openings O5 and O6 respectively to be electrically connected to the third source region 116a and the third drain region 116c of the third semiconductor layer 116.

After the above process, the production of the active element substrate 20 can be basically completed.

FIG5 is a schematic diagram of an equivalent circuit of a pixel circuit PX according to an embodiment of the present invention. The pixel circuit PX of FIG5 is, for example, a pixel circuit PX on an active element substrate in any of the aforementioned embodiments.

Please refer to Figure 5, the pixel circuit PX includes a first semiconductor element T1, a second semiconductor element T2, a third semiconductor element T3, a storage capacitor Cst and a light-emitting element EL.

The first semiconductor element T1 can be used as a switch transistor. The first gate of the first semiconductor element T1 is electrically connected to the voltage V _S1 (for example, the scanning line voltage), the first drain (or the first source) of the first semiconductor element T1 is electrically connected to the voltage V _data (for example, the data line voltage), and the first source (or the first drain) of the first semiconductor element T1 is electrically connected to the first node a.

The second semiconductor element T2 has the functions of a driving transistor and a memory. The second gate of the second semiconductor element T2 is electrically connected to the first node a. The second drain of the second semiconductor element T2 is electrically connected to the voltage V _DD , and the second source of the second semiconductor element T2 is electrically connected to the second node b.

The third semiconductor element T3 can be used as a sensing transistor, for example. The third gate of the third semiconductor element T3 is electrically connected to the voltage V _S2 , the third drain of the third semiconductor element T3 is electrically connected to the third node c, and the third source of the third semiconductor element T3 is electrically connected to the voltage V _sus . The voltage V _S2 is used to control the switch of the third semiconductor element T3, so as to transmit the information of the driving current to the external chip through the third semiconductor element T3.

One end of the storage capacitor Cst is electrically connected to the first node a, and the other end of the storage capacitor Cst is electrically connected to the third node c. The second node b is electrically connected to the third node c. Since the second gate of the second semiconductor element T2 is electrically connected to the storage capacitor Cst, even if the first semiconductor element T1 is turned off, the second semiconductor element T2 can continue to be turned on for a short period of time.

One end of the light emitting element EL is electrically connected to the second node b, and the other end of the light emitting element EL is electrically connected to the voltage V _SS . The brightness of the light emitting element EL will change due to the different magnitudes of the driving current passing through the second semiconductor element T2 . The light emitting element EL is, for example, a micro light emitting diode, an organic light emitting diode or other light emitting element.

In this embodiment, at the first node a, the first source (or first drain) of the first semiconductor element T1, the second gate of the second semiconductor element T2, and one end of the storage capacitor Cst are electrically connected to each other. At the second node b, the second source of the second semiconductor element T2 and one end of the light-emitting element EL are electrically connected to each other. At the third node c, the third drain of the third semiconductor element T3 and the other end of the storage capacitor Cst are electrically connected to each other. The third drain of the third semiconductor element T3 is electrically connected to the second source of the second semiconductor element T2 through the third node c and the second node b.

FIG6 is a flowchart of a pixel compensation operation of a display device according to an embodiment of the present invention under the pixel circuit setting of FIG5.

The following briefly describes the operation of pixel compensation in the display device under the setting of the pixel circuit PX, please refer to Figure 5 and Figure 6. First, the display device is in a closed state, so that the pixel circuit PX performs gray level sensing in the background. The gray level sensing method is, for example, to turn on the first semiconductor element T1, the second semiconductor element T2 and the third semiconductor element T3, so that the driving voltage through the first semiconductor element T1 and the driving current of the second semiconductor element T2 can be transmitted to the external chip through the third semiconductor element T3.

Then, the external chip establishes a corresponding model through signal processing and calculation, and then calculates the corresponding compensation information. After that, the compensation information is written into the pixel circuit PX. For example, the first semiconductor element T1, the second semiconductor element T2, and the third semiconductor element T3 are turned on to write the compensation information calculated by the external chip into the ferroelectric material layer in the second semiconductor element T2. Specifically, by polarizing the ferroelectric material layer in the second semiconductor element T2, the information is recorded in the second semiconductor element T2. In some embodiments, the third semiconductor element T3 is turned on to reduce the voltage difference between the source and the drain of the second semiconductor element T2, or further to eliminate the voltage difference between the source and the drain of the second semiconductor element T2.

Next, the display device is turned on. Since the compensation information has been written into the second semiconductor element T2, the size of the driving current through the second semiconductor element T2 can be adjusted, thereby achieving the function of pixel compensation. In some embodiments, when the display device is turned on, the third semiconductor element T3 is in the off state.

In summary, the second semiconductor element T2 of the present invention has the function of a memory, so there is no need to set up a compensation memory in an external chip, which simplifies the overall system and reduces costs.

10: Active component substrate

100: Substrate

102: Buffer layer

112: First semiconductor layer

112a: First source region

112b: First channel area

112c: First drain region

114: Second semiconductor layer

114a: Second source region

114b: Second channel area

114c: Second drain region

116: Third semiconductor layer

116a: The third source region

116b: Third channel area

116c: The third drain area

120: Gate dielectric layer

140: Ferroelectric material layer

150: Interlayer dielectric layer

D1: First drain

D2: Second drain

D3: Third drain

G1: First gate

G2: Second gate

G3: The third gate

GI: Gate dielectric structure

ND: Normal direction

O1,O2,O3,O4,O5,O6: Open

S1: First source

S2: Second source

S3: The third source

T1: First semiconductor element

T2: Second semiconductor element

T3: The third semiconductor element

Claims (16)

An active device substrate comprises: a substrate; a first semiconductor device disposed on the substrate, wherein the first semiconductor device comprises: a first gate and a first semiconductor layer, wherein a gate dielectric structure is sandwiched between the first gate and the first semiconductor layer, wherein the gate dielectric structure comprises a stack of a portion of a gate dielectric layer and a portion of a ferroelectric material layer; a first source and a first drain electrically connected to the first semiconductor layer; and a second semiconductor layer. The body element is disposed on the substrate and electrically connected to the first semiconductor element, wherein the second semiconductor element includes: a second gate and a second semiconductor layer, wherein another portion of the ferroelectric material layer is sandwiched between the second gate and the second semiconductor layer, wherein the distance between the first gate and the first semiconductor layer is greater than the distance between the second gate and the second semiconductor layer; a second source and a second drain, electrically connected to the second semiconductor layer. An active device substrate as described in claim 1, wherein the ferroelectric material layer extends from between the first gate and the gate dielectric layer to between the second gate and the second semiconductor layer. An active device substrate as described in claim 1, wherein the ferroelectric material layer surrounds the first source, the first drain, the second source and the second drain. An active device substrate as described in claim 1, wherein the first source, the first drain, the second source and the second drain pass through the ferroelectric material layer. An active device substrate as described in claim 1, wherein the ferroelectric material layer includes: a first ferroelectric material pattern overlapping the first gate; and a second ferroelectric material pattern overlapping the second gate, wherein the first ferroelectric material pattern is separated from the second ferroelectric material pattern. An active device substrate as described in claim 5, wherein the sidewall of the first ferroelectric material pattern is aligned with the sidewall of the first gate, and the sidewall of the second ferroelectric material pattern is aligned with the sidewall of the second gate. An active element substrate as described in claim 1, wherein the subcritical swing of the first semiconductor element is less than 60mV/dec. The active device substrate as claimed in claim 1, wherein the material of the ferroelectric material layer comprises Ni _x Mg _y Zn _0.98-y O or Hf _z Zr _1-z O ₂ , wherein x is 0.01 to 0.05, y is 0.05 to 0.15, and z is 0.4 to 0.6. An active device substrate as described in claim 1, wherein the thickness of the ferroelectric material layer is 5 nm to 50 nm, and the thickness of the gate dielectric layer is 50 nm to 100 nm. The active device substrate as described in claim 1 further includes: a third semiconductor device disposed on the substrate and electrically connected to the second semiconductor device, wherein the third semiconductor device includes: a third gate and a third semiconductor layer, wherein another portion of the gate dielectric layer is sandwiched between the third gate and the third semiconductor layer; a third source and a third drain, electrically connected to the third semiconductor layer. An active device substrate as described in claim 11, wherein the first drain is electrically connected to the second gate, and the third drain is electrically connected to the second source. A method for manufacturing an active element substrate includes: forming a first semiconductor layer and a second semiconductor layer on a substrate; forming a gate dielectric layer on the first semiconductor layer; forming a ferroelectric material layer on the gate dielectric layer and the second semiconductor layer; forming a first gate and a second gate on the ferroelectric material layer, wherein the gate dielectric layer is located at The first gate is between the first semiconductor layer, and the ferroelectric material layer is between the first gate and the first semiconductor layer and between the second gate and the second semiconductor layer; a first source and a first drain are formed which are electrically connected to the first semiconductor layer; and a second source and a second drain are formed which are electrically connected to the second semiconductor layer. The manufacturing method of the active element substrate as described in claim 12 further includes: using the first gate and the second gate as masks to perform a doping process on the first semiconductor layer and the second semiconductor layer. The manufacturing method of the active device substrate as described in claim 12 further includes: using the first gate and the second gate as masks to pattern the gate dielectric layer and the ferroelectric material layer. A method for manufacturing an active device substrate as described in claim 12, wherein the gate dielectric layer includes an opening exposing the second semiconductor layer, and the ferroelectric material layer is filled in the opening to contact the second semiconductor layer. The manufacturing method of the active element substrate as described in claim 12 further includes: forming a third semiconductor layer on the substrate, wherein the first semiconductor layer, the second semiconductor layer and the third semiconductor layer are formed at the same time; forming the gate dielectric layer on the third semiconductor layer; forming a third gate on the gate dielectric layer, wherein the first gate, the second gate and the third gate are formed at the same time; and forming a third source and a third drain electrically connected to the third semiconductor layer, wherein the first source, the first drain, the second source, the second drain, the third source and the third drain are formed at the same time.

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