TWI869115B - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

A semiconductor device includes a substrate, a bottom gate electrode, a bottom gate dielectric layer, a first semiconductor layer, a second semiconductor layer, a top gate dielectric layer, a top gate electrode, a source electrode and a drain electrode. The bottom gate electrode is located above the substrate. The bottom gate dielectric layer is located on the bottom gate electrode. The first semiconductor layer is located on the bottom gate dielectric layer. The second semiconductor layer is located on the first semiconductor layer and includes an intrinsic semiconductor region and a heavily doped region. The top gate dielectric layer is located on the second semiconductor layer. The top gate electrode is located on the top gate dielectric layer and overlapping with the intrinsic semiconductor region. The source electrode is connected to the intrinsic semiconductor region. The drain electrode is connected to the heavily doped region.

Description

Semiconductor device and method for manufacturing the same

The present invention relates to a semiconductor device and a manufacturing method thereof.

At present, the channel material of thin film transistors mostly uses amorphous silicon semiconductors. This semiconductor has the advantages of simple process and low cost, so it is widely favored by various thin film transistors. However, with the rapid development of display technology, the resolution of display panels is also constantly improving. In order to adapt to the reduction in the size of thin film transistors in pixel circuits, many manufacturers are actively developing new high carrier mobility semiconductor materials, such as metal oxide semiconductor materials.

The present invention provides a semiconductor device and a manufacturing method thereof, which can improve the problem of drain induced barrier lowering (DIBL).

At least one embodiment of the present invention provides a semiconductor device, which includes a substrate, a bottom gate, a bottom gate dielectric layer, a first semiconductor layer, a second semiconductor layer, a top gate dielectric layer, a top gate, a source and a drain. The bottom gate is located above the substrate. The bottom gate dielectric layer is located on the bottom gate. The first semiconductor layer is located on the bottom gate dielectric layer. The second semiconductor layer is located on the first semiconductor layer and includes an intrinsic semiconductor region and a heavily doped region. The top gate dielectric layer is located on the second semiconductor layer. The top gate is located on the top gate dielectric layer and overlaps the intrinsic semiconductor region in the normal direction of the top surface of the substrate. The source is connected to the intrinsic semiconductor region. The drain is connected to the heavily doped region. The bottom gate overlaps the first contact surface between the source and the intrinsic semiconductor region in the normal direction of the top surface of the substrate and does not overlap the second contact surface between the drain and the heavily doped region.

At least one embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising the following steps: forming a bottom gate above a substrate; forming a bottom gate dielectric layer on the bottom gate; forming a first semiconductor layer on the bottom gate dielectric layer; forming a second semiconductor layer on the first semiconductor layer; forming a top gate dielectric layer on the second semiconductor layer; forming a shielding structure on the top gate dielectric layer; performing a re-doping process on the second semiconductor layer using the shielding structure as a mask to form an intrinsic semiconductor region and a re-doped region in the second semiconductor layer. The shielding structure is patterned to form a top gate, wherein the top gate overlaps the intrinsic semiconductor region in a normal direction of the top surface of the substrate. A source connected to the intrinsic semiconductor region is formed. A drain connected to the heavily doped region is formed.

1 is a schematic cross-sectional view of a semiconductor device 10A according to an embodiment of the present invention. The semiconductor device 10A includes a substrate 100, a bottom gate 210, a bottom gate dielectric layer 120, a first semiconductor layer 300, a second semiconductor layer 400, a top gate dielectric layer 130, a top gate 220, a source 232, and a drain 234. In this embodiment, the semiconductor device 10A further includes an interlayer dielectric layer 140 and a planar layer 150.

The substrate 100 is, for example, a rigid substrate, and its material may be glass, quartz, organic polymer or opaque/reflective material (e.g., conductive material, metal, wafer, ceramic or other applicable material) or other applicable materials. However, the present invention is not limited thereto, and in other embodiments, the substrate 100 may also be a flexible substrate or a stretchable substrate. For example, the materials of the flexible substrate and the stretchable substrate include polyimide (PI), polydimethylsiloxane (PDMS), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyester (PES), polymethylmethacrylate (PMMA), polycarbonate (PC), polyurethane PU or other suitable materials.

The bottom gate 210 is located above the substrate 100. In the present embodiment, the bottom gate 210 directly contacts the top surface of the substrate 100, but the present invention is not limited thereto. In other embodiments, a buffer layer (not shown) may be additionally included between the bottom gate 210 and the substrate 100. The buffer layer, for example, includes silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride or other suitable materials or a combination of the foregoing materials or a stack of the foregoing materials. In some embodiments, the buffer layer is used, for example, as a hydrogen barrier layer and/or a metal ion barrier layer.

In some embodiments, the material of the bottom gate 210 includes, for example, metals such as chromium, gold, silver, copper, tin, lead, uranium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, nickel, alloys of the above metals, oxides of the above metals, nitrides of the above metals, or combinations thereof or other conductive materials. The bottom gate 210 may have a single-layer structure or a multi-layer structure.

The bottom gate dielectric layer 120 is located on the bottom gate 210 and covers the top and side surfaces of the bottom gate 210. In some embodiments, the material of the bottom gate dielectric layer 120 includes silicon oxide, silicon oxynitride, silicon nitride, aluminum oxide, vanadium oxide, zirconium oxide or other suitable materials or combinations thereof.

The first semiconductor layer 300 is located on the bottom gate dielectric layer 120. The second semiconductor layer 400 is located on the first semiconductor layer 300. In some embodiments, the materials of the first semiconductor layer 300 and the second semiconductor layer 400 include oxides of three or more of gallium (Ga), zinc (Zn), indium (In), tin (Sn), aluminum (Al), and tungsten (W) (for example, metal oxides such as indium gallium zinc tin oxide (IGZTO), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), aluminum zinc tin oxide (AZTO), and indium tungsten zinc oxide (IWZO)), indium gallium oxide (IGO), indium tungsten oxide (IWO), indium zinc oxide (IZO), or tungsten-based rare earth doped metal oxides (for example, Ln-IZO), or other suitable metal oxides or combinations of the above materials.

In some embodiments, the first semiconductor layer 300 and the second semiconductor layer 400 include different metal oxides and have different carrier mobilities. For example, the first semiconductor layer 300 includes indium tin zinc oxide (ITZO), indium zinc oxide (IZO), or other suitable metal oxides, and the second semiconductor layer 400 includes indium gallium zinc oxide (IGZO) or other suitable metal oxides. In some embodiments, before an additional doping process (such as a hydrogen treatment process) is performed, the carrier mobility of the first semiconductor layer 300 is greater than the carrier mobility of the second semiconductor layer 400.

In this embodiment, the first semiconductor layer 300 is not subjected to an additional doping process, and the second semiconductor layer 400 is subjected to a heavy doping process and includes an intrinsic semiconductor region 420 and a heavy doped region 410. The heavy doped region 410 is a region subjected to a heavy doping process, and the intrinsic semiconductor region 420 is a region not subjected to an additional doping process. In some embodiments, the resistivity of the first semiconductor layer 300 is lower than the resistivity of the intrinsic semiconductor region 420. In this embodiment, the first semiconductor layer 300 is not subjected to an additional doping process, and the resistivity of the first semiconductor layer 300 is higher than the resistivity of the heavily doped region 410, but the present invention is not limited thereto. In other embodiments, the first semiconductor layer 300 is also subjected to a heavy doping process to have a doped region with a low resistivity, and the resistivity of the doped region in the first semiconductor layer 300 may be higher than, equal to, or lower than the resistivity of the heavily doped region 410.

In some embodiments, the heavily doped region 410 includes a first portion 412 and a second portion 414 separated from each other. The intrinsic semiconductor region 420 is sandwiched between the first portion 412 and the second portion 414.

In some embodiments, the energy band gap of the first semiconductor layer 300 is different from the energy band gap of the second semiconductor layer 400, which helps to form a channel for carrier flow at the interface between the first semiconductor layer 300 and the second semiconductor layer 400 when the semiconductor device 10A is operated, thereby increasing the conduction current of the semiconductor device 10A. In some embodiments, the energy band gap of the first semiconductor layer 300 is smaller than the energy band gap of the second semiconductor layer 400.

The top gate dielectric layer 130 is located on the second semiconductor layer 400 and covers the first semiconductor layer 300 and the second semiconductor layer 400. In some embodiments, the material of the top gate dielectric layer 130 includes silicon oxide, silicon oxynitride, silicon nitride, aluminum oxide, vanadium oxide, zirconium oxide or other suitable materials or combinations thereof.

The top gate 220 is located on the top gate dielectric layer 130 and overlaps the intrinsic semiconductor region 420 of the second semiconductor layer 400 in the normal direction ND of the top surface of the substrate 100. In this embodiment, part of the intrinsic semiconductor region 420 overlaps the top gate 220 in the normal direction ND, while another part of the intrinsic semiconductor region 420 does not overlap the top gate 220 in the normal direction ND.

In some embodiments, the material of the top gate 220 includes, for example, metals such as chromium, gold, silver, copper, tin, lead, uranium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, nickel, alloys of the above metals, oxides of the above metals, nitrides of the above metals, or combinations thereof or other conductive materials. The top gate 220 may have a single-layer structure or a multi-layer structure.

In some embodiments, the top gate 220 is electrically connected to the bottom gate 210 and is electrically connected to the same signal source. For example, the top gate 220 is electrically connected to the bottom gate 210 through a conductive portion not shown in FIG. 1. In other embodiments, the top gate 220 and the bottom gate 210 can be operated separately and electrically connected to different signal sources.

The interlayer dielectric layer 140 is located on the top gate 220 and the top gate dielectric layer 130, and covers the top gate 220. In some embodiments, the material of the interlayer dielectric layer 140 includes silicon oxide, silicon oxynitride, silicon nitride, aluminum oxide, vanadium oxide, zirconium oxide or other suitable materials or combinations thereof.

The planarization layer 150 is located on the interlayer dielectric layer 140. In some embodiments, the material of the planarization layer 150 includes silicon oxide, silicon oxynitride, silicon nitride, aluminum oxide, einsteinium oxide, zirconium oxide, organic insulating material or other suitable materials or a combination of the foregoing materials.

The source 232 and the drain 234 are located above the second semiconductor layer 400. In the present embodiment, the source 232 and the drain 234 are located on the planar layer 150 and contact the second semiconductor layer 400 through the first through hole TH1 and the second through hole TH2, respectively. The first through hole TH1 and the second through hole TH2 pass through the planar layer 150, the interlayer dielectric layer 140, and the top gate dielectric layer 130. In some embodiments, the source 232 and the drain 234 are separated from the first semiconductor layer 300. The second semiconductor layer 400 is located between the source 232 and the first semiconductor layer 300 and between the drain 234 and the first semiconductor layer 300.

The source 232 is filled into the first through hole TH1 and connected to the intrinsic semiconductor region 420 of the second semiconductor layer 400. In this embodiment, there is a Schottky contact between the source 232 and the intrinsic semiconductor region 420. In other words, there is a Schottky barrier between the source 232 and the intrinsic semiconductor region 420. The short channel effect caused by the drain-induced potential barrier drop (DIBL) can be improved through the Schottky barrier between the source 232 and the intrinsic semiconductor region 420, thereby avoiding the leakage problem of the semiconductor device 10A. The intrinsic semiconductor region 420 extends continuously from the source 232 to below the top gate 220.

The drain electrode 234 fills the second through hole TH2 and is connected to the heavily doped region 410 of the second semiconductor layer 400. In some embodiments, the interface resistance between the drain electrode 234 and the heavily doped region 410 is smaller than the interface resistance between the source electrode 232 and the intrinsic semiconductor region 420. In some embodiments, the energy barrier between the drain electrode 234 and the heavily doped region 410 is lower than the energy barrier between the source electrode 232 and the intrinsic semiconductor region 420. In some embodiments, the drain electrode 234 and the heavily doped region 410 have an ohmic contact.

The bottom gate 210 overlaps the first contact surface 231 between the source 232 and the intrinsic semiconductor region 420 in the normal direction ND of the top surface of the substrate 100 and does not overlap the second contact surface 233 between the drain 234 and the heavily doped region 410. In some embodiments, the bottom gate 210 overlaps the source 232 in the normal direction ND of the top surface of the substrate 100 and does not overlap the drain 234. In some embodiments, the resistivity of the first contact surface 231 is greater than the resistivity of the second contact surface 233.

The bottom gate 210 overlaps the first contact surface 231 between the source 232 and the heavily doped region 410 in the normal direction ND, and the bottom gate 210 extends from below the first contact surface 231 to below the top gate 220, thereby forming a source-gate transistor (SGT) with excellent gate control capability. The bottom gate 210 helps to generate and control a depletion region in the intrinsic semiconductor region 420 below the source 232, thereby reducing the saturation drain voltage (Vdsat), thereby reducing energy consumption.

2A to 2I are cross-sectional views of a method for manufacturing the semiconductor device 10A of FIG1 . Referring to FIG2A , a bottom gate 210 is formed on a substrate 100 . A bottom gate dielectric layer 120 is formed on the bottom gate 210 .

Referring to FIG. 2B , a first semiconductor layer 300 is formed on the bottom gate dielectric layer 120. In some embodiments, a blanket first semiconductor material layer is first formed on the bottom gate dielectric layer 120. Then, a patterned photoresist layer is formed on the first semiconductor material layer. Finally, the first semiconductor material layer is etched using the patterned photoresist layer as a mask to form the first semiconductor layer 300.

Referring to FIG. 2C , a second semiconductor layer 400 is formed on the first semiconductor layer 300. In some embodiments, a blanket second semiconductor material layer is first formed on the bottom gate dielectric layer 120 and the first semiconductor layer 300. Then, a patterned photoresist layer is formed on the second semiconductor material layer. Finally, the second semiconductor material layer is etched using the patterned photoresist layer as a mask to form the second semiconductor layer 400.

In this embodiment, the first semiconductor layer 300 and the second semiconductor layer 400 are defined by different masks, but the present invention is not limited thereto. In other embodiments, the first semiconductor material layer and the second semiconductor material layer are continuously deposited on the bottom gate dielectric layer 120. Then, a patterned photoresist layer is formed on the second semiconductor material layer. Finally, the second semiconductor material layer and the first semiconductor material layer are etched using the patterned photoresist layer as a mask to form the second semiconductor layer 400 and the first semiconductor layer 300. In other words, the first semiconductor layer 300 and the second semiconductor layer 400 can be defined by the same mask, and the first semiconductor layer 300 and the second semiconductor layer 400 have substantially the same orthographic projection shape on the substrate 100.

2D , a top gate dielectric layer 130 is formed on the second semiconductor layer 400. A shielding structure 220′ is formed on the top gate dielectric layer 130. In this embodiment, the shielding structure 220′ partially overlaps the first semiconductor layer 300 and the second semiconductor layer 400 in the normal direction ND of the top surface of the substrate 100.

The second semiconductor layer 400 is subjected to a re-doping process HP using the shielding structure 220′ as a mask to form an intrinsic semiconductor region 420 and a re-doped region 410 in the second semiconductor layer 400. Specifically, the portion of the second semiconductor layer 400 not shielded by the shielding structure 220′ will be doped in the re-doping process HP and will be the re-doped region 410. The portion of the second semiconductor layer 400 shielded by the shielding structure 220′ will not be doped in the re-doping process HP and will be the intrinsic semiconductor region 420.

In some embodiments, the re-doping process HP provides hydrogen elements to the re-doped region 410 of the second semiconductor layer 400, thereby reducing the resistivity of the re-doped region 410.

2E , the shielding structure 220′ is patterned to form a top gate 220. The top gate 220 overlaps the intrinsic semiconductor region 420 in the normal direction ND of the top surface of the substrate 100.

2F , an interlayer dielectric layer 140 is formed on the top gate 220 and the top gate dielectric layer 130 .

2G , after forming the interlayer dielectric layer 140, the interlayer dielectric layer 140 and the top gate dielectric layer 130 are optionally etched to form a first opening O1 and a second opening O2 that expose the second semiconductor layer 400. The first opening O1 and the second opening O2 expose the intrinsic semiconductor region 420 and the heavily doped region 410 of the second semiconductor layer 400, respectively.

2H , a planarization layer 150 is optionally formed on the interlayer dielectric layer 140. In this embodiment, the planarization layer 150 is filled into the first opening O1 and the second opening O2.

2I , an etching process is performed on the planar layer 150 to form a first through hole TH1 and a second through hole TH2 that expose the second semiconductor layer 400. The first through hole TH1 and the second through hole TH2 correspond to the positions of the first opening O1 and the second opening O2, respectively.

In this embodiment, before forming the planar layer 150, the interlayer dielectric layer 140 and the top gate dielectric layer 130 are first etched to form the first opening O1 and the second opening O2, but the present invention is not limited thereto. In other embodiments, after forming the planar layer 150, the planar layer 150, the interlayer dielectric layer 140 and the top gate dielectric layer 130 are etched to form the first through hole TH1 and the second through hole TH2 that expose the second semiconductor layer 400. In other words, before forming the planar layer 150, the interlayer dielectric layer 140 and the top gate dielectric layer 130 may not be etched.

Finally, returning to FIG. 1 , a source electrode 232 and a drain electrode 234 are formed on the planar layer 150. The source electrode 232 and the drain electrode 234 are respectively filled into the first through hole TH1 and the second through hole TH2 to respectively connect the intrinsic semiconductor region 420 and the heavily doped region 410.

In this embodiment, the source 232 and the drain 234 are formed on the planar layer 150, but the present invention is not limited thereto. In other embodiments, after forming the first opening O1 and the second opening O2 of the interlayer dielectric layer 140 as shown in FIG. 2G, the source 232 and the drain 234 are formed on the interlayer dielectric layer 140, and the source 232 and the drain 234 are respectively filled into the first opening O1 and the second opening O2 to connect to the second semiconductor layer 400.

FIG3 is a cross-sectional schematic diagram of a semiconductor device 10B according to an embodiment of the present invention. It should be noted that the embodiment of FIG3 uses the component numbers and some contents of the embodiment of FIG1, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.

The main difference between the semiconductor device 10B of FIG. 3 and the semiconductor device 10A of FIG. 1 is that the first semiconductor layer 300 and the second semiconductor layer 400 of the semiconductor device 10B have different orthographic projection shapes on the substrate 100 .

Referring to FIG. 3 , in this embodiment, the width of the second semiconductor layer 400 is different from the width of the first semiconductor layer 300. For example, the width of the second semiconductor layer 400 is greater than the width of the first semiconductor layer 300. The second semiconductor layer 400 extends and covers the side of the first semiconductor layer 300. In this embodiment, both sides of the first semiconductor layer 300 are covered by the second semiconductor layer 400, but the present invention is not limited thereto. In other embodiments, at least one side of the first semiconductor layer 300 is covered by the second semiconductor layer 400.

FIG4 is a cross-sectional schematic diagram of a semiconductor device 10C according to an embodiment of the present invention. It should be noted that the embodiment of FIG4 uses the component numbers and part of the content of the embodiment of FIG1, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical content is omitted. The description of the omitted part can refer to the aforementioned embodiment, and will not be repeated here.

The main difference between the semiconductor device 10C of FIG. 4 and the semiconductor device 10A of FIG. 1 is that the first semiconductor layer 300 of the semiconductor device 10C is doped to include a bottom doping region 310 and a channel region 320 .

For example, when performing the heavy doping process HP as shown in FIG. 2D , a portion of the dopants are implanted into the second semiconductor layer 400 to form a heavy doped region 410 in the second semiconductor layer 400. At the same time, another portion of the dopants diffuse into the first semiconductor layer 300 to form a bottom doped region 310 in the first semiconductor layer 300. In some embodiments, the dopants are, for example, hydrogen, and both the bottom doped region 310 and the heavy doped region 410 include hydrogen. The bottom doped region 310 is located between the heavy doped region 410 and the bottom gate dielectric layer 120.

In this embodiment, the heavily doped region 410 includes a first portion 412 and a second portion 414 separated from each other. Similarly, the bottom doped region 310 also includes a first portion 312 and a second portion 314 separated from each other.

The undoped portion of the first semiconductor layer 300 is a channel region 320. The channel region 320 is located between the intrinsic semiconductor region 420 and the bottom gate dielectric layer 120. In this embodiment, the channel region 320 is located between the first portion 312 and the second portion 314.

In summary, in the semiconductor device of the present invention, a Schottky contact is provided between the source and the intrinsic semiconductor region of the second semiconductor layer, and the bottom gate overlaps the first contact surface between the source and the intrinsic semiconductor region in the normal direction of the top surface of the substrate, thereby improving the problem of drain-induced barrier lowering (DIBL) and reducing the saturated drain voltage of the semiconductor device to reduce energy consumption.

10A, 10B, 10C: semiconductor device 100: substrate 120: bottom gate dielectric layer 130: top gate dielectric layer 140: interlayer dielectric layer 150: planar layer 210: bottom gate 220: top gate 220': shielding structure 231: first contact surface 232: source 233: second contact surface 234: drain 300: first semiconductor layer 310: bottom doping region 312, 412: first part 314, 414: second part 320: channel region 400: second semiconductor layer 410: Re-doping area 420: Intrinsic semiconductor area HP: Re-doping process ND: Normal direction O1: First opening O2: Second opening TH1: First through hole TH2: Second through hole

FIG. 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. FIG. 2A to FIG. 2I are schematic cross-sectional views of a method for manufacturing the semiconductor device of FIG. 1 . FIG. 3 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. FIG. 4 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

10A: Semiconductor devices

100: Substrate

120: Bottom gate dielectric layer

130: Top gate dielectric layer

140: Interlayer dielectric layer

150: Flat layer

210: Bottom gate

220: Top Gate

231: First contact surface

232: Source

233: Second contact surface

234: Drainage

300: First semiconductor layer

400: Second semiconductor layer

410: Remixed area

412: Part 1

414: Part 2

420: Intrinsic semiconductor region

ND: Normal direction

TH1: First through hole

TH2: Second through hole

Claims (9)

A semiconductor device comprises: a substrate; a bottom gate located above the substrate; a bottom gate dielectric layer located on the bottom gate; a first semiconductor layer located on the bottom gate dielectric layer; a second semiconductor layer located on the first semiconductor layer and comprising an intrinsic semiconductor region and a heavily doped region, wherein the first semiconductor layer and the second semiconductor layer comprise different metal oxides, and the resistivity of the first semiconductor layer is lower than the resistivity of the intrinsic semiconductor region; A top gate dielectric layer is located on the second semiconductor layer; a top gate is located on the top gate dielectric layer and overlaps the intrinsic semiconductor region in the normal direction of the top surface of the substrate; a source is connected to the intrinsic semiconductor region; and a drain is connected to the heavily doped region, wherein the bottom gate overlaps a first contact surface between the source and the intrinsic semiconductor region in the normal direction of the top surface of the substrate and does not overlap a second contact surface between the drain and the heavily doped region. A semiconductor device as described in claim 1, wherein a Schottky contact is provided between the source and the intrinsic semiconductor region, wherein the resistivity of the first contact surface is greater than the resistivity of the second contact surface. A semiconductor device as described in claim 1, wherein the source and the drain are separated from the first semiconductor layer. A semiconductor device as described in claim 1, wherein the bottom gate overlaps the first contact surface in the normal direction, and the bottom gate extends from below the first contact surface to below the top gate. A semiconductor device as described in claim 1, wherein the resistivity of the first semiconductor layer is higher than the resistivity of the heavily doped region. A semiconductor device as described in claim 1, wherein the heavily doped region includes a first portion and a second portion separated from each other, wherein the intrinsic semiconductor region is sandwiched between the first portion and the second portion. A semiconductor device as described in claim 1, wherein the first semiconductor layer includes: a bottom doped region located between the heavily doped region and the bottom gate dielectric layer, wherein both the bottom doped region and the heavily doped region include hydrogen elements; and a channel region located between the intrinsic semiconductor region and the bottom gate dielectric layer. A method for manufacturing a semiconductor device includes: forming a bottom gate on a substrate; forming a bottom gate dielectric layer on the bottom gate; forming a first semiconductor layer on the bottom gate dielectric layer; forming a second semiconductor layer on the first semiconductor layer, wherein the first semiconductor layer and the second semiconductor layer include different metal oxides; forming a top gate dielectric layer on the second semiconductor layer; forming a shielding structure on the top gate dielectric layer; using the shielding structure as a mask to shield the top gate dielectric layer; The second semiconductor layer performs a heavily doped process to form an intrinsic semiconductor region and a heavily doped region in the second semiconductor layer, wherein the resistivity of the first semiconductor layer is lower than the resistivity of the intrinsic semiconductor region; patterning the shielding structure to form a top gate, wherein the top gate overlaps the intrinsic semiconductor region in a normal direction of the top surface of the substrate; forming a source, the source is connected to the intrinsic semiconductor region; and forming a drain, the drain is connected to the heavily doped region. A manufacturing method as described in claim 8, wherein when performing the heavy doping process, a portion of the dopants are implanted into the second semiconductor layer to form the heavy doped region in the second semiconductor layer, and another portion of the dopants are diffused into the first semiconductor layer to form a bottom doped region in the first semiconductor layer, wherein the bottom doped region is located between the heavy doped region and the bottom gate dielectric layer.

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