TWI874761B - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

A semiconductor device includes a substrate, a semiconductor structure, a first gate dielectric layer, a first gate, a source and a drain. The semiconductor structure includes a first metal oxide layer and a second metal oxide layer. The second metal oxide layer covers a top surface and sidewalls of the first metal oxide layer. The second metal oxide layer has a stepped structure at the sidewalls of the first metal oxide layer. The carrier mobility of the first metal oxide layer is greater than that of a channel region of the second metal oxide layer. A thickness of the second metal oxide layer is greater than or equal to a thickness of the first metal oxide layer. The difference between a width of the first gate electrode and a width of the first metal oxide layer is less than 0.5 µm.

Description

Semiconductor device and method for manufacturing the same

The present invention relates to a semiconductor device and a manufacturing method thereof, and in particular to a semiconductor device including a metal oxide layer and a manufacturing method thereof.

Currently, common thin film transistors usually use amorphous silicon semiconductors as channels. Amorphous silicon semiconductors are widely used in various thin film transistors due to their simple manufacturing process and low cost.

With the advancement of display technology, the resolution of display panels has been increasing year by year. In order to shrink the thin film transistors in the pixel circuit, many manufacturers are committed to developing new semiconductor materials, such as metal oxide semiconductor materials. Among metal oxide semiconductor materials, indium gallium zinc oxide (IGZO) has the advantages of small area and high electron mobility, so it is regarded as an important new semiconductor material.

The present invention provides a semiconductor device, the semiconductor structure of which has the advantages of high carrier mobility and can reduce the hot carrier effect caused by the electric field on the gate.

The present invention provides a method for manufacturing a semiconductor device, which has the advantages of high process yield and low cost.

At least one embodiment of the present invention provides a semiconductor device. The semiconductor device includes a substrate, a semiconductor structure, a first gate dielectric layer, a first gate, a source and a drain. The semiconductor structure is located on the substrate and includes a first metal oxide layer and a second metal oxide layer. The second metal oxide layer covers the top surface and side walls of the first metal oxide layer. The second metal oxide layer has a step structure at the side walls of the first metal oxide layer. The carrier mobility of the first metal oxide layer is greater than the carrier mobility of the channel region of the second metal oxide layer. The thickness of the second metal oxide layer is greater than or equal to the thickness of the first metal oxide layer. The first gate dielectric layer is located on the semiconductor structure. The first gate is located on the first gate dielectric layer and overlaps the first metal oxide layer. The difference between the width of the first gate and the width of the first metal oxide layer is less than 0.5 microns. The source and the drain are electrically connected to the second metal oxide layer.

At least one embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising: forming a first metal oxide layer on a substrate; forming a second metal oxide layer on the first metal oxide layer, wherein the second metal oxide layer covers the top surface and sidewalls of the first metal oxide layer, and the second metal oxide layer has a step structure at the sidewalls of the first metal oxide layer, wherein the thickness of the second metal oxide layer is greater than or equal to the thickness of the first metal oxide layer; forming a first gate dielectric layer on the second metal oxide layer; oxide layer; forming a first gate on the first gate dielectric layer, and the first gate overlaps the first metal oxide layer, wherein the width difference between the first gate and the first metal oxide layer is less than 0.5 microns; forming a source region, a drain region and a channel region between the source region and the drain region in the second metal oxide layer, wherein the carrier mobility of the first metal oxide layer is greater than the carrier mobility of the channel region of the second metal oxide layer; forming a source and a drain electrically connected to the second metal oxide layer.

Fig. 1A is a schematic top view of a semiconductor device according to an embodiment of the present invention. Fig. 1B is a schematic cross-sectional view taken along line A-A' of Fig. 1A.

1A and 1B , the semiconductor device 10A includes a substrate 100, a semiconductor structure 220, a first gate dielectric layer 120, a first gate 240, a source 232, and a drain 234. In some embodiments, the semiconductor device 10A further includes a buffer layer 102 and an interlayer dielectric layer 130.

The material of the substrate 100 can be glass, quartz, organic polymer or opaque/reflective material (e.g., conductive material, metal, wafer, ceramic or other applicable material) or other applicable materials. If a conductive material or metal is used, an insulating layer (not shown) is covered on the substrate 100 to avoid short circuit problems.

The buffer layer 102 is formed on the surface of the substrate 100. The material of the buffer layer 102 includes, for example, silicon oxide, silicon nitride, silicon oxynitride or other insulating materials. In some embodiments, the buffer layer 102 is a single-layer structure or a multi-layer structure.

The semiconductor structure 220 is located on the substrate 100. In this embodiment, the semiconductor structure 220 is formed on the buffer layer 102. The semiconductor structure 220 includes a first metal oxide layer 220A and a second metal oxide layer 220B.

The first metal oxide layer 220A is formed on the buffer layer 102. In some embodiments, the first metal oxide layer 220A includes at least one of indium, tungsten, gallium, zinc, and tin. For example, the first metal oxide layer 220A is indium tungsten zinc oxide (InWZnO, IWZO) or indium gallium zinc oxide (InGaZnO, IGZO).

The second metal oxide layer 220B covers the top surface t and the sidewall s of the first metal oxide layer 220A. The second metal oxide layer 220B is conformally formed on the first metal oxide layer 220A, and the second metal oxide layer 220B has a step structure st at the sidewall s of the first metal oxide layer 220A. In some embodiments, the second metal oxide layer 220B includes at least one of indium, gallium, and zinc. For example, the second metal oxide layer 220B is indium gallium zinc oxide (InGaZnO, IGZO).

In this embodiment, the second metal oxide layer 220B includes a source region 222, a drain region 226, and a channel region 224 located between the source region 222 and the drain region 226. The channel region 224 overlaps the first metal oxide layer 220A in the normal direction ND of the top surface of the substrate 100, and the channel region 224 covers the top surface t of the first metal oxide layer 220A. The source region 222 and the drain region 226 cover the sidewall s of the first metal oxide layer 220A. In some embodiments, the step structure st is located in the source region 222 and/or the drain region 226.

The source region 222 and the drain region 226 are, for example, hydrogen-doped regions. The resistivity of the source region 222 and the drain region 226 is less than the resistivity of the channel region 224. In some embodiments, the oxygen concentration of the source region 222 and the drain region 226 is less than the oxygen concentration of the channel region 224, and the hydrogen concentration of the source region 222 and the drain region 226 is greater than the hydrogen concentration of the channel region 224.

The carrier mobility of the first metal oxide layer 220A is greater than the carrier mobility of the channel region 224 of the second metal oxide layer 220B. For example, the carrier mobility of the first metal oxide layer 220A is 25 cm ² /Vs to 35 cm ² /Vs, and the carrier mobility of the channel region 224 of the second metal oxide layer 220B is 8 cm ² /Vs to 10 cm ² /Vs. In some embodiments, the carrier mobility of the first metal oxide layer 220A is greater than the carrier mobility of the channel region 224 of the second metal oxide layer 220B by adjusting the oxygen concentration and/or indium concentration in the first metal oxide layer 220A and the second metal oxide layer 220B. In some embodiments, the oxygen concentration of the channel region 224, the source region 222, and the drain region 226 of the second metal oxide layer 220B is greater than the oxygen concentration of the first metal oxide layer 220A, and the oxygen vacancy concentration of the channel region 224 of the second metal oxide layer 220B is less than the oxygen vacancy concentration of the first metal oxide layer 220A. In some embodiments, the indium concentration of the channel region 224, the source region 222, and the drain region 226 of the second metal oxide layer 220B is less than the indium concentration of the first metal oxide layer 220A.

The thickness T2 of the second metal oxide layer 220B is greater than or equal to the thickness T1 of the first metal oxide layer 220A. In some embodiments, the thickness T2 of the second metal oxide layer 220B is 15 nm to 25 nm, and the thickness T1 of the first metal oxide layer 220A is 5 nm to 15 nm.

The first gate dielectric layer 120 is located on the semiconductor structure 220. The first gate dielectric layer 120 includes inorganic materials (eg, silicon oxide, silicon nitride, silicon oxynitride, tantalum oxide, aluminum oxide, other suitable materials, or a stack of at least two of the above materials), organic materials, other suitable materials, or a combination thereof.

The first gate 240 is located on the first gate dielectric layer 120 and overlaps the channel region 224 of the first metal oxide layer 220A and the second metal oxide layer 220B in the normal direction ND of the top surface of the substrate 100. The material of the first gate 240 is, for example, a metal such as chromium, gold, silver, copper, tin, lead, cobalt, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, the above alloys, the above metal oxides, the above metal nitrides, or a combination thereof or other conductive materials. In this embodiment, the first gate 240 is a stacked layer of titanium, aluminum, and titanium. When the first gate 240 includes aluminum, the first gate 240 can serve as a hydrogen barrier layer, thereby reducing the probability of hydrogen atoms diffusing into the channel region 224.

The difference between the width W1 of the first gate 240 and the width W2 of the first metal oxide layer 220A is less than 0.5 micrometers. In a preferred embodiment, the edge 240s of the first gate 240 and the sidewall s of the first metal oxide layer 220A overlap in the normal direction ND of the top surface of the substrate 100. Based on the above, the probability of the first metal oxide layer 220A being damaged by etching solution or ultraviolet light in subsequent processes can be reduced.

The horizontal distance d between the edge 240s of the first gate 240 and the discontinuity of the step structure st of the second metal oxide layer 220B is less than 0.5 micrometers, and the step structure st of the semiconductor structure 220 is substantially adjacent to the edge of the first gate 240. When the semiconductor device 10A is operated, a strong electric field is likely to appear at the edge 240s of the first gate 240. By arranging the step structure st with a thickness variation of the semiconductor structure 220 at a position adjacent to the edge 240s of the first gate 240, the hot carrier effect caused by the electric field on the first gate 240 can be reduced, thereby improving the reliability of the semiconductor device 10A.

The interlayer dielectric layer 130 is located on the first gate dielectric layer 120 and the first gate 240. Two contact holes penetrate the interlayer dielectric layer 130 and the first gate dielectric layer 120 and extend to the source region 222 and the drain region 226 of the second metal oxide layer 220B.

The interlayer dielectric layer 130 includes an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride, tantalum oxide, aluminum oxide, other suitable materials, or a stack of at least two of the above materials), an organic material or other suitable materials, or a combination thereof. In some embodiments, the interlayer dielectric layer 130 includes hydrogen. In some embodiments, during the process of manufacturing the semiconductor device 10A, the hydrogen in the interlayer dielectric layer 130 is diffused to the source region 222 and the drain region 226 of the second metal oxide layer 220B through a heat treatment process, but the present invention is not limited thereto. In other embodiments, hydrogen elements are diffused into the source region 222 and the drain region 226 through a hydrogen plasma process or other doping processes.

The source 232 and the drain 234 are located on the interlayer dielectric layer 130 and are filled in the first contact hole TH1 and the second contact hole TH2 penetrating the interlayer dielectric layer 130 and the first gate dielectric layer 120 to electrically connect the source region 222 and the drain region 226 of the second metal oxide layer 220B, respectively.

The signal line 310 is located on the interlayer dielectric layer 130 and fills the third contact hole TH3 penetrating the interlayer dielectric layer 130 to be electrically connected to the first gate 240 .

In some embodiments, the signal line 310, the source 232 and the drain 234 are made of metals such as chromium, gold, silver, copper, tin, lead, uranium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, their alloys, their metal oxides, their metal nitrides, or their combinations or other conductive materials. In this embodiment, the signal line 310, the source 232 and the drain 234 are stacked layers of titanium, aluminum and titanium.

In this embodiment, the semiconductor device 10A is a top-gate thin film transistor, which has the advantage of fast response and is suitable for use as a switching element.

2A to 2G are cross-sectional schematic views of a method for manufacturing the semiconductor device 10A of FIGS. 1A and 1B .

2A to 2B , a first metal oxide layer 220A is formed on the substrate 100. First, a blanket first metal oxide material layer 220A' is formed on the substrate 100 and the buffer layer 102, and then, a patterned photoresist (not shown) is formed on the first metal oxide material layer 220A' by a lithography process; then, a wet or dry etching process is performed on the first metal oxide material layer 220A' using the patterned photoresist as a mask to form the first metal oxide layer 220A; finally, the patterned photoresist is removed.

Referring to FIG. 2C to FIG. 2D , a second metal oxide layer 220B is formed on the first metal oxide layer 220A. First, a blanket second metal oxide material layer 220B' is formed on the substrate 100, the buffer layer 102, and the first metal oxide layer 220A. Then, a patterned photoresist (not shown) is formed on the second metal oxide material layer 220B' by a lithography process. Then, a wet or dry etching process is performed on the second metal oxide material layer 220B' using the patterned photoresist as a mask to form the second metal oxide layer 220B. Finally, the patterned photoresist is removed.

The second metal oxide layer 220B covers the top surface t and the sidewall s of the first metal oxide layer 220A, and the second metal oxide layer 220B has a step structure st at the sidewall s of the first metal oxide layer 220A.

2E , a first gate dielectric layer 120 is formed on the second metal oxide layer 220B. A first gate 240 is formed on the first gate dielectric layer 120. The first gate 240 overlaps the first metal oxide layer 220A.

The second metal oxide layer 220B is subjected to a doping process P using the first gate 240 as a mask to form a source region 222, a drain region 226, and a channel region 224 in the second metal oxide layer 220B. In some embodiments, the doping process P is, for example, a hydrogen plasma process.

2F , an interlayer dielectric layer 130 is formed on the first gate 240 and the first gate dielectric layer 120 . The interlayer dielectric layer 130 covers the first gate 240 .

2G , a first contact hole TH1 and a second contact hole TH2 are formed through the interlayer dielectric layer 130 and the first gate dielectric layer 120 . In some embodiments, a third contact hole (not shown in FIG. 2G ) is also formed through the interlayer dielectric layer 130 .

Finally, please return to FIG. 1A and FIG. 1B to form the source 232, the drain 234, and the signal line 310. The source 232, the drain 234, and the signal line 310 belong to the same patterned conductive layer. The source 232 and the drain 234 are respectively filled into the first contact hole TH1 and the second contact hole TH2 to electrically connect the source region 222 and the drain region 226 of the second metal oxide layer 220B. The signal line 310 is filled into the third contact hole TH3 to electrically connect the first gate 240.

Based on the above, the semiconductor structure 220 of the semiconductor device 10A includes a first metal oxide layer 220A and a second metal oxide layer 220B, and the carrier mobility of the first metal oxide layer 220A is greater than the carrier mobility of the channel region 224 of the second metal oxide layer 220B, thereby improving the drain current of the semiconductor device 10A. In addition, since the difference between the width W1 of the first gate 240 and the width W2 of the first metal oxide layer 220A is less than 0.5 microns, the hot carrier effect caused by the electric field on the first gate 240 can be reduced, thereby improving the reliability of the semiconductor device 10A.

FIG. 3A is a schematic top view of a semiconductor device according to an embodiment of the present invention. FIG. 3B is a schematic cross-sectional view of line A-A' of FIG. 3A. It should be noted that the embodiments of FIG. 3A and FIG. 3B use the component numbers and partial contents of the embodiments of FIG. 1A and FIG. 1B, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.

The main difference between the semiconductor device 10B in FIGS. 3A and 3B and the semiconductor device 10A in FIG. 1A is that the semiconductor device 10B further includes a second gate dielectric layer 110 and a second gate 210 .

The second gate 210 is located on the substrate 100. In some embodiments, a buffer layer (not shown in FIG. 3A ) is sandwiched between the second gate 210 and the substrate 100. The material of the second gate 210 is, for example, a metal such as chromium, gold, silver, copper, tin, lead, uranium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, or the like, the alloys thereof, the metal oxides thereof, the metal nitrides thereof, or a combination thereof or other conductive materials.

The second gate dielectric layer 110 is located on the second gate 210. The second gate dielectric layer 110 is located between the semiconductor structure 220 and the substrate 100. The second gate 210 is located between the second gate dielectric layer 110 and the substrate 100. The second gate 210 overlaps the semiconductor structure 220, and the width W3 of the second gate 210 is greater than the width W2 of the first metal oxide layer 210. In some embodiments, the first gate 240 is filled in the fourth contact hole TH4 penetrating the first gate dielectric layer 120 and the second gate dielectric layer 110, and is electrically connected to the second gate 210.

In this embodiment, the semiconductor structure 220 is formed on the second gate dielectric layer 110. The semiconductor structure 220 includes a first metal oxide layer 220A and a second metal oxide layer 220B.

The carrier mobility of the first metal oxide layer 220A is greater than the carrier mobility of the channel region 224 of the second metal oxide layer 220B. For example, the carrier mobility of the first metal oxide layer 220A is 65 cm ² /Vs to 75 cm ² /Vs, and the carrier mobility of the channel region 224 of the second metal oxide layer 220B is 16 cm ² /Vs to 23 cm ² /Vs. In some embodiments, the carrier mobility of the first metal oxide layer 220A is greater than the carrier mobility of the channel region 224 of the second metal oxide layer 220B by adjusting the oxygen concentration and/or indium concentration in the first metal oxide layer 220A and the second metal oxide layer 220B. In some embodiments, the oxygen concentration of the channel region 224, the source region 222, and the drain region 226 of the second metal oxide layer 220B is greater than the oxygen concentration of the first metal oxide layer 220A, and the oxygen vacancy concentration of the channel region 224 of the second metal oxide layer 220B is less than the oxygen vacancy concentration of the first metal oxide layer 220A. In some embodiments, the indium concentration of the channel region 224, the source region 222, and the drain region 226 of the second metal oxide layer 220B is less than the indium concentration of the first metal oxide layer 220A.

The thickness T2 of the second metal oxide layer 220B is greater than or equal to the thickness T1 of the first metal oxide layer 220A. In some embodiments, the thickness T2 of the second metal oxide layer 220B is 15 nm to 25 nm, and the thickness T1 of the first metal oxide layer 220A is 5 nm to 15 nm.

The first gate 240 is located on the first gate dielectric layer 120 and overlaps the first metal oxide layer 220A, the channel region 224 of the second metal oxide layer 220B and the second gate 210 in the normal direction ND of the top surface of the substrate 100. The semiconductor structure 220 is located between the first gate 240 and the second gate 210.

The difference between the width W1 of the first gate 240 and the width W2 of the first metal oxide layer 220A is less than 0.5 micrometers. In a preferred embodiment, the edge 240s of the first gate 240 and the sidewall s of the first metal oxide layer 220A overlap in the normal direction ND of the top surface of the substrate 100. Based on the above, the probability of the first metal oxide layer 220A being damaged by etching solution or ultraviolet light in subsequent processes can be reduced.

The horizontal distance d between the edge 240s of the first gate 240 and the discontinuity of the step structure st of the second metal oxide layer 220B is less than 0.5 micrometers, and the step structure st of the semiconductor structure 220 is substantially adjacent to the edge 240s of the first gate 240. When the semiconductor device 10B is operated, a strong electric field is likely to appear at the edge 240s of the first gate 240. By arranging the step structure st with a thickness variation of the semiconductor structure 220 at a position adjacent to the edge of the first gate 240, the hot carrier effect caused by the electric field on the first gate 240 can be reduced, thereby improving the reliability of the semiconductor device 10B.

In this embodiment, the semiconductor device 10B includes a dual-gate thin film transistor, which has the advantage of a large drain current and is suitable for use as a driving element.

4A to 4G are cross-sectional schematic views of a method for manufacturing the semiconductor device 10B of FIGS. 3A and 3B .

4A , a second gate 210 is formed on the substrate 100 . A second gate dielectric layer 110 is formed on the second gate 210 . A blanket first metal oxide material layer 220A′ is formed on the substrate 100 and the second gate dielectric layer 110 .

Referring to FIG. 4B , the first metal oxide material layer 220A′ is patterned to form a first metal oxide layer 220A on the second gate dielectric layer 110.

4C to 4D , the second metal oxide layer 220B is formed on the first metal oxide layer 220A. First, a blanket second metal oxide material layer 220B' is formed on the substrate 100, the second gate dielectric layer 110 and the first metal oxide layer 220A, and then the second metal oxide material layer 220B' is patterned to form the second metal oxide layer 220B.

Referring to FIG. 4E , a first gate dielectric layer 120 is formed on the second metal oxide layer 220B. A first gate 240 is formed on the first gate dielectric layer 120. The first gate 240 overlaps the first metal oxide layer 220A. In some embodiments, before forming the first gate 240, a fourth contact hole (not shown in FIG. 4E ) is formed penetrating the first gate dielectric layer 120 and the second gate dielectric layer 110. The first gate 240 is electrically connected to the second gate 210 through the fourth contact hole.

The second metal oxide layer 220B is subjected to a doping process P using the first gate 240 as a mask to form a source region 222, a drain region 226, and a channel region 224 in the second metal oxide layer 220B. In some embodiments, the doping process P is, for example, a hydrogen plasma process.

4F , an interlayer dielectric layer 130 is formed on the first gate 240 and the first gate dielectric layer 120 . The interlayer dielectric layer 130 covers the first gate 240 .

4G , a first contact hole TH1 and a second contact hole TH2 are formed through the interlayer dielectric layer 130 and the first gate dielectric layer 120 . In some embodiments, a third contact hole (not shown in FIG. 4G ) is also formed through the interlayer dielectric layer 130 .

Finally, please return to FIG. 3A and FIG. 3B to form the source 232, the drain 234, and the signal line 310. The source 232, the drain 234, and the signal line 310 belong to the same patterned conductive layer. The source 232 and the drain 234 are respectively filled into the first contact hole TH1 and the second contact hole TH2 to electrically connect the source region 222 and the drain region 226 of the second metal oxide layer 220B. The signal line 310 is filled into the third contact hole TH3 to electrically connect the first gate 240.

Based on the above, the semiconductor structure 220 of the semiconductor device 10B includes a first metal oxide layer 220A and a second metal oxide layer 220B, and the carrier mobility of the first metal oxide layer 220A is greater than the carrier mobility of the channel region 224 of the second metal oxide layer 220B, thereby improving the drain current of the semiconductor device 10B. In addition, since the difference between the width W1 of the first gate 240 and the width W2 of the first metal oxide layer 220A is less than 0.5 microns, the hot carrier effect caused by the electric field on the first gate 240 can be reduced, thereby improving the reliability of the semiconductor device 10B.

FIG. 5A is a schematic top view of a semiconductor device according to an embodiment of the present invention. FIG. 5B is a schematic cross-sectional view of line A-A' and line B-B' of FIG. 5A. It should be noted that the embodiments of FIG. 3A and FIG. 3B use the component numbers and part of the contents of the embodiments of FIG. 1A and FIG. 1B, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.

The main difference between the semiconductor device 10C of FIGS. 5A and 5B and the semiconductor device 10B of FIG. 3A is that the source 232 of the semiconductor device 10C is electrically connected to the second gate 210 .

5A and 5B , the semiconductor device 10C further includes a transfer electrode 320. The transfer electrode 320 is filled in a fifth contact hole TH5 penetrating the second gate dielectric layer 110 and the first gate dielectric layer 120 to be electrically connected to the second gate 210, and the source 232 is filled in a sixth contact hole TH6 penetrating the interlayer gate dielectric layer 130 to be electrically connected to the transfer electrode 320. In this embodiment, the first gate 240 and the second gate 210 are not directly connected.

In this embodiment, the source 232 of the semiconductor device 10C is electrically connected to the second gate 210, so that it has the advantage of small parasitic capacitance and is suitable for being used as a driving element.

In some embodiments, the carrier mobility of the first metal oxide layer 220A is 30 cm ² /Vs to 40 cm ² /Vs, and the carrier mobility of the channel region 224 of the second metal oxide layer 220B is 3 cm ² /Vs to 6 cm ² /Vs.

6A to 6H are cross-sectional schematic views of a method for manufacturing the semiconductor device of FIG. 5A and FIG. 5B .

6A , a second gate 210 is formed on the substrate 100 . A second gate dielectric layer 110 is formed on the second gate 210 . A blanket first metal oxide material layer 220A′ is formed on the substrate 100 and the second gate dielectric layer 110 .

Referring to FIG. 6B , the first metal oxide material layer 220A′ is patterned to form a first metal oxide layer 220A on the second gate dielectric layer 110.

6C to 6D , the second metal oxide layer 220B is formed on the first metal oxide layer 220A. First, a blanket second metal oxide material layer 220B' is formed on the substrate 100, the second gate dielectric layer 110 and the first metal oxide layer 220A, and then the second metal oxide material layer 220B' is patterned to form the second metal oxide layer 220B.

6E , a first gate dielectric layer 120 is formed on the second metal oxide layer 220B. A fifth contact hole TH5 is formed penetrating the second gate dielectric layer 110 and the first gate dielectric layer 120 . The fifth contact hole TH5 exposes the second gate 210 .

6F, a first gate 240 and a transfer electrode 320 are formed on the first gate dielectric layer 120. The first gate 240 and the transfer electrode 320 belong to the same patterned conductive layer. The first gate 240 overlaps the first metal oxide layer 220A. The transfer electrode 320 fills the fifth contact hole TH5 to electrically connect the second gate 210. The transfer electrode 320 is formed on the second gate 210.

The second metal oxide layer 220B is subjected to a doping process P using the first gate 240 as a mask to form a source region 222, a drain region 226, and a channel region 224 in the second metal oxide layer 220B. In some embodiments, the doping process P is, for example, a hydrogen plasma process.

6G , an interlayer dielectric layer 130 is formed on the first gate 240 , the first gate dielectric layer 120 , and the transfer electrode 320 . The interlayer dielectric layer 130 covers the first gate 240 and the transfer electrode 320 .

6H , a first contact hole TH1 and a second contact hole TH2 are formed through the interlayer dielectric layer 130 and the first gate dielectric layer 120. In some embodiments, a sixth contact hole TH6 of the interlayer gate dielectric layer 130 is also formed at the same time. In some embodiments, a third contact hole (not shown in FIG. 6H ) is also formed through the interlayer dielectric layer 130 at the same time.

Finally, please return to FIG. 5A and FIG. 5B to form the source 232, the drain 234, and the signal line 310. The source 232, the drain 234, and the signal line 310 belong to the same patterned conductive layer. The source 232 and the drain 234 are respectively filled in the first contact hole TH1 and the second contact hole TH2 to electrically connect the source region 222 and the drain region 226 of the second metal oxide layer 220B. The source 232 is filled in the sixth contact hole TH6 to electrically connect the transfer electrode 320, and the source 232 is electrically connected to the second gate 210 through the transfer electrode 320. The signal line 310 is filled in the third contact hole TH3 to electrically connect the first gate 240.

Based on the above, the semiconductor structure 220 of the semiconductor device 10C includes a first metal oxide layer 220A and a second metal oxide layer 220B, and the carrier mobility of the first metal oxide layer 220A is greater than the carrier mobility of the channel region 224 of the second metal oxide layer 220B, thereby improving the drain current of the semiconductor device 10C. In addition, since the difference between the width W1 of the first gate 240 and the width W2 of the first metal oxide layer 220A is less than 0.5 microns, the hot carrier effect caused by the electric field on the first gate 240 can be reduced, thereby improving the reliability of the semiconductor device 10B.

10A, 10B, 10C: semiconductor device 100: substrate 102: buffer layer 110: second gate dielectric layer 120: first gate dielectric layer 130: interlayer dielectric layer 210: second gate 220: semiconductor structure 220A: first metal oxide layer 220A’: first metal oxide material layer 220B: second metal oxide layer 220B’: second metal oxide material layer 222: source region 224: channel region 226: drain region 232: source 234: drain 240: first gate 240s: edge 310: signal line 320: transfer electrode A-A’, B-B’: line d: horizontal distance ND: normal direction P: doping process s: side wall t: top surface st: step structure T1, T2: thickness TH1: first contact hole TH2: second contact hole TH3: third contact hole TH4: fourth contact hole TH5: fifth contact hole TH6: sixth contact hole W1, W2, W3: width

FIG. 1A is a schematic top view of a semiconductor device according to an embodiment of the present invention. FIG. 1B is a schematic cross-sectional view of line A-A’ of FIG. 1A. FIG. 2A to FIG. 2G are schematic cross-sectional views of a method for manufacturing the semiconductor device of FIG. 1A and FIG. 1B. FIG. 3A is a schematic top view of a semiconductor device according to an embodiment of the present invention. FIG. 3B is a schematic cross-sectional view of line A-A’ of FIG. 3A. FIG. 4A to FIG. 4G are schematic cross-sectional views of a method for manufacturing the semiconductor device of FIG. 3A and FIG. 3B. FIG. 5A is a schematic top view of a semiconductor device according to an embodiment of the present invention. FIG. 5B is a schematic cross-sectional view of line A-A’ and line B-B’ of FIG. 5A. Figures 6A to 6H are cross-sectional schematic diagrams of the manufacturing method of the semiconductor device of Figures 5A and 5B.

10A: Semiconductor devices

100: Substrate

102: Buffer layer

120: First gate dielectric layer

130: Interlayer dielectric layer

220:Semiconductor structure

220A: First metal oxide layer

220B: Second metal oxide layer

222: Source region

224: Channel area

226: Drainage area

232: Source

234: Drainage

240: First Gate

240s: Edge

A-A’: line

d: horizontal distance

ND: Normal direction

s: side wall

t: Top

st: ladder structure

T1, T2: thickness

W1,W2: Width

Claims (20)

A semiconductor device comprises: a substrate; a semiconductor structure located on the substrate and comprising: a first metal oxide layer; and a second metal oxide layer, wherein the second metal oxide layer covers the top surface and the side wall of the first metal oxide layer, and the second metal oxide layer has a step structure at the side wall of the first metal oxide layer, wherein the second metal oxide layer comprises a source region, a drain region and a channel region located between the source region and the drain region, wherein the resistivity of the source region and the drain region is less than the resistivity of the channel region, and the channel region is A semiconductor structure is provided with a semiconductor structure having a first gate region overlapping the first metal oxide layer, the carrier mobility of the first metal oxide layer is greater than the carrier mobility of the channel region of the second metal oxide layer, and the thickness of the second metal oxide layer is greater than or equal to the thickness of the first metal oxide layer; a first gate dielectric layer located on the semiconductor structure; a first gate electrode located on the first gate dielectric layer and overlapping the first metal oxide layer, wherein the difference between the width of the first gate electrode and the width of the first metal oxide layer is less than 0.5 micrometers; and a source electrode and a drain electrode electrically connected to the second metal oxide layer. A semiconductor device as described in claim 1, wherein the oxygen concentration of the channel region of the second metal oxide layer is greater than the oxygen concentration of the first metal oxide layer. A semiconductor device as described in claim 1, wherein the indium concentration of the channel region of the second metal oxide layer is less than the indium concentration of the first metal oxide layer. A semiconductor device as described in claim 1, wherein the thickness of the second metal oxide layer is 15nm to 25nm, and the thickness of the first metal oxide layer is 5nm to 15nm. The semiconductor device as described in claim 1 further includes: a second gate dielectric layer located between the semiconductor structure and the substrate; and a second gate electrode located between the second gate dielectric layer and the substrate and overlapping the semiconductor structure, wherein the width of the second gate electrode is greater than the width of the first metal oxide layer. A semiconductor device as described in claim 5, wherein the source is electrically connected to the second gate. A semiconductor device as described in claim 1, wherein the sidewall of the first gate overlaps with the sidewall of the first metal oxide layer in the normal direction of the top surface of the substrate. A semiconductor device as described in claim 1, wherein the step structure is located in the source region and/or the drain region. A semiconductor device as described in claim 1, wherein the material of the second metal oxide layer is indium gallium zinc oxide, and the material of the first metal oxide layer is indium gallium zinc oxide or indium tungsten zinc oxide. A semiconductor device as described in claim 1, wherein the horizontal distance between the sidewall of the first gate and the discontinuity of the step structure of the second metal oxide layer is less than 0.5 micrometers. A method for manufacturing a semiconductor device includes: forming a first metal oxide layer on a substrate; forming a second metal oxide layer on the first metal oxide layer, wherein the second metal oxide layer covers the top surface and sidewalls of the first metal oxide layer, and the second metal oxide layer has a step structure at the sidewalls of the first metal oxide layer, wherein the thickness of the second metal oxide layer is greater than or equal to the thickness of the first metal oxide layer; forming a first gate dielectric layer on the second metal oxide layer; forming a first gate on the first gate dielectric layer, and the first gate The first gate is overlapped on the first metal oxide layer, wherein the width difference between the first gate and the first metal oxide layer is less than 0.5 microns; the second metal oxide layer is subjected to a doping process using the first gate as a mask to form a source region, a drain region and a channel region between the source region and the drain region in the second metal oxide layer, wherein the carrier mobility of the first metal oxide layer is greater than the carrier mobility of the channel region of the second metal oxide layer; and a source and a drain are formed, wherein the source and the drain are electrically connected to the second metal oxide layer. The method for manufacturing a semiconductor device as described in claim 11 further includes: forming a second gate on the substrate; forming a second gate dielectric layer on the second gate; and forming the first metal oxide layer on the second gate dielectric layer. The method for manufacturing a semiconductor device as described in claim 12 further includes: forming a transfer electrode on the second gate; forming an inter-dielectric layer on the transfer electrode and the first gate; and forming the source and the drain on the inter-dielectric layer, wherein the source is electrically connected to the second gate through the transfer electrode. A method for manufacturing a semiconductor device as described in claim 12, wherein the width of the second gate is greater than the width of the first metal oxide layer. A method for manufacturing a semiconductor device as described in claim 11, wherein the material of the second metal oxide layer includes indium gallium zinc oxide, and the material of the first metal oxide layer includes indium gallium zinc oxide or indium tungsten zinc oxide. A method for manufacturing a semiconductor device as described in claim 11, wherein the horizontal distance between the sidewall of the first gate and the discontinuity of the step structure of the second metal oxide layer is less than 0.5 micrometers. A method for manufacturing a semiconductor device as described in claim 11, wherein the thickness of the second metal oxide layer is 15nm to 25nm, and the thickness of the first metal oxide layer is 5nm to 15nm. A method for manufacturing a semiconductor device as described in claim 11, wherein the sidewall of the first gate is aligned with the sidewall of the first metal oxide layer. A semiconductor device comprises: a substrate; a semiconductor structure located on the substrate and comprising: a first metal oxide layer; and a second metal oxide layer, wherein the second metal oxide layer covers the top surface and sidewalls of the first metal oxide layer, and the second metal oxide layer has a step structure at the sidewalls of the first metal oxide layer, the carrier mobility of the first metal oxide layer is greater than the carrier mobility of a channel region of the second metal oxide layer, and the second metal oxide layer The thickness of the first gate is greater than or equal to the thickness of the first metal oxide layer; a first gate dielectric layer is located on the semiconductor structure; a first gate is located on the first gate dielectric layer and overlaps the first metal oxide layer, wherein the difference between the width of the first gate and the width of the first metal oxide layer is less than 0.5 microns, wherein the sidewall of the first gate overlaps the sidewall of the first metal oxide layer in the normal direction of the top surface of the substrate; and a source and a drain are electrically connected to the second metal oxide layer. A method for manufacturing a semiconductor device includes: forming a first metal oxide layer on a substrate; forming a second metal oxide layer on the first metal oxide layer, wherein the second metal oxide layer covers the top surface and sidewalls of the first metal oxide layer, and the second metal oxide layer has a step structure at the sidewalls of the first metal oxide layer, wherein the thickness of the second metal oxide layer is greater than or equal to the thickness of the first metal oxide layer; forming a first gate dielectric layer on the second metal oxide layer; forming a first gate on the first gate dielectric layer, and the second metal oxide layer has a step structure at the sidewalls of the first metal oxide layer; forming a first gate on the second metal oxide layer; forming a first gate on the first gate dielectric layer; forming a first gate on the second ... first gate dielectric layer; forming a first gate on the second gate dielectric layer; forming a first gate on the first gate dielectric layer; forming a first gate on the second gate dielectric layer; forming a first gate on the first gate dielectric layer; forming a first gate on the second gate dielectric layer; forming a first gate on the first gate dielectric layer; forming a first gate on the second gate dielectric layer; forming a first gate on the first gate dielectric layer; forming a first gate on the second gate dielectric layer; forming a first gate on the first gate dielectric layer; forming a first gate on the first gate dielectric layer; forming a first gate on the first gate dielectric layer; forming a first gate on the first gate dielectric layer; forming a first gate on the first gate dielectric layer; forming a first gate on the first gate dielectric layer; forming a first A gate is overlapped on the first metal oxide layer, wherein the difference between the width of the first gate and the width of the first metal oxide layer is less than 0.5 micrometers, wherein the sidewall of the first gate is aligned with the sidewall of the first metal oxide layer; a source region, a drain region and a channel region between the source region and the drain region are formed in the second metal oxide layer, wherein the carrier mobility of the first metal oxide layer is greater than the carrier mobility of the channel region of the second metal oxide layer; and a source and a drain are formed, wherein the source and the drain are electrically connected to the second metal oxide layer.

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