TWI862313B - Semiconductor device and manufacturing method thtereof - Google Patents

Abstract

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a first gate, a first semiconductor layer, a first gate dielectric layer, a second gate, a second gate dielectric layer, a second semiconductor layer, a third gate dielectric layer, a first contact hole, a second contact hole, a source, a drain and a third gate. The first semiconductor layer is over the first gate. The first gate dielectric layer is between the first gate and the first semiconductor layer. The second gate is over the first semiconductor layer. The second gate dielectric layer is between the first semiconductor layer and the second gate. The second semiconductor layer is over the second gate. The third gate dielectric layer is between the second gate and the second semiconductor layer. The first contact hole and the second contact hole continuously penetrates through the second dielectric layer and the third dielectric layer respectively. The source and the drain respectively fill the first contact hole and the second contact hole and electrically connect to the first semiconductor layer and the second semiconductor layer. The third gated is over the second semiconductor layer.

Description

Semiconductor device and method for manufacturing the same

The present invention relates to a device, and in particular to a semiconductor device.

Dual-channel thin film transistors improve the shortcomings of traditional single-gate thin film transistors and dual-gate thin film transistors, such as high driving voltage and low reliability, and are therefore suitable as driving elements for organic light-emitting diode display devices or micro-light-emitting diode display devices. However, in order to connect the two channels of the dual-channel thin film transistor to the same source and drain, the source and drain need to be connected by forming deep vias that penetrate at least four insulating layers or forming two electrically connected vias that are connected to the two channels respectively. Limited by design rules and etching conditions, it is difficult to reduce the diameter of deep vias and the distance between two electrically connected vias, resulting in a large area occupied by the dual-channel thin film transistor, which is not conducive to the design of high-resolution, thin and short circuits. In addition, the channel may be damaged during the formation of the via, which affects the performance of the dual-channel thin film transistor.

The present invention provides a semiconductor device having a reduced area and good performance.

The semiconductor device of the present invention comprises a substrate, a first gate, a first semiconductor layer, a first gate dielectric layer, a second gate, a second gate dielectric layer, a second semiconductor layer, a third gate dielectric layer, a first contact hole, a second contact hole, a source, a drain, a third gate and a fourth gate dielectric layer. The first gate is located above the substrate. The first semiconductor layer is located above the first gate. The first gate dielectric layer is located between the first gate and the first semiconductor layer. The second gate is located above the first semiconductor layer. The second gate dielectric layer is located between the first semiconductor layer and the second gate. The second semiconductor layer is located above the second gate. The third gate dielectric layer is located between the second gate electrode and the second semiconductor layer. The first contact hole continuously penetrates the second gate dielectric layer and the third gate dielectric layer. The second contact hole continuously penetrates the second gate dielectric layer and the third gate dielectric layer. The source electrode is filled in the first contact hole and electrically connects the first semiconductor layer and the second semiconductor layer. The drain electrode is filled in the second contact hole and electrically connects the first semiconductor layer and the second semiconductor layer. The third gate electrode is located on the second semiconductor layer. The fourth gate dielectric layer is located between the second semiconductor layer and the third gate electrode.

The manufacturing method of the semiconductor device of the present invention includes the following steps. A first gate is formed on a substrate. A first gate dielectric layer is formed on the first gate. A first semiconductor layer is formed on the first gate dielectric layer. A second gate dielectric layer is formed on the first semiconductor layer. A second gate is formed on the second gate dielectric layer. A third gate dielectric layer is formed on the second gate. A first contact hole and a second contact hole are formed in the second gate dielectric layer and the third gate dielectric layer and expose a portion of the surface of the first semiconductor layer respectively. A source is formed on the third gate dielectric layer and filled into the first contact hole. A drain is formed on the third gate dielectric layer and filled into the second contact hole. A second semiconductor layer is formed on the third gate dielectric layer. A fourth gate dielectric layer is formed on the top surface of the source, the top surface of the drain and the top surface of the second semiconductor layer. A third gate is formed on the fourth gate dielectric layer.

Based on the above, the semiconductor device of the present invention electrically connects the source and drain to the first semiconductor layer and the second semiconductor layer through the first contact hole and the second contact hole with small apertures, so that the orthographic projection area of the source and the drain on the substrate can be reduced, thereby reducing the area of the semiconductor device. At the same time, the semiconductor device can disperse the current between the source and the drain through the first semiconductor layer and the second semiconductor layer, thereby improving the negative effects of current stress or hot carrier effect and increasing the driving voltage, so that when the semiconductor device is applied to the driving element of the panel, it can cooperate with the compact circuit design in the panel to achieve the requirements of a thin, short and high-resolution panel.

10,20,30,40,50:Semiconductor devices

100: Substrate

112: First gate dielectric layer

114: Second gate dielectric layer

116: Third gate dielectric layer

116t,140t,152t,154t: Top surface

118: Fourth gate dielectric layer

120: First gate

122: Second gate

124: The third gate

130: First semiconductor layer

130a,130b: mixed area

130c: Channel area

132: First level

134: Second level

140: Second semiconductor layer

152: Source

154: Drainage

160: Protective layer

170: Third semiconductor layer

A-A’, B-B’, C-C’, D-D’, E-E’: lines

CH1: First contact hole

CH2: Second contact hole

ND: Normal direction

P: Doping process

sw1,sw11,sw12,sw2,sw21,sw22: side wall

FIG1A is a schematic top view of a semiconductor device according to an embodiment of the present invention.

FIG1B is a schematic cross-sectional view along line A-A’ of FIG1A .

Figures 2A to 2G are cross-sectional schematic diagrams of a method for manufacturing the semiconductor device of Figures 1A to 1B.

FIG3A is a schematic top view of a semiconductor device according to an embodiment of the present invention.

Figure 3B is a schematic cross-sectional view along line B-B’ of Figure 3A.

FIG4A is a schematic top view of a semiconductor device according to an embodiment of the present invention.

FIG4B is a schematic cross-sectional view along line C-C’ of FIG4A .

Figures 5A and 5B are cross-sectional schematic diagrams of a method for manufacturing the semiconductor device of Figures 4A and 4B.

FIG6A is a schematic top view of a semiconductor device according to an embodiment of the present invention.

FIG6B is a schematic cross-sectional view along line D-D’ of FIG6A .

FIG7A is a schematic top view of a semiconductor device according to an embodiment of the present invention.

FIG7B is a schematic cross-sectional view along line E-E’ of FIG7A .

Figures 8A and 8B are cross-sectional schematic diagrams of a method for manufacturing the semiconductor device of Figures 7A and 7B.

In the accompanying drawings, the thickness of layers, films, panels, regions, etc., is exaggerated for clarity. Throughout the specification, the same figure reference numerals represent the same elements. It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to another element, or intermediate elements can also exist. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intermediate elements. As used herein, "connected" can refer to physical and/or electrical connections. Furthermore, "electrically connected" or "coupled" can mean the presence of other elements between two elements.

It should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, components, regions, layers and/or parts, these elements, components, regions, and/or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, the "first element", "component", "region", "layer" or "part" discussed below can be referred to as the second element, component, region, layer or part without departing from the teachings of this article.

FIG1A is a schematic top view of a semiconductor device according to an embodiment of the present invention. FIG1B is a schematic cross-sectional view along line A-A' of FIG1A. FIG1A shows a first gate 120, a second gate 122, a third gate 124, a first semiconductor layer 130, a second semiconductor layer 140, a source 152, a drain 154, a first contact hole CH1, and a second contact hole CH2, and other components are omitted. The omitted parts can be understood with reference to FIG1B.

1A and 1B , the semiconductor device 10 includes a substrate 100, a first gate 120, a second gate 122, a third gate 124, a first semiconductor layer 130, a second semiconductor layer 140, a first gate dielectric layer 112, a second gate dielectric layer 114, a third gate dielectric layer 116, a fourth gate dielectric layer 118, a source 152, a drain 154, a first contact hole CH1, and a second contact hole CH2.

The first gate 120 is disposed above the substrate 100. The first semiconductor layer 130 is located above the first gate 120, and the first gate dielectric layer 112 is located between the first gate 120 and the first semiconductor layer 130. The second gate 122 is located above the first semiconductor layer 130, and the second gate dielectric layer 114 is located between the first semiconductor layer 130 and the second gate 122. The second semiconductor layer 140 is located above the second gate 122, and the third gate dielectric layer 116 is located between the second gate 122 and the second semiconductor layer 140. The third gate 124 is located on the second semiconductor layer 140, and the fourth gate dielectric layer 118 is located between the second semiconductor layer 140 and the third gate 124. In some embodiments, the semiconductor device 10 further includes a protective layer 160, and the protective layer 160 covers the third gate 124.

In some embodiments, the material of the substrate 100 includes glass, quartz, organic polymer or opaque/reflective material (e.g., conductive material, metal, wafer, ceramic or other applicable material) or other applicable materials. If a conductive material or metal is used, an insulating layer (not shown) is covered on the substrate 100 to avoid short circuit problems. In some embodiments, one or more buffer layers (not shown) are also included between the first gate 120 and the substrate 100, but the present invention is not limited thereto.

In some embodiments, the materials of the first gate 120, the second gate 122, and the third gate 124 may include metals such as chromium, gold, silver, copper, tin, lead, uranium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, the above alloys, the above metal oxides, the above metal nitrides, or the above combinations or other conductive materials. For example, the first gate 120, the second gate 122, and the third gate 124 may each be a stacked layer of titanium metal, aluminum metal, and titanium metal. The materials of the first gate 120, the second gate 122, and the third gate 124 may be the same or different, and the present invention is not limited thereto.

In some embodiments, the materials of the first gate dielectric layer 112, the second gate dielectric layer 114, the third gate dielectric layer 116, the fourth gate dielectric layer 118 and the protective layer 160 include silicon nitride, silicon oxynitride, silicon oxide, tantalum oxide, combinations thereof or other suitable materials. In some embodiments, the materials of the first gate dielectric layer 112, the second gate dielectric layer 114, the third gate dielectric layer 116, the fourth gate dielectric layer 118 and the protective layer 160 may be the same or different, and the present invention is not limited thereto. In some embodiments, the first gate dielectric layer 112, the second gate dielectric layer 114, the third gate dielectric layer 116, the fourth gate dielectric layer 118 and the protective layer 160 can be single-layer or multi-layer structures respectively, but the present invention is not limited thereto.

In some embodiments, the material of the first semiconductor layer 130 may include amorphous silicon, polycrystalline silicon, microcrystalline silicon, single crystal silicon, organic semiconductor materials, metal oxide semiconductor materials (e.g., indium-gallium-zinc oxide (IGZO), indium-tin-zinc oxide (ITZO), aluminum-zinc-tin oxide (AZTO), indium-tungsten-zinc oxide (ZIWO), zinc oxide (ZnO), tin oxide (SnO), indium-zinc oxide (IZO), gallium-zinc oxide (GZO), etc.). Oxide, GZO), zinc-tin oxide (Zinc-Tin Oxide, ZTO), aluminum-zinc oxide (Aluminum-Zinc Oxide, AZO) or indium-tin oxide (Indium-Tin Oxide, ITO) or other suitable materials) or other suitable materials or a combination of the above materials.

In the present embodiment, the first semiconductor layer 130 is a double-layer structure. For example, the first semiconductor layer 130 may include a first layer 132 and a second layer 134 stacked on each other. The first layer 132 is located on the first gate dielectric layer 112, and the second layer 134 is located on the first layer 132. In other words, the first layer 132 is between the second layer 134 and the first gate dielectric layer 112. The band gap of the first layer 132 is different from the band gap of the second layer 134, so a two-dimensional electron gas (2DEG) can be formed at the interface between the first layer 132 and the second layer 134 to improve the electron mobility of the first semiconductor layer 130. However, the present invention is not limited thereto, and in other embodiments, the first semiconductor layer 130 may be a single-layer structure, or the first semiconductor layer 130 may be a multi-layer structure.

The energy gap difference between the first layer 132 and the second layer 134 can be achieved by making the materials or compositions of the first layer 132 and the second layer 134 different. In some embodiments, the materials of the first layer 132 and the second layer 134 may include metal oxide semiconductor materials, and the oxygen content of the first layer 132 is different from the oxygen content of the second layer 134, so that the energy gap of the first layer 132 is different from the energy gap of the second layer 134. In some embodiments, the oxygen content of the first layer 132 is less than the oxygen content of the second layer 134. For example, the oxygen content of the first layer 132 may be between 0 atomic % and 25 atomic %, and the oxygen content of the second layer 134 may be between 25 atomic % and 50 atomic %. In this way, the band gap of the first layer 132 is smaller than the band gap of the second layer 134, so that a two-dimensional electron gas is formed at the interface between the first layer 132 and the second layer 134, thereby improving the electron mobility and increasing the output current of the semiconductor device 10. However, the present invention is not limited to this. In other embodiments, the oxygen content of the first layer 132 can be greater than the oxygen content of the second layer 134. In addition, the oxygen content of the first layer 132 and the oxygen content of the second layer 134 can be adjusted according to actual needs, and the present invention is not limited to this.

In some embodiments, the material of the second semiconductor layer 140 may include amorphous silicon, polycrystalline silicon, microcrystalline silicon, single crystal silicon, organic semiconductor material, metal oxide semiconductor material (e.g., indium gallium zinc oxide, indium tin zinc oxide, aluminum zinc tin oxide, indium tungsten zinc oxide, zinc oxide, tin oxide, indium zinc oxide, gallium zinc oxide, zinc tin oxide, aluminum zinc oxide, or indium tin oxide or other suitable materials) or other suitable materials or combinations thereof. In some embodiments, the material of the second semiconductor layer 140 may be the same as or different from the material of the first semiconductor layer 130. Although FIG. 1B shows that the second semiconductor layer 140 is a single-layer structure, it is not intended to limit the present invention. The second semiconductor layer 140 can be a double-layer or multi-layer structure according to actual needs.

In some embodiments, the orthographic projection area of the second semiconductor layer 140 on the substrate 100 is smaller than the orthographic projection area of the first semiconductor layer 130 on the substrate 100.

The first contact hole CH1 continuously penetrates the second gate dielectric layer 114 and the third gate dielectric layer 116. The second contact hole CH2 continuously penetrates the second gate dielectric layer 114 and the third gate dielectric layer 116. The source 152 is filled in the first contact hole CH1 and electrically connects the first semiconductor layer 130 and the second semiconductor layer 140. The drain 154 is filled in the second contact hole CH2 and electrically connects the first semiconductor layer 130 and the second semiconductor layer 140. The fourth gate dielectric layer 118 covers the top surface 152t of the source 152 and the top surface 154t of the drain 154. In this article, “continuously penetrate” means that the contact hole is formed by penetrating one or more gate dielectric layers in one etching process, that is, the first contact hole CH1 penetrates the second gate dielectric layer 114 and the third gate dielectric layer 116 in one etching process, and the second contact hole CH2 penetrates the second gate dielectric layer 114 and the third gate dielectric layer 116 in one etching process. Therefore, in the first contact hole CH1, the side wall sw1 of the first contact hole CH1 is composed of the side wall sw11 of the second gate dielectric layer 114 and the side wall sw12 of the third gate dielectric layer 116, wherein the side wall sw11 of the second gate dielectric layer 114 and the side wall sw12 of the third gate dielectric layer 116 are substantially aligned; in the second contact hole CH2, the side wall sw2 of the second contact hole CH2 is composed of the side wall sw21 of the second gate dielectric layer 114 and the side wall sw22 of the third gate dielectric layer 116, wherein the side wall sw21 of the second gate dielectric layer 114 and the side wall sw22 of the third gate dielectric layer 116 are substantially aligned.

In some embodiments, the fourth gate dielectric layer 118 covers the first contact hole CH1 and the second contact hole CH2 in the normal direction ND of the substrate 100. That is, the source 152 and the drain 154 are buried in the second gate dielectric layer 114, the third gate dielectric layer 116 and the fourth gate dielectric layer 118.

Since the first contact hole CH1 and the second contact hole CH2 penetrate the second gate dielectric layer 114 and the third gate dielectric layer 116 without penetrating the fourth gate dielectric layer 118 and the protective layer 160, the first contact hole CH1 and the second contact hole CH2 may have a smaller aperture, thereby reducing the orthographic projection area of the source 152 and the drain 154 on the substrate 100. In some embodiments, the aperture of the first contact hole CH1 and the second contact hole CH2 may be between about 2μm and 5μm.

In some embodiments, the orthographic projections of the first contact hole CH1 and the second contact hole CH2 on the substrate 100 are respectively located on opposite sides of the orthographic projections of the first gate 120, the second gate 122 or the third gate 124 on the substrate 100.

In some embodiments, the first semiconductor layer 130 has doped regions 130a, 130b and a channel region 130c. The channel region 130c is located between the doped region 130a and the doped region 130b. The resistivity of the doped region 130a and the doped region 130b is less than the resistivity of the channel region 130c. In some embodiments, the channel region 130c substantially overlaps with the second gate 122 in the normal direction ND of the substrate 100, while the doped region 130a and the doped region 130b substantially do not overlap with the second gate 122 in the normal direction ND of the substrate 100. In some embodiments, the first contact hole CH1 and the second contact hole CH2 overlap the doped region 130a and the doped region 130b respectively in the normal direction ND of the substrate 100.

In this embodiment, the second semiconductor layer 140 extends into the first contact hole CH1 and the second contact hole CH2 and directly contacts the first semiconductor layer 130. Specifically, the second semiconductor layer 140 extends along the top surface 116t of the third gate dielectric layer 116 to the sidewall sw1 of the first contact hole CH1 and the sidewall sw2 of the second contact hole CH2 and contacts the doped regions 130a and 130b of the first semiconductor layer 130, thereby connecting to the first semiconductor layer 130. In this way, the loss of the first semiconductor layer 130 that may be caused when forming the first contact hole CH1 and the second contact hole CH2 can be compensated, thereby improving the contact resistance.

In some embodiments, the first contact hole CH1 and the second contact hole CH2 overlap with the first semiconductor layer 130 and the second semiconductor layer 140 in the normal direction ND of the substrate 100.

In some embodiments, the source 152 and the drain 154 are respectively located on opposite sides of the second semiconductor layer 140. The source 152 directly contacts the top surface 140t of the second semiconductor layer 140, and the drain 154 directly contacts the top surface 140t of the second semiconductor layer 140. That is, part of the second semiconductor layer 140 is sandwiched between the first semiconductor layer 130 and the source 152 and between the first semiconductor layer 130 and the drain 154.

In some embodiments, an ohmic contact layer (not shown) may be provided between the source 152 and the second semiconductor layer 140 and between the drain 154 and the second semiconductor layer 140 to enhance the electrical connection between the source 152, the drain 154 and the second semiconductor layer 140. For example, the ohmic contact layer may include a doped silicon-containing semiconductor material or a metal oxide semiconductor material so that the resistivity of the ohmic contact layer is less than the resistivity of the second semiconductor layer 140.

In some embodiments, the first gate 120, the second gate 122, and the third gate 124 overlap each other in the normal direction ND of the substrate 100. The first gate 120, the second gate 122, and the third gate 124 can be electrically connected or electrically separated according to the actual circuit design, and the present invention is not limited thereto. For example, in some embodiments, the second gate 122 can be used as a main control gate, and the first gate 120 and the third gate 124 are floating. In some other embodiments, the first gate 120, the second gate 122, and the third gate 124 can be electrically connected to each other through a conductive hole (not shown).

Since the first contact hole CH1 and the second contact hole CH2 have small apertures, and the source 152 and the drain 154 are electrically connected to the first semiconductor layer 130 and the second semiconductor layer 140 through the first contact hole CH1 and the second contact hole CH2, the orthographic projection area of the source 152 and the drain 154 on the substrate 100 can be reduced, thereby reducing the semiconductor The area of the semiconductor device 10 can be reduced, and at the same time, the semiconductor device 10 can disperse the current between the source 152 and the drain 154 through the first semiconductor layer 130 and the second semiconductor layer 140, thereby improving the negative effects of current stress or hot carrier effect and increasing the driving voltage, so that the semiconductor device 10 still has good performance under the condition of reduced area.

FIG. 2A to FIG. 2G are cross-sectional schematic diagrams of the manufacturing method of the semiconductor device of FIG. 1A to FIG. 1B. It must be explained here that the embodiment of FIG. 2A to FIG. 2G uses the component numbers and part of the content of the embodiment of FIG. 1A to FIG. 1B, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical content is omitted. The description of the omitted part can be referred to the aforementioned embodiment, which will not be repeated here.

Referring to FIG. 2A , a first gate 120 is formed on a substrate 100. For example, a first gate material layer (not shown) may be deposited on the substrate 100, and then the first gate material layer may be patterned to form the first gate 120. In some embodiments, the first gate material layer may be formed by, for example, electroplating, electroless plating, physical vapor deposition, or chemical vapor deposition, but the present invention is not limited thereto. In some embodiments, the method of patterning the first gate material layer may include, for example, lithography and etching, but the present invention is not limited thereto.

Referring to FIG. 2B , a first gate dielectric layer 112 is formed on the first gate 120. In some embodiments, the first gate dielectric layer 112 is conformally deposited on the first gate 120 and the substrate 100. In some embodiments, the first gate dielectric layer 112 may be formed by a method such as physical vapor deposition or chemical vapor deposition, but the present invention is not limited thereto.

Then, a first semiconductor layer 130 is formed on the first gate dielectric layer 112. For example, a first layer of a first semiconductor material layer and a second layer of a first semiconductor material layer are sequentially deposited on the first gate dielectric layer 112 by, for example, physical vapor deposition or chemical vapor deposition. Then, the first semiconductor material layer is patterned by lithography and etching to form the first semiconductor layer 130 including the first layer 132 and the second layer 134. In an embodiment where the first semiconductor layer 130 is a metal oxide semiconductor, the oxygen content of the first layer 132 is different from the oxygen content of the second layer 134. Although FIG. 2C shows that the first semiconductor layer 130 has a double-layer structure, it is not intended to limit the present invention. The number of layers of the first semiconductor layer 130 can be adjusted according to actual needs.

Please refer to FIG. 2C , a second gate dielectric layer 114 is formed on the first semiconductor layer 130. The second gate dielectric layer 114 may be formed by, for example, physical vapor deposition or chemical vapor deposition, but the present invention is not limited thereto.

Then, a second gate 122 is formed on the second gate dielectric layer 114. For example, a second gate material layer (not shown) may be first deposited on the second gate dielectric layer 114, and then the second gate material layer may be patterned to form the second gate 122. In some embodiments, the second gate material layer may be formed by, for example, electroplating, electroless plating, physical vapor deposition, or chemical vapor deposition, but the present invention is not limited thereto. In some embodiments, the method of patterning the second gate material layer may include, for example, lithography and etching, but the present invention is not limited thereto.

Referring to FIG. 2D , the first semiconductor layer 130 is subjected to a doping process P using the second gate 122 as a mask to form a doping region 130a, a doping region 130b, and a channel region 130c. The doping region 130a and the doping region 130b are respectively formed in the first semiconductor layer 130 on both sides of the second gate 122. The channel region 130c is aligned with the second gate 122 and is substantially undoped. In some embodiments, the doping process P includes a hydrogen plasma process, an ion implantation process, or other suitable processes.

Please refer to FIG. 2E , a third gate dielectric layer 116 is formed on the second gate 122 and the second gate dielectric layer 114. The third gate dielectric layer 116 may be formed by, for example, physical vapor deposition or chemical vapor deposition, but the present invention is not limited thereto.

Then, a first contact hole CH1 and a second contact hole CH2 are formed in the second gate dielectric layer 114 and the third gate dielectric layer 116 to expose a portion of the surface of the first semiconductor layer 130. In some embodiments, the first contact hole CH1 and the second contact hole CH2 expose the doped region 130a and the doped region 130b of the first semiconductor layer 130, respectively. In some embodiments, the method for forming the first contact hole CH1 and the second contact hole CH2 includes: forming a patterned photoresist layer (not shown) on the third gate dielectric layer 116, and then performing an etching process on the third gate dielectric layer 116 and the second gate dielectric layer 114 using the patterned photoresist layer as a mask to remove a portion of the second gate dielectric layer 114 and a portion of the third gate dielectric layer 116, wherein the first semiconductor layer 130 can be used as an etching stop layer of the etching process. In some embodiments, the etching process can be, for example, a wet etching process or a dry etching process, but the present invention is not limited thereto.

Since only the second gate dielectric layer 114 and the third gate dielectric layer 116 need to be removed during the etching process to form the first contact hole CH1 and the second contact hole CH2, the first contact hole CH1 and the second contact hole CH2 can have a small aperture, for example, between about 2μm and 5μm, thereby reducing the possible loss of the first semiconductor layer 130 during the etching process.

Referring to FIG. 2F , the second semiconductor layer 140 is formed on the third gate dielectric layer 116, and the second semiconductor layer 140 is also formed on the sidewall sw1 of the first contact hole CH1, the sidewall sw2 of the second contact hole CH2, and the surface of the first semiconductor layer 130 exposed by the first contact hole CH1 and the second contact hole CH2. For example, a second semiconductor material layer (not shown) may be first deposited on the third gate dielectric layer 116 and in the first contact hole CH1 and the second contact hole CH2 by, for example, physical vapor deposition or chemical vapor deposition, and then the second semiconductor material layer may be patterned by photolithography and etching to form the second semiconductor layer 140. The second semiconductor layer 140 is formed on the first semiconductor layer 130 through the first contact hole CH1 and the second contact hole CH2 and directly contacts the first semiconductor layer 130, which can compensate for the loss of the first semiconductor layer 130 that may be caused during the etching process of forming the first contact hole CH1 and the second contact hole CH2, thereby improving the contact resistance.

2G , a source electrode 152 is formed on the third gate dielectric layer 116 and filled into the first contact hole CH1, and a drain electrode 154 is formed on the third gate dielectric layer 116 and filled into the second contact hole CH2. For example, a conductive material layer (not shown) may be first deposited on the second semiconductor layer 140 and the third gate dielectric layer 116, and then the conductive material layer may be patterned to form the source electrode 152 and the drain electrode 154. In some embodiments, the conductive material layer may be formed by, for example, electroplating, electroless plating, physical vapor deposition, or chemical vapor deposition, but the present invention is not limited thereto. In some embodiments, the method of patterning the conductive material layer may include, for example, lithography and etching, but the present invention is not limited thereto.

In some embodiments, an ohmic contact layer (not shown) may be formed on the second semiconductor layer 140 before forming the source 152 and the drain 154. For example, the ohmic contact material layer may be deposited before depositing the aforementioned conductive material layer, and then the ohmic contact material layer may be patterned to form an ohmic contact layer between the source 152 and the second semiconductor layer 140 and between the drain 154 and the second semiconductor layer 140.

Please return to FIG. 1B to form a fourth gate dielectric layer 118 on the top surface 152t of the source 152, the top surface 154t of the drain 154, and the top surface 140t of the second semiconductor layer 140. The fourth gate dielectric layer 118 may be formed by, for example, physical vapor deposition or chemical vapor deposition, but the present invention is not limited thereto.

Then, a third gate 124 is formed on the fourth gate dielectric layer 118. For example, a third gate material layer (not shown) may be first deposited on the fourth gate dielectric layer 118, and then the third gate material layer may be patterned to form the third gate 124. In some embodiments, the third gate material layer may be formed by, for example, electroplating, electroless plating, physical vapor deposition, or chemical vapor deposition, but the present invention is not limited thereto. In some embodiments, the method of patterning the third gate material layer may include, for example, lithography and etching, but the present invention is not limited thereto.

Afterwards, a protective layer 160 is formed on the third gate 124 and the fourth gate dielectric layer 118. The protective layer 160 may be formed by, for example, physical vapor deposition or chemical vapor deposition, but the present invention is not limited thereto.

After the above process, the production of the semiconductor device 10 can be roughly completed.

FIG. 3A is a schematic top view of a semiconductor device according to an embodiment of the present invention. FIG. 3B is a schematic cross-sectional view along line B-B' of FIG. 3A. It should be noted that the embodiment of FIG. 3A and FIG. 3B uses the component numbers and part of the content of the embodiment of FIG. 1A and FIG. 1B, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical content is omitted. The description of the omitted part can refer to the aforementioned embodiment, and will not be repeated here. In FIG. 3A, the first gate 120, the second gate 122, the third gate 124, the first semiconductor layer 130, the second semiconductor layer 140, the third semiconductor layer 170, the source 152, the drain 154, the first contact hole CH1 and the second contact hole CH2 are shown, and other components are omitted. The omitted parts can be understood by referring to FIG. 3B.

Please refer to FIG. 3A and FIG. 3B . The semiconductor device 20 of this embodiment is different from the embodiment of FIG. 1A to FIG. 1B in that the semiconductor device 20 further includes a third semiconductor layer 170, the third semiconductor layer 170 is stacked on the second semiconductor layer 140, and the fourth gate dielectric layer 118 covers a portion of the top surface 152t of the source 152, a portion of the top surface 154t of the drain 154, and the third semiconductor layer 170.

In some embodiments, the third semiconductor layer 170 extends from the top surface 140t of the second semiconductor layer 140 to the top surface 152t of the source 152 and the top surface 154t of the drain 154, and part of the source 152 and part of the drain 154 are located between the third semiconductor layer 170 and the second semiconductor layer 140. In this way, the possible loss of the second semiconductor layer 140 during the etching process of the source 152 and the drain 154 can be compensated, thereby improving the contact resistance.

In some embodiments, the material of the third semiconductor layer 170 may include amorphous silicon, polycrystalline silicon, microcrystalline silicon, single crystal silicon, organic semiconductor material, metal oxide semiconductor material (e.g., indium gallium zinc oxide, indium tin zinc oxide, aluminum zinc tin oxide, indium tungsten zinc oxide, zinc oxide, tin oxide, indium zinc oxide, gallium zinc oxide, zinc tin oxide, aluminum zinc oxide, or indium tin oxide or other suitable materials) or other suitable materials or combinations thereof. In some embodiments, the material of the third semiconductor layer 170 may be the same as or different from the material of the first semiconductor layer 130 and/or the second semiconductor layer 140. Although FIG. 3B shows that the third semiconductor layer 170 is a single-layer structure, it is not intended to limit the present invention. The third semiconductor layer 170 can be a double-layer or multi-layer structure according to actual needs.

In some embodiments, the energy gap of the third semiconductor layer 170 is different from the energy gap of the second semiconductor layer 140, so a two-dimensional electron gas (2DEG) can be formed at the interface between the third semiconductor layer 170 and the second semiconductor layer 140 to improve electron mobility.

The energy gap difference between the third semiconductor layer 170 and the second semiconductor layer 140 can be achieved by making the materials or compositions of the third semiconductor layer 170 different from those of the second semiconductor layer 140. In some embodiments, the materials of the third semiconductor layer 170 and the second semiconductor layer 140 may include a metal oxide semiconductor material, and the oxygen content of the third semiconductor layer 170 is different from that of the second semiconductor layer 140, so that the energy gap of the third semiconductor layer 170 is different from that of the second semiconductor layer 140. In some embodiments, the oxygen content of the third semiconductor layer 170 is less than that of the second semiconductor layer 140. For example, the oxygen content of the third semiconductor layer 170 may be between 0 atomic % and 25 atomic %, and the oxygen content of the second semiconductor layer 140 may be between 25 atomic % and 50 atomic %. However, the present invention is not limited thereto, and in other embodiments, the oxygen content of the third semiconductor layer 170 may be greater than the oxygen content of the second semiconductor layer 140. In addition, the oxygen content of the third semiconductor layer 170 and the oxygen content of the second semiconductor layer 140 may be adjusted according to actual needs, and the present invention is not limited thereto.

In some embodiments, the orthographic projection area of the third semiconductor layer 170 on the substrate 100 is smaller than the orthographic projection area of the second semiconductor layer 140 on the substrate 100.

The manufacturing method of the semiconductor device 20 is similar to the manufacturing method of the semiconductor device 10, except that after the source 152 and the drain 154 are formed and before the fourth gate dielectric layer 118 is formed, a third semiconductor layer 170 is formed on the second semiconductor layer 140, wherein the third semiconductor layer 170 extends from the top surface 140t of the second semiconductor layer 140 to the top surface 152t of the source 152 and the top surface 154t of the drain 154, and a portion of the source 152 and a portion of the drain 154 are located between the third semiconductor layer 170 and the second semiconductor layer 140. The method for forming the third semiconductor layer 170 may include first depositing a third semiconductor material layer (not shown) on the second semiconductor layer 140 and the source 152 and the drain 154 by, for example, physical vapor deposition or chemical vapor deposition, and then patterning the third semiconductor material layer by lithography and etching to form the third semiconductor layer 170.

In some embodiments, the manufacturing method of the semiconductor device 20 may further include, after the third gate 124 is formed, performing a doping process (such as a hydrogen plasma process, an ion implantation process or other suitable process) on the third semiconductor layer 170 using the third gate 124 as a mask to form a doped region (not shown) in the third semiconductor layer 170 not covered by the third gate 124, and the third semiconductor layer 170 aligned with the third gate 124 is a channel region (not shown).

Since the third semiconductor layer 170 is formed on the second semiconductor layer 140 after the source 152 and the drain 154 are formed, it can compensate for the possible loss of the second semiconductor layer 140 during the etching process of forming the source 152 and the drain 154, thereby improving the contact resistance.

FIG. 4A is a schematic top view of a semiconductor device according to an embodiment of the present invention. FIG. 4B is a schematic cross-sectional view along line C-C' of FIG. 4A. It should be noted that the embodiment of FIG. 4A and FIG. 4B uses the component numbers and part of the content of the embodiment of FIG. 1A and FIG. 1B, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical content is omitted. The description of the omitted part can refer to the aforementioned embodiment, and will not be repeated here. In FIG. 4A, the first gate 120, the second gate 122, the third gate 124, the first semiconductor layer 130, the second semiconductor layer 140, the source 152, the drain 154, the first contact hole CH1 and the second contact hole CH2 are shown, and other components are omitted. The omitted parts can be understood by referring to FIG. 4B.

4A and 4B , the semiconductor device 30 of this embodiment is different from the embodiment of FIGS. 1A to 1B in that the source 152 of the semiconductor device 30 directly contacts the first semiconductor layer 130 through the first contact hole CH1, and the drain 154 directly contacts the first semiconductor layer 130 through the second contact hole CH2. In other words, the second semiconductor layer 140 of the semiconductor device 30 does not extend into the first contact hole CH1 and the second contact hole CH2 to directly contact the first semiconductor layer 130. The opposite sides of the second semiconductor layer 140 are respectively located between the source 152 and the third gate dielectric layer 116 and between the drain 154 and the third gate dielectric layer 116.

In some embodiments, the source 152 is in direct contact with the doped region 130a of the first semiconductor layer 130, and the drain 154 is in direct contact with the doped region 130b of the first semiconductor layer 130. In some embodiments, the source 152 and the drain 154 are in direct contact with the top surface 140t of the second semiconductor layer 140.

In some embodiments, the first contact hole CH1 and the second contact hole CH2 overlap with the first semiconductor layer 130 in the normal direction ND of the substrate 100, but do not overlap with the second semiconductor layer 140.

Since the first contact hole CH1 and the second contact hole CH2 have small apertures, and the source electrode 152 and the drain electrode 154 electrically connect the first semiconductor layer 130 and the second semiconductor layer 140 through the first contact hole CH1 and the second contact hole CH2, the orthographic projection area of the source electrode 152 and the drain electrode 154 on the substrate 100 can be reduced, thereby reducing the semiconductor The area of the device 30 is reduced, and at the same time, the semiconductor device 30 can disperse the current between the source 152 and the drain 154 through the first semiconductor layer 130 and the second semiconductor layer 140, thereby improving the negative effects of current stress or hot carrier effect and increasing the driving voltage, so that the semiconductor device 30 still has good performance under the condition of reduced area.

FIG. 5A to FIG. 5B are cross-sectional schematic diagrams of the manufacturing method of the semiconductor device of FIG. 4A to FIG. 4B. It must be explained here that the embodiment of FIG. 5A to FIG. 5B uses the component numbers and part of the content of the embodiment of FIG. 4A to FIG. 4B, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical content is omitted. The description of the omitted part can refer to the aforementioned embodiment, which will not be repeated here. FIG. 5A can be a process continuing FIG. 2A to FIG. 2E, and the relevant process description can refer to the aforementioned.

5A , following the step of FIG. 2E , a second semiconductor layer 140 is formed on the third gate dielectric layer 116. For example, a second semiconductor material layer (not shown) may be deposited on the third gate dielectric layer 116 by physical vapor deposition or chemical vapor deposition, and then the second semiconductor material layer may be patterned by photolithography and etching to form the second semiconductor layer 140. Alternatively, a patterned photoresist layer (not shown) may be formed to cover the first contact hole CH1 and the second contact hole CH2 and expose the location where the second semiconductor layer 140 is to be formed, and then a second semiconductor material layer (not shown) is formed on the third gate dielectric layer 116, and then the patterned photoresist layer is stripped off to form the second semiconductor layer 140 on the third gate dielectric layer 116.

Referring to FIG. 5B , a source electrode 152 is formed on the third gate dielectric layer 116 and the second semiconductor layer 140 and filled into the first contact hole CH1 to directly contact the first semiconductor layer 130. A drain electrode 154 is formed on the third gate dielectric layer 116 and the second semiconductor layer 140 and filled into the second contact hole CH2 to directly contact the first semiconductor layer 130. For example, a conductive material layer (not shown) may be first deposited on the second semiconductor layer 140 and the third gate dielectric layer 116, and then the conductive material layer may be patterned to form the source electrode 152 and the drain electrode 154. In some embodiments, the method for forming the conductive material layer may be, for example, electroplating, electroless plating, physical vapor deposition, or chemical vapor deposition, but the present invention is not limited thereto. In some embodiments, the method for patterning the conductive material layer may include, for example, lithography and etching, but the present invention is not limited thereto.

Please go back to Figure 4B, and then follow the steps similar to forming the fourth gate dielectric layer 118, the third gate 124 and the protective layer 160 of the semiconductor device 10, and the manufacturing of the semiconductor device 20 can be basically completed.

FIG. 6A is a schematic top view of a semiconductor device according to an embodiment of the present invention. FIG. 6B is a schematic cross-sectional view along line D-D' of FIG. 6A. It should be noted that the embodiment of FIG. 6A and FIG. 6B uses the component numbers and part of the content of the embodiment of FIG. 4A and FIG. 4B, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical content is omitted. The description of the omitted part can refer to the aforementioned embodiment, and will not be repeated here. In FIG. 6A, the first gate 120, the second gate 122, the third gate 124, the first semiconductor layer 130, the second semiconductor layer 140, the third semiconductor layer 170, the source 152, the drain 154, the first contact hole CH1 and the second contact hole CH2 are shown, and other components are omitted. The omitted parts can be understood by referring to FIG. 6B.

Please refer to FIG. 6A and FIG. 6B . The semiconductor device 40 of this embodiment is different from the embodiment of FIG. 4A to FIG. 4B in that the semiconductor device 40 further includes a third semiconductor layer 170, the third semiconductor layer 170 is stacked on the second semiconductor layer 140, and the fourth gate dielectric layer 118 covers a portion of the top surface 152t of the source 152, a portion of the top surface 154t of the drain 154, and the third semiconductor layer 170.

In some embodiments, the third semiconductor layer 170 extends from the top surface 140t of the second semiconductor layer 140 to the top surface 152t of the source 152 and the top surface 154t of the drain 154, and part of the source 152 and part of the drain 154 are located between the third semiconductor layer 170 and the second semiconductor layer 140. In this way, the possible loss of the second semiconductor layer 140 during the etching process of the source 152 and the drain 154 can be compensated, thereby improving the contact resistance.

In some embodiments, the material of the third semiconductor layer 170 may include amorphous silicon, polycrystalline silicon, microcrystalline silicon, single crystal silicon, organic semiconductor material, metal oxide semiconductor material (e.g., indium gallium zinc oxide, indium tin zinc oxide, aluminum zinc tin oxide, indium tungsten zinc oxide, zinc oxide, tin oxide, indium zinc oxide, gallium zinc oxide, zinc tin oxide, aluminum zinc oxide, or indium tin oxide or other suitable materials) or other suitable materials or combinations thereof. In some embodiments, the material of the third semiconductor layer 170 may be the same as or different from the material of the first semiconductor layer 130 and/or the second semiconductor layer 140. Although FIG. 6B shows that the third semiconductor layer 170 is a single-layer structure, it is not intended to limit the present invention. The third semiconductor layer 170 can be a double-layer or multi-layer structure according to actual needs.

In some embodiments, the energy gap of the third semiconductor layer 170 is different from the energy gap of the second semiconductor layer 140, so a two-dimensional electron gas (2DEG) can be formed at the interface between the third semiconductor layer 170 and the second semiconductor layer 140 to improve electron mobility.

The energy gap difference between the third semiconductor layer 170 and the second semiconductor layer 140 can be achieved by making the materials or compositions of the third semiconductor layer 170 different from those of the second semiconductor layer 140. In some embodiments, the materials of the third semiconductor layer 170 and the second semiconductor layer 140 may include a metal oxide semiconductor material, and the oxygen content of the third semiconductor layer 170 is different from that of the second semiconductor layer 140, so that the energy gap of the third semiconductor layer 170 is different from that of the second semiconductor layer 140. In some embodiments, the oxygen content of the third semiconductor layer 170 is less than that of the second semiconductor layer 140. For example, the oxygen content of the third semiconductor layer 170 may be between 0 atomic % and 25 atomic %, and the oxygen content of the second semiconductor layer 140 may be between 25 atomic % and 50 atomic %. However, the present invention is not limited thereto, and in other embodiments, the oxygen content of the third semiconductor layer 170 may be greater than the oxygen content of the second semiconductor layer 140. In addition, the oxygen content of the third semiconductor layer 170 and the oxygen content of the second semiconductor layer 140 may be adjusted according to actual needs, and the present invention is not limited thereto.

In some embodiments, the orthographic projection area of the third semiconductor layer 170 on the substrate 100 is smaller than the orthographic projection area of the second semiconductor layer 140 on the substrate 100.

The manufacturing method of the semiconductor device 40 is similar to the manufacturing method of the semiconductor device 30, except that after the source 152 and the drain 154 are formed and before the fourth gate dielectric layer 118 is formed, the third semiconductor layer 170 is formed on the second semiconductor layer 140, wherein the third semiconductor layer 170 extends from the top surface 140t of the second semiconductor layer 140 to the top surface 152t of the source 152 and the top surface 154t of the drain 154, and a portion of the source 152 and a portion of the drain 154 are located between the third semiconductor layer 170 and the second semiconductor layer 140. The method for forming the third semiconductor layer 170 may include first depositing a third semiconductor material layer (not shown) on the second semiconductor layer 140 and the source 152 and the drain 154 by, for example, physical vapor deposition or chemical vapor deposition, and then patterning the third semiconductor material layer by lithography and etching to form the third semiconductor layer 170.

Since the third semiconductor layer 170 is formed on the second semiconductor layer 140 after the source 152 and the drain 154 are formed, it can compensate for the possible loss of the second semiconductor layer 140 during the etching process of forming the source 152 and the drain 154, thereby improving the contact resistance.

FIG. 7A is a schematic top view of a semiconductor device according to an embodiment of the present invention. FIG. 7B is a schematic cross-sectional view along line E-E' of FIG. 7A. It should be noted that the embodiment of FIG. 7A and FIG. 7B uses the component numbers and part of the content of the embodiment of FIG. 1A and FIG. 1B, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical content is omitted. The description of the omitted part can refer to the aforementioned embodiment, and will not be repeated here. In FIG. 7A, the first gate 120, the second gate 122, the third gate 124, the first semiconductor layer 130, the second semiconductor layer 140, the source 152, the drain 154, the first contact hole CH1 and the second contact hole CH2 are shown, and other components are omitted. The omitted parts can be understood by referring to FIG. 7B.

7A and 7B , the semiconductor device 50 of this embodiment is different from the embodiment of FIGS. 1A to 1B in that the source 152 of the semiconductor device 50 is in direct contact with the first semiconductor layer 130 through the first contact hole CH1, the drain 154 is in direct contact with the first semiconductor layer 130 through the second contact hole CH2, and the second semiconductor layer 140 extends from the top surface 116t of the third gate dielectric layer 116 to the top surface 152t of the source 152 and the top surface 154t of the drain 154, and a portion of the source 152 and a portion of the drain 154 are located between the third gate dielectric layer 116 and the second semiconductor layer 140. That is, the second semiconductor layer 140 of the semiconductor device 50 does not extend into the first contact hole CH1 and the second contact hole CH2.

In some embodiments, opposite sides of the second semiconductor layer 140 are respectively between the fourth gate dielectric layer 118 and the source 152 and between the fourth gate dielectric layer 118 and the drain 154.

Since the first contact hole CH1 and the second contact hole CH2 have small apertures, and the source electrode 152 and the drain electrode 154 electrically connect the first semiconductor layer 130 and the second semiconductor layer 140 through the first contact hole CH1 and the second contact hole CH2, the orthographic projection area of the source electrode 152 and the drain electrode 154 on the substrate 100 can be reduced, thereby reducing the semiconductor The area of the semiconductor device 50 can be reduced, and at the same time, the semiconductor device 50 can disperse the current between the source 152 and the drain 154 through the first semiconductor layer 130 and the second semiconductor layer 140, thereby improving the negative effects of current stress or hot carrier effect and increasing the driving voltage, so that the semiconductor device 50 still has good performance under the condition of reduced area.

FIG8A to FIG8B are cross-sectional schematic diagrams of the manufacturing method of the semiconductor device of FIG7A to FIG7B. It must be noted that the embodiment of FIG8A to FIG8B uses the component numbers and part of the content of the embodiment of FIG7A to FIG7B, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical content is omitted. The description of the omitted part can refer to the aforementioned embodiment, which will not be repeated here. FIG7A can be a process continuing FIG2A to FIG2E, and the relevant process description can refer to the aforementioned.

8A , following the step of FIG. 2E , a source electrode 152 is formed on the third gate dielectric layer 116 and filled into the first contact hole CH1 to directly contact the first semiconductor layer 130, and a drain electrode 154 is formed on the third gate dielectric layer 116 and filled into the second contact hole CH2 to directly contact the first semiconductor layer 130. For example, a conductive material layer (not shown) may be first deposited on the third gate dielectric layer 116, and then the conductive material layer may be patterned to form the source electrode 152 and the drain electrode 154. In some embodiments, the method for forming the conductive material layer may be, for example, electroplating, electroless plating, physical vapor deposition, or chemical vapor deposition, but the present invention is not limited thereto. In some embodiments, the method for patterning the conductive material layer may include, for example, lithography and etching, but the present invention is not limited thereto.

Referring to FIG. 8B , the second semiconductor layer 140 is formed on the third gate dielectric layer 116, a portion of the source 152, and a portion of the drain 154. For example, a second semiconductor material layer (not shown) can be deposited on the third gate dielectric layer 116, the source 152, and the drain 154 by, for example, physical vapor deposition or chemical vapor deposition, and then the second semiconductor material layer is patterned by lithography and etching to form the second semiconductor layer 140.

Please return to FIG. 7B , and then the steps similar to those of the semiconductor device 10 to form the fourth gate dielectric layer 118 , the third gate 124 , and the protective layer 160 may be continued.

In some embodiments, the manufacturing method of the semiconductor device 50 may further include, after the third gate 124 is formed, performing a doping process (such as a hydrogen plasma process, an ion implantation process or other suitable process) on the second semiconductor layer 140 using the third gate 124 as a mask to form a doping region (not shown) in the second semiconductor layer 140 not covered by the third gate 124, and the second semiconductor layer 140 aligned with the third gate 124 is a channel region (not shown).

After the above process, the production of the semiconductor device 50 can be roughly completed.

In summary, the semiconductor device of the present invention electrically connects the source and drain to the first semiconductor layer and the second semiconductor layer through the first contact hole and the second contact hole with small apertures, so that the orthographic projection area of the source and the drain on the substrate can be reduced, thereby reducing the area of the semiconductor device. At the same time, the semiconductor device can disperse the current between the source and the drain through the first semiconductor layer and the second semiconductor layer, thereby improving the negative effects of current stress or hot carrier effect and increasing the driving voltage, so that when the semiconductor device is applied to the driving element of the panel, it can cooperate with the compact circuit design in the panel to achieve the requirements of a thin, short and high-resolution panel.

Although the present invention has been disclosed as above by the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope of the attached patent application.

10: Semiconductor devices

100: Substrate

112: First gate dielectric layer

114: Second gate dielectric layer

116: Third gate dielectric layer

116t,140t,152t,154t: Top surface

118: Fourth gate dielectric layer

120: First gate

122: Second gate

124: The third gate

130: First semiconductor layer

130a,130b: mixed area

130c: Channel area

132: First level

134: Second level

140: Second semiconductor layer

152: Source

154: Drainage

160: Protective layer

A-A’: line

CH1: First contact hole

CH2: Second contact hole

ND: Normal direction

sw1,sw11,sw12,sw2,sw21,sw22: side wall

Claims (18)

A semiconductor device includes: a substrate; a first gate located above the substrate; a first semiconductor layer located above the first gate; a first gate dielectric layer located between the first gate and the first semiconductor layer; a second gate located above the first semiconductor layer; a second gate dielectric layer located between the first semiconductor layer and the second gate; a second semiconductor layer located above the second gate; a third gate dielectric layer located between the second gate and the second semiconductor layer; a first contact hole continuously penetrating the second gate dielectric layer and the third gate dielectric layer. a second gate dielectric layer; a second contact hole continuously penetrating the second gate dielectric layer and the third gate dielectric layer; a source electrode filled in the first contact hole and electrically connected to the first semiconductor layer and the second semiconductor layer; a drain electrode filled in the second contact hole and electrically connected to the first semiconductor layer and the second semiconductor layer; a third gate electrode located on the second semiconductor layer; and a fourth gate dielectric layer located between the second semiconductor layer and the third gate electrode, wherein the fourth gate dielectric layer covers the first contact hole and the second contact hole in a normal direction of the substrate. A semiconductor device as described in claim 1, wherein the second semiconductor layer extends to the first semiconductor layer and directly contacts the first semiconductor layer. A semiconductor device as described in claim 2, wherein the second semiconductor layer extends into the first contact hole and the second contact hole. A semiconductor device as described in claim 2, wherein a portion of the second semiconductor layer is sandwiched between the first semiconductor layer and the source and between the first semiconductor layer and the drain. The semiconductor device as described in claim 1 further includes: a third semiconductor layer extending from a top surface of the second semiconductor layer to a top surface of the source and a top surface of the drain, and a portion of the source and a portion of the drain are located between the third semiconductor layer and the second semiconductor layer. A semiconductor device as described in claim 5, wherein the oxygen content of the third semiconductor layer is different from the oxygen content of the second semiconductor layer. A semiconductor device as described in claim 1, wherein the second semiconductor layer extends from a top surface of the third gate dielectric layer to a top surface of the source and a top surface of the drain, and a portion of the source and a portion of the drain are located between the second semiconductor layer and the third gate dielectric layer. A semiconductor device as described in claim 1, wherein the source and the drain contact a top surface of the second semiconductor layer. A semiconductor device as described in claim 1, wherein the fourth gate dielectric layer covers a top surface of the source and a top surface of the drain. A semiconductor device as described in claim 1, wherein the source is in direct contact with the first semiconductor layer, and the drain is in direct contact with the first semiconductor layer. A semiconductor device as described in claim 1, wherein the first semiconductor layer comprises: a first layer located on the first gate dielectric layer; and a second layer located on the first layer, wherein the oxygen content of the first layer is different from the oxygen content of the second layer. A method for manufacturing a semiconductor device includes: forming a first gate on a substrate; forming a first gate dielectric layer on the first gate; forming a first semiconductor layer on the first gate dielectric layer; forming a second gate dielectric layer on the first semiconductor layer; forming a second gate on the second gate dielectric layer; forming a third gate dielectric layer on the second gate; forming a first contact hole and a second contact hole in the second gate dielectric layer and the third gate dielectric layer. and respectively expose a portion of the surface of the first semiconductor layer; form a source on the third gate dielectric layer and fill it into the first contact hole; form a drain on the third gate dielectric layer and fill it into the second contact hole; form a second semiconductor layer on the third gate dielectric layer; form a fourth gate dielectric layer on a top surface of the source, a top surface of the drain and a top surface of the second semiconductor layer; and form a third gate on the fourth gate dielectric layer. A method for manufacturing a semiconductor device as described in claim 12, wherein the second semiconductor layer is also formed in the first contact hole and the second contact hole and connected to the first semiconductor layer. A method for manufacturing a semiconductor device as described in claim 12, wherein the source is also formed on the second semiconductor layer, and the drain is also formed on the second semiconductor layer, so that part of the second semiconductor layer is sandwiched between the third gate dielectric layer and the source and between the third gate dielectric layer and the drain. The method for manufacturing a semiconductor device as described in claim 12 further includes: forming a third semiconductor layer on the second semiconductor layer, wherein the third semiconductor layer extends from the top surface of the second semiconductor layer to the top surface of the source and the top surface of the drain. A method for manufacturing a semiconductor device as described in claim 15, wherein the oxygen content of the third semiconductor layer is different from the oxygen content of the second semiconductor layer. A method for manufacturing a semiconductor device as described in claim 12, wherein the second semiconductor layer is also formed on the top surface of the source and the top surface of the drain, so that part of the source and part of the drain are located between the second semiconductor layer and the third gate dielectric layer. A method for manufacturing a semiconductor device as described in claim 12, wherein the source is in direct contact with the first semiconductor layer, and the drain is in direct contact with the first semiconductor layer.

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