TWI877927B - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

A semiconductor device includes first to third source/drain electrode, a first insulating structure, a second insulating structure, a semiconductor structure, a gate dielectric layer and a gate electrode. The first insulation structure is located on the first source/drain electrode and has a first through hole. The second source/drain electrode is located on the first insulating structure and has a second through hole. The second insulation structure is located on the second source/drain electrode and has a third through hole. The third source/drain electrode is located on the second insulating structure and has a fourth through hole. The semiconductor structure extends upward from the first source/drain electrode in the first through hole along the sidewall of the first through hole, and extends continuously and sequentially along the sidewall of the second through hole, the side of the third through hole and the sidewall of the fourth through hole, reaching the third source/drain.

Description

Semiconductor device and method for manufacturing the same

The present invention relates to a semiconductor device and a method for manufacturing the same.

At present, general thin film transistors usually use amorphous silicon semiconductors as channel materials. Due to the simple process and low cost of amorphous silicon semiconductors, they are widely used in various thin film transistors. However, with the continuous advancement of display technology, the resolution of display panels is also constantly improving. In order to reduce the size of thin film transistors in pixel circuits, many manufacturers are committed to developing semiconductor materials with higher carrier mobility, including metal oxide semiconductor materials.

The research and development of these new semiconductor materials aims to improve the performance of thin film transistors and thus enhance the overall performance of display devices. Metal oxide semiconductor materials have excellent electron mobility and can cope with the ever-increasing resolution requirements. Therefore, manufacturers seek these new materials to achieve smaller and more efficient pixel configurations while ensuring continued improvement in display quality. This also promotes technological innovation and process improvements in the field of semiconductor materials.

The present invention provides a semiconductor device having the advantages of high turn-on current (I _on ), high critical voltage (Vth), low leakage current (I _off ) and small footprint.

The present invention provides a method for manufacturing a semiconductor device, which has the advantages of high yield and high alignment accuracy.

At least one embodiment of the present invention provides a semiconductor device, which includes a substrate, a first source/drain, a first insulating structure, a second source/drain, a second insulating structure, a third source/drain, a semiconductor structure, a gate dielectric layer, and a gate. The first source/drain is located on the substrate. The first insulating structure is located on the first source/drain and has a first through hole overlapping the top surface of the first source/drain. The orthographic projection pattern of the first through hole on the substrate is completely located within the orthographic projection pattern of the first source/drain on the substrate. The second source/drain is located on the first insulating structure and has a second through hole overlapping the first through hole. The second insulating structure is located on the second source/drain and has a third through hole overlapping the second through hole. The third source/drain is located on the second insulating structure and has a fourth through hole overlapping the third through hole. The semiconductor structure extends upward from the top surface of the first source/drain in the first through hole along the side wall of the first through hole, and continuously and sequentially extends along the side wall of the second through hole, the side wall of the third through hole, and the side wall of the fourth through hole to the top surface of the third source/drain. The gate dielectric layer is located on the semiconductor structure. The gate is located on the gate dielectric layer.

At least one embodiment of the present invention provides a method for manufacturing a semiconductor device, which includes the following steps. A first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer, and a third conductive layer are sequentially formed. Multiple etching processes are performed on the first conductive layer, the first insulating layer, the second conductive layer, the second insulating layer, and the third conductive layer to obtain a first source/drain, a first insulating structure with a first through hole, a second source/drain with a second through hole, a second insulating structure with a third through hole, and a third source/drain with a fourth through hole, wherein the method for performing multiple etching processes includes the following steps. A patterned photoresist layer is formed on the third conductive layer. A first wet etching process is performed on the third conductive layer using the patterned photoresist layer as a mask to obtain a third source/drain. A first dry etching process is performed on the second insulating layer using the patterned photoresist layer as a mask to obtain an intermediate insulating structure, wherein the intermediate insulating structure has an opening overlapping the fourth through hole, and the width of the opening is smaller than the width of the fourth through hole. A second dry etching process or a second wet etching process is performed on the second conductive layer using the intermediate insulating structure and the patterned photoresist layer as masks to obtain a second source/drain. The patterned photoresist layer is removed. Perform a third dry etching process on the intermediate insulating structure using the third source/drain as a mask to obtain a second insulating structure. Perform a fourth dry etching process on the first insulating layer using the second source/drain as a mask to obtain a first insulating structure. Form a semiconductor structure in the first through hole, the second through hole, the third through hole, and the fourth through hole. Form a gate dielectric layer on the semiconductor structure. Form a gate on the gate dielectric layer.

At least one embodiment of the present invention provides a method for manufacturing a semiconductor device, which includes the following steps: forming a first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer, and a third conductive layer in sequence; performing multiple etching processes on the first conductive layer, the first insulating layer, the second conductive layer, the second insulating layer, and the third conductive layer to obtain a first source/drain, a first insulating structure with a first through hole, a second source/drain with a second through hole, a second insulating structure with a third through hole, and a third source/drain with a fourth through hole, wherein the method for performing multiple etching processes includes the following steps. A first patterned photoresist layer is formed on the second conductive layer. A first etching process is performed on the second conductive layer using the first patterned photoresist layer as a mask to obtain a second source/drain. A second etching process is performed on the first insulating layer using the second source/drain as a mask to obtain a first insulating structure. A second insulating layer and a third conductive layer are sequentially formed above the second source/drain. A second patterned photoresist layer is formed on the third conductive layer. A third etching process is performed on the third conductive layer using the second patterned photoresist layer as a mask to obtain a third source/drain. Perform a fourth etching process on the second insulating layer using the third source/drain as a mask to obtain a second insulating structure. Form a semiconductor structure in the first through hole, the second through hole, the third through hole, and the fourth through hole. Form a gate dielectric layer on the semiconductor structure. Form a gate on the gate dielectric layer.

10,10A,20:Semiconductor devices

100: Substrate

210,210A: First source/drain

210t,230t:Top

210w, 310w, 220w, 320w, 230w: outer side wall

210’: First conductive layer

220,220A: Second source/drain

220’: Second conductive layer

222,232,232’: groove

230: Third source/drain

230’: The third conductive layer

310,310A: First insulation structure

310’: First insulating layer

320: Second insulation structure

320’: Second insulating layer

320”: Intermediate insulation structure

330: Gate dielectric layer

400,400A:Semiconductor structure

410,410A: First semiconductor layer

420,420A: Second semiconductor layer

430,430A: Third semiconductor layer

500,500A: Gate

CL: Center Line

D1, D1’, D2: Depth

H1, H1A: First through hole

H2, H2A: Second through hole

H3: The third through hole

H4: Fourth through hole

ND: Normal direction

O,P: Open

O1: First opening

PR: Patterned photoresist layer

PR1: First patterned photoresist layer

PR2: Second patterned photoresist layer

T1: First transistor

T2: Second transistor

w1,w2,w3:width

FIG1A is a schematic top view of a semiconductor device according to an embodiment of the present invention.

FIG1B is a schematic cross-sectional view along line A-A’ of FIG1A .

FIG2A is an equivalent circuit diagram of a semiconductor device according to an embodiment of the present invention.

FIG2B is an equivalent circuit diagram of a semiconductor device according to an embodiment of the present invention.

Figures 3A to 12A are top-view schematic diagrams of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

Figures 3B to 12B are schematic cross-sectional views along lines A-A’ of Figures 3A to 12A, respectively.

FIG13A is a top view schematic diagram of another semiconductor device according to an embodiment of the present invention.

FIG13B is a schematic cross-sectional view along line A-A’ of FIG13A .

Figures 14A to 14I are cross-sectional schematic diagrams of a method for manufacturing a semiconductor device according to another embodiment of the present invention.

Figures 15A and 15B are cross-sectional schematic diagrams of a method for manufacturing a semiconductor device according to another embodiment of the present invention.

FIG. 1A is a schematic top view of a semiconductor device 10 according to an embodiment of the present invention. FIG. 1B is a schematic cross-sectional view along line A-A' of FIG. 1A. Referring to FIG. 1A and FIG. 1B, the semiconductor device 10 includes a first source/drain 210, a first insulating structure 310, a second source/drain 220, a second insulating structure 320, a third source/drain 230, a semiconductor structure 400, a gate dielectric layer 330, and a gate 500.

The substrate 100 is, for example, a rigid substrate, and its material may be glass, quartz, organic polymer or opaque/reflective material (e.g., conductive material, metal, wafer, ceramic or other applicable material) or other applicable material. However, the present invention is not limited thereto, and in other embodiments, the substrate 100 may also be a flexible substrate or a stretchable substrate. For example, the materials of the flexible substrate and the stretchable substrate include polyimide (PI), polydimethylsiloxane (PDMS), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyester (PES), polymethylmethacrylate (PMMA), polycarbonate (PC), polyurethane PU or other suitable materials.

In this embodiment, the first source/drain 210, the first insulating structure 310, the second source/drain 220, the second insulating structure 320 and the third source/drain 230 are stacked in sequence on the substrate 100 along the normal direction ND of the top surface of the substrate 100.

The first source/drain 210 is located on the substrate 100. In this embodiment, the first source/drain 210 directly contacts the top surface of the substrate 100, but the present invention is not limited thereto. In other embodiments, a buffer layer (not released) may be additionally included between the first source/drain 210 and the substrate 100, and the buffer layer is used, for example, as a hydrogen barrier layer and/or a metal ion barrier layer.

The first insulating structure 310 is located on the first source/drain 210 and has a first through hole H1 overlapping the top surface 210t of the first source/drain 210. The orthographic projection pattern of the first through hole H1 on the substrate 100 is completely located within the orthographic projection pattern of the first source/drain 210 on the substrate 100.

The second source/drain 220 is located on the first insulating structure 310 and has a second through hole H2 overlapping the first through hole H1. The width w1 of the first through hole H1 is less than or equal to the width w2 of the second through hole H2. In this embodiment, the second source/drain 220 is aligned with the first insulating structure 310, and the second through hole H2 is aligned with the first through hole H1. In some embodiments, the width w1 of the first through hole H1 is greater than 2 microns.

The second insulating structure 320 is located on the second source/drain 220 and has a third through hole H3 overlapping the second through hole H2. The width w2 of the second through hole H2 is smaller than the width w3 of the third through hole H3, and part of the top surface of the second source/drain 220 is located at the bottom of the third through hole H3.

The third source/drain 230 is located on the second insulating structure 320 and has a fourth through hole H4 overlapping the third through hole H3. The width w3 of the third through hole H3 is less than or equal to the width w4 of the fourth through hole H4. In this embodiment, the third source/drain 230 is aligned with the second insulating structure 320, and the fourth through hole H4 is aligned with the third through hole H3.

In some embodiments, the materials of the first source/drain 210, the second source/drain 220, and the third source/drain 230 include, for example, metals such as chromium, gold, silver, copper, tin, lead, cobalt, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, nickel, the above alloys, the above metal oxides, the above metal nitrides, or the above combinations or other conductive materials. The materials of the first source/drain 210, the second source/drain 220, and the third source/drain 230 are the same or different from each other. The first source/drain 210, the second source/drain 220, and the third source/drain 230 may each have a single-layer structure or a multi-layer structure.

In some embodiments, the materials of the first insulating structure 310 and the second insulating structure 320 include, for example, silicon oxide, silicon oxynitride, silicon nitride, aluminum oxide, beta oxide, zirconium oxide or other suitable materials or combinations of the foregoing materials. In some embodiments, the materials of the first insulating structure 310 and the second insulating structure 320 include oxides (such as silicon oxide) and can be used as oxygen storage/oxygen replenishing layers, thereby adjusting the oxygen concentration in the semiconductor structure 400 during the manufacturing process. In some embodiments, the first insulating structure 310 and the second insulating structure 320 can each have a single-layer structure or a multi-layer structure. When the first insulating structure 310 and the second insulating structure 320 have a multi-layer structure, an oxide layer (such as a silicon oxide layer) and a nitride layer (such as a silicon nitride layer) can be used in combination to optimize the performance of the semiconductor device 10. For example, the oxide layer can be used as an oxygen storage/replenishing layer, and the nitride layer can be used as a hydrogen barrier layer or a metal ion barrier layer.

The semiconductor structure 400 extends upward from the top surface 210t of the first source/drain 210 in the first through hole H1 along the side wall of the first through hole H1, and continuously and sequentially extends along the side wall of the second through hole H2, the side wall of the third through hole H3, and the side wall of the fourth through hole H4 to the top surface 230t of the third source/drain 230. The semiconductor structure 400 contacts the first source/drain 210, the second source/drain 220, and the third source/drain 230. In some embodiments, the shapes of the first through hole H1, the second through hole H2, the third through hole H3, and the fourth through hole H4 in the top view are circular, but the present invention is not limited thereto. In other embodiments, the shapes of the first through hole H1, the second through hole H2, the third through hole H3 and the fourth through hole H4 in the top view are rectangular, elliptical or other geometric shapes.

In some embodiments, the material of the semiconductor structure 400 includes an oxide of three or more of gallium (Ga), zinc (Zn), indium (In), tin (Sn), aluminum (Al), and tungsten (W) (e.g., metal oxides such as indium gallium zinc tin oxide (IGZTO), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), aluminum zinc tin oxide (AZTO), indium tungsten zinc oxide (IWZO), and indium gallium oxide (IGO)) or a rare earth-doped metal oxide (e.g., Ln-IZO) or other suitable metal oxides or a combination of the above materials.

The semiconductor structure 400 has a single-layer structure or a multi-layer structure. In the present embodiment, the semiconductor structure 400 includes a first semiconductor layer 410, a second semiconductor layer 420, and a third semiconductor layer 430 sequentially stacked above the first source/drain 210. In some embodiments, the first semiconductor layer 410, the second semiconductor layer 420, and the third semiconductor layer 430 include the same or different materials. In some embodiments, the first semiconductor layer 410, the second semiconductor layer 420, and the third semiconductor layer 430 include the same metal element but have different oxygen concentrations.

In some embodiments, the orthographic projection shape of the semiconductor structure 400 on the substrate 100 is circular, but the present invention is not limited thereto. In other embodiments, the orthographic projection shape of the semiconductor structure 400 on the substrate 100 is rectangular, elliptical or other geometric shapes.

The gate dielectric layer 330 is located on the semiconductor structure 400. The material of the gate dielectric layer 330 includes silicon oxide, silicon oxynitride, silicon nitride, aluminum oxide, einsteinium oxide, zirconium oxide or other suitable materials or a combination of the foregoing materials. In some embodiments, the thickness of the gate dielectric layer 330 is less than or equal to the thickness of the first insulating structure 310 and the thickness of the second insulating structure 320, but the present invention is not limited thereto.

In some embodiments, the gate dielectric layer 330 extends downward from the top surface 230t of the third source/drain 230 and sequentially contacts the outer sidewall 230w of the third source/drain 230, the outer sidewall 320w of the second insulating structure 320, the outer sidewall 220w of the second source/drain 220, the outer sidewall 310w of the first insulating structure 310, and the outer sidewall 210w of the first source/drain 210, but the present invention is not limited thereto.

The gate 500 is located on the gate dielectric layer 330. In some embodiments, the gate dielectric layer 330 and the gate 500 are partially filled into the first through hole H1, the second through hole H2, the third through hole H3 and the fourth through hole H4. In some embodiments, the length of the gate 500 is greater than the width w4 of the fourth through hole H4, thereby preferably covering the entire fourth through hole H4.

In some embodiments, the material of the gate 500 includes, for example, metals such as chromium, gold, silver, copper, tin, lead, uranium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, nickel, the above alloys, the above metal oxides, the above metal nitrides, or the above combinations or other conductive materials. The gate 500 may have a single-layer structure or a multi-layer structure.

In this embodiment, the equivalent circuit diagram of the semiconductor device 10 is actually equivalent to a first transistor T1 and a second transistor T2 connected in series, as shown in FIG. 2A and FIG. 2B. The first transistor T1 and the second transistor T2 share the same gate, such as the gate 500 shown in FIG. 1B. The first transistor T1 and the second transistor T2 share one of the source/drain, such as the second source/drain 220 shown in FIG. 1B.

In this embodiment, the current needs to pass through the semiconductor structure 400 twice when flowing from the first source/drain 210 to the third source/drain 230 (or from the third source/drain 230 to the first source/drain 210), one time passing through the semiconductor structure 400 between the first source/drain 210 and the second source/drain 220, and the other time passing through the semiconductor structure 400 between the second source/drain 220 and the third source/drain 230. With such a configuration, the semiconductor device 10 has the advantages of high turn-on current (I _on ), high critical voltage (Vth), and low leakage current (I _off ).

In some embodiments, the second source/drain 220 may not be connected to other signal lines, as shown in FIG. 2A. In other embodiments, the second source/drain 220 is connected to other signal lines, as shown in FIG. 2B.

In this embodiment, the first source/drain 210, the first insulating structure 310, the second source/drain 220, the second insulating structure 320 and the third source/drain 230 are stacked on the substrate 100 to effectively reduce the area required for setting the semiconductor device 10. Specifically, compared with setting the first transistor T1 and the second transistor T2 on the same plane, the semiconductor device 10 can reduce the area required for the first transistor T1 and the second transistor T2 connected in series by using the stacking design.

FIG. 3A to FIG. 12A are top views of the manufacturing method of the semiconductor device 10 of FIG. 1A and FIG. 1B. FIG. 3B to FIG. 12B are cross-sectional views along the line A-A' of FIG. 3A to FIG. 12A, respectively. Referring to FIG. 3A and FIG. 3B, a first conductive layer 210' is formed above the substrate 100.

Please refer to FIG. 4A and FIG. 4B , an etching process is performed on the first conductive layer 210' to obtain the first source/drain 210.

Referring to FIG. 5A and FIG. 5B , a first insulating layer 310' is formed on the first source/drain 210. The first insulating layer 310' has, for example, a single-layer or multi-layer structure. A second conductive layer 220' is formed on the first insulating layer 310'. A first patterned photoresist layer PR1 is formed on the second conductive layer 220'. In this embodiment, the first patterned photoresist layer PR1 has a first opening O1. The orthographic projection of the first opening O1 on the substrate 100 is located in the orthographic projection of the first source/drain 210 on the substrate 100.

Referring to FIG. 6A and FIG. 6B , a first etching process is performed on the second conductive layer 220' using the first patterned photoresist layer PR1 as a mask to obtain the second source/drain 220. The second through hole H2 of the second source/drain 220 is aligned with the first opening O1. In some embodiments, the first etching process includes a dry etching process or a wet etching process. In some embodiments, after obtaining the second source/drain 220, the first patterned photoresist layer PR1 is optionally removed. The method of removing the first patterned photoresist layer PR1 includes an ashing process or other suitable processes.

Please refer to FIG. 7A and FIG. 7B , the second etching process is performed on the first insulating layer 310' using the second source/drain 220 as a mask to obtain the first insulating structure 310 and expose the first source/drain 210. In this embodiment, the first insulating structure 310 is formed by a self-alignment method, and the first through hole H1 of the first insulating structure 310 is aligned with the second through hole H2 of the second source/drain 220. In some embodiments, the second etching process includes a dry etching process or a wet etching process.

In this embodiment, the first patterned photoresist layer PR1 is removed before the second etching process (see FIG. 5B ), but the present invention is not limited thereto. In other embodiments, the first patterned photoresist layer PR1 is removed after the second etching process.

Referring to FIG. 8A and FIG. 8B , a second insulating layer 320' and a third conductive layer 230' are sequentially formed on the second source/drain 220. In this embodiment, the second insulating layer 320' is filled into the second through hole H2 and the first through hole H1. A second patterned photoresist layer PR2 is formed on the third conductive layer 230'. In this embodiment, the second patterned photoresist layer PR2 has a second opening O2. The orthographic projection of the second opening O2 on the substrate 100 at least partially overlaps the orthographic projection of the second through hole H2 and the first through hole H1 on the substrate 100.

Referring to FIG. 9A and FIG. 9B , a third etching process is performed on the third conductive layer 230' using the second patterned photoresist layer PR2 as a mask to obtain the third source/drain 230. The second four-hole H4 of the third source/drain 230 is aligned with the second opening O2. In some embodiments, the third etching process includes a dry etching process or a wet etching process. In some embodiments, after obtaining the third source/drain 230, the second patterned photoresist layer PR2 is optionally removed. The method of removing the second patterned photoresist layer PR2 includes an ashing process or other suitable processes.

Please refer to FIG. 10A and FIG. 10B , the fourth etching process is performed on the second insulating layer 320' using the third source/drain 230 as a mask to obtain the second insulating structure 320, and expose the first source/drain 210 and the second source/drain 220. In this embodiment, the second insulating structure 320 is formed by a self-alignment method, and the third through hole H3 of the second insulating structure 320 is aligned with the fourth through hole H4 of the third source/drain 230. In some embodiments, the fourth etching process includes a dry etching process or a wet etching process.

In this embodiment, the second patterned photoresist layer PR2 is removed before the fourth etching process (see FIG. 8B ), but the present invention is not limited thereto. In other embodiments, the second patterned photoresist layer PR2 is removed after the fourth etching process.

In this embodiment, the center of the fourth through hole H4 is aligned with the center of the second through hole H2, but the present invention is not limited thereto. In this embodiment, since the second source/drain 220 and the third source/drain 230 are formed by two different photolithography processes, the second through hole H2 of the second source/drain 220 and the fourth through hole H4 of the third source/drain 230 may be offset due to process errors, resulting in the center of the fourth through hole H4 not being aligned with the center of the second through hole H2.

Referring to FIG. 11A and FIG. 11B , a first semiconductor material layer 410' is formed on the top surface of the first source/drain 210, the side wall of the first through hole H1, the side wall of the second through hole H2, the side wall of the third through hole H3, the side wall of the fourth through hole H4, and the top surface of the third source/drain 230. A second semiconductor material layer 420' is formed on the first semiconductor material layer 410'. A third semiconductor material layer 430' is formed on the second semiconductor material layer 420'.

Referring to FIG. 12A and FIG. 12B , the first semiconductor material layer 410 ', the second semiconductor material layer 420 ', and the third semiconductor material layer 430 ' are patterned to form a semiconductor structure 400 including the first semiconductor layer 410, the second semiconductor layer 420, and the third semiconductor layer 430.

In some embodiments, a patterned photoresist layer (not shown) is formed on the third semiconductor material layer 430', and the patterned photoresist layer is used as a mask to etch the first semiconductor material layer 410', the second semiconductor material layer 420' and the third semiconductor material layer 430' to form the first semiconductor layer 410, the second semiconductor layer 420 and the third semiconductor layer 430 respectively. Therefore, the first semiconductor layer 410, the second semiconductor layer 420 and the third semiconductor layer 430 have substantially the same orthographic projection pattern on the substrate 100.

In some embodiments, after forming the semiconductor structure 400, a first annealing process is performed to diffuse oxygen in the semiconductor structure 400 or the environment and store it in the first insulating structure 310 and the second insulating structure 320.

Finally, returning to FIG. 1A and FIG. 1B , a gate dielectric layer 330 is formed on the semiconductor structure 400. A gate 500 is formed on the gate dielectric layer 330.

In some embodiments, before forming the gate 500, a second annealing process is performed to diffuse the oxygen stored in the first insulating structure 310 and the second insulating structure 320 into the semiconductor structure 400, thereby reducing the oxygen vacancies in the portion of the semiconductor structure 400 that contacts the first insulating structure 310 and the second insulating structure 320 (i.e., the portion that serves as the semiconductor channel region) and increasing its resistivity, thereby reducing the leakage current problem.

FIG. 13A is a schematic top view of another semiconductor device 10A according to an embodiment of the present invention. FIG. 13B is a schematic cross-sectional view along line A-A' of FIG. 13A. It must be noted that the embodiments of FIG. 13A and FIG. 13B use the component numbers and partial contents of the embodiments of FIG. 1A to FIG. 12B, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, which will not be elaborated here.

Referring to FIG. 13A and FIG. 13B , in this embodiment, the semiconductor device 10A includes a first source/drain 210A, a first insulating structure 310A, a second source/drain 220A, a semiconductor structure 400A, a gate dielectric layer 330, and a gate 500A.

In some embodiments, the semiconductor device 10A of FIGS. 13A and 13B shares some of the manufacturing processes with the semiconductor device 10 of FIGS. 1A and 1B. For example, in the steps of FIGS. 3A to 4B, the first conductive layer 210' is patterned to simultaneously form the first source/drain 210 of the semiconductor device 10 and the first source/drain 210A of the semiconductor device 10A.

In the steps of FIG. 5A to FIG. 6B , the second conductive layer 220' is patterned to simultaneously form the second source/drain 220 of the semiconductor device 10 and the second source/drain 220A of the semiconductor device 10A.

In the steps of FIG. 7A and FIG. 7B , the first insulating layer 310' is patterned to simultaneously form the first insulating structure 310 of the semiconductor device 10 and the first insulating structure 310A of the semiconductor device 10A.

In the steps of FIG. 9A to FIG. 10B , the third conductive layer 230' and the second insulating layer 320' above the second source/drain 220A of the semiconductor device 10A are removed.

In the steps of FIG. 11A to FIG. 12B, the first semiconductor material layer 410', the second semiconductor material layer 420' and the third semiconductor material layer 430' are patterned to form a semiconductor structure 400A including the first semiconductor layer 410A, the second semiconductor layer 420A and the third semiconductor layer 430A. The semiconductor structure 400A is filled into the first through hole H1A of the first insulating structure 310A and the second through hole H2A of the second source/drain 220A.

A gate dielectric layer 330 is formed to cover the semiconductor structure 400 of FIGS. 1A and 1B and the semiconductor structure 400A of FIGS. 13A and 13B. A gate 500A is formed on the semiconductor structure 400A, and the gate 500A overlaps the semiconductor structure 400A. In some embodiments, the gate 500 of FIGS. 1A and 1B and the gate 500A of FIGS. 13A and 13B may be formed simultaneously.

In some embodiments, the semiconductor device 10A of FIG. 13A and FIG. 13B is electrically connected to or electrically independent of the semiconductor device 10 of FIG. 1A and FIG. 1B. The semiconductor device 10A and the semiconductor device 10 can be disposed at different locations according to requirements. For example, when the semiconductor device 10A and the semiconductor device 10 are both disposed in a display device, the semiconductor device 10A and the semiconductor device 10 are disposed in a display area and/or a peripheral area of the display device according to actual requirements.

Figures 14A to 14I are cross-sectional schematic diagrams of a method for manufacturing a semiconductor device according to another embodiment of the present invention. It must be noted that the embodiments of Figures 14A to 14I use the component numbers and partial contents of the embodiments of Figures 1A to 12B, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. For the description of the omitted parts, please refer to the aforementioned embodiments, which will not be elaborated here.

Referring to FIG. 14A , a first conductive layer, a first insulating layer 310’, a second conductive layer 220’, a second insulating layer 320’ and a third conductive layer 230’ are sequentially formed. In this embodiment, before forming the first insulating layer 310’, an etching process is first performed to pattern the first conductive layer, thereby forming a first source/drain 210, as shown in FIGS. 3A to 4B .

Next, please refer to FIG. 14B to form a patterned photoresist layer PR on the third conductive layer 230'. In this embodiment, the patterned photoresist layer PR has an opening O. The orthographic projection of the opening O on the substrate 100 is located in the orthographic projection of the first source/drain 210 on the substrate 100.

Next, please refer to FIG. 14C , and the third conductive layer 230' is subjected to a first wet etching process using the patterned photoresist layer PR as a mask to obtain the third source/drain 230. In some embodiments, the third source/drain 230 and the second insulating layer 320' thereunder have a high etching selectivity in the first wet etching process. The etching rate of the third source/drain 230 in the first wet etching process is greater than the etching rate of the second insulating layer 320' in the first wet etching process. In some embodiments, the etchant used in the first wet etching process includes aluminum acid, copper acid, oxalic acid, silver acid or other suitable etchants or a combination thereof.

In this embodiment, the third source/drain 230 is retracted due to side etching to form a groove 232 formed by the bottom surface of the patterned photoresist layer PR, the sidewall of the third source/drain 230, and the top surface of the second insulating layer 320'. In some embodiments, the depth D1 of the groove 232 is 0.1 micron to 1 micron. The depth D1 is the horizontal distance between the sidewall of the third source/drain 230 and the sidewall of the patterned photoresist layer PR.

In some embodiments, the patterned photoresist layer PR and the second insulating layer 320' may also be partially etched in the first wet etching process. However, since the etching rate of the third conductive layer 230' in the first wet etching process is significantly faster than the etching rate of the patterned photoresist layer PR and the second insulating layer 320' in the first wet etching process, it is beneficial to form the groove 232.

In this embodiment, the third source/drain 230 has a fourth through hole H4. The groove 232 can be regarded as a part of the fourth through hole H4.

Referring to FIG. 14D , the second insulating layer 320' is subjected to a first dry etching process using the patterned photoresist layer PR as a mask to obtain an intermediate insulating structure 320". The intermediate insulating structure 320" has an opening P overlapping the fourth through hole H4, and the width w3' of the opening P is smaller than the width w4 of the fourth through hole H4. In this embodiment, the first dry etching process is anisotropic etching. Since the patterned photoresist layer PR shields the third source/drain 230, the third source/drain 230 is hardly damaged in the first dry etching process. The intermediate insulating structure 320" is, for example, aligned with the patterned photoresist layer PR.

Please refer to FIG. 14E , the second conductive layer 220' is subjected to a second dry etching process using the intermediate insulating structure 320" and the patterned photoresist layer PR as a mask to obtain the second source/drain 220. In this embodiment, the second dry etching process is anisotropic etching. Since the patterned photoresist layer PR shields the third source/drain 230, the third source/drain 230 is hardly damaged in the second dry etching process. The opening P of the intermediate insulating structure 320" is aligned with the second through hole H2 of the second source/drain 220, for example.

Please refer to FIG. 14F to remove the patterned photoresist layer PR. The third source/drain 230 is used as a mask to perform a third dry etching process on the intermediate insulating structure 320” to obtain the second insulating structure 320. The second source/drain 220 is used as a mask to perform a fourth dry etching process on the first insulating layer 310’ to obtain the first insulating structure 310. In some embodiments, the third dry etching process and the fourth dry etching process are performed simultaneously.

In this embodiment, since the manufacturing process of the first insulating structure 310, the second source/drain 220, the second insulating structure 320 and the third source/drain 230 utilizes the same patterned photoresist layer PR, the first through hole H1 of the first insulating structure 310, the second through hole H2 of the second source/drain 220, the third through hole H3 of the second insulating structure 320 and the fourth through hole H4 of the third source/drain 230 have better symmetry. For example, the first through hole H1, the second through hole H2, the third through hole H3 and the fourth through hole H4 have a left-right symmetric structure based on the center line CL. In some embodiments, the center of the first through hole H1, the center of the second through hole H2, the center of the third through hole H3, and the center of the fourth through hole H4 are aligned with each other.

In some embodiments, the difference between the width w4 of the fourth through hole H4 and the width w2 of the second through hole H2 is 2 microns to 3 microns.

Referring to FIG. 14G , a semiconductor structure 400 is formed in the first through hole H1, the second through hole H2, the third through hole H3, and the fourth through hole H4. In this embodiment, the semiconductor structure 400 has a single-layer structure, but the present invention is not limited thereto. In other embodiments, the semiconductor structure 400 has a multi-layer structure.

In some embodiments, after forming the semiconductor structure 400, a first annealing process is performed to diffuse oxygen in the semiconductor structure 400 or the environment and store it in the first insulating structure 310 and the second insulating structure 320.

Referring to FIG. 14H , a gate dielectric layer 330 is formed on the semiconductor structure 400. Finally, a gate 500 is formed on the gate dielectric layer 330 to obtain the semiconductor device 20, as shown in FIG. 14I . In some embodiments, before forming the gate 500, a second annealing process is performed to diffuse the oxygen stored in the first insulating structure 310 and the second insulating structure 320 into the semiconductor structure 400, thereby reducing oxygen vacancies in the portion of the semiconductor structure 400 that contacts the first insulating structure 310 and the second insulating structure 320 (i.e., the portion that serves as the semiconductor channel region), and increasing its resistivity, thereby reducing the problem of leakage current. In some embodiments, the equivalent circuit diagram of the semiconductor device 20 is shown in FIG2A or FIG2B. The semiconductor device 20 has the advantages of high turn-on current (I _on ), high critical voltage (Vth), and low leakage current (I _off ).

In this embodiment, the first source/drain 210, the first insulating structure 310, the second source/drain 220, the second insulating structure 320 and the third source/drain 230 are stacked on the substrate 100 to effectively reduce the area required for setting up the semiconductor device 20.

FIG. 15A to FIG. 15B are cross-sectional schematic diagrams of a method for manufacturing a semiconductor device according to another embodiment of the present invention. It must be noted that the embodiment of FIG. 15A to FIG. 15B uses the component numbers and partial contents of the embodiment of FIG. 14A to FIG. 14I, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical content is omitted. The description of the omitted part can be referred to the aforementioned embodiment, and will not be repeated here.

FIG. 15A is a continuation of the step of FIG. 14D , wherein a second wet etching process is performed on the second conductive layer 220′ using the intermediate insulating structure 320″ and the patterned photoresist layer PR as a mask to obtain the second source/drain 220. In some embodiments, the second source/drain 220 and the first insulating layer 310′ thereunder are separated from each other during the second wet etching process. The process has a high etching selectivity. The etching rate of the second source/drain 220 in the second wet etching process is greater than the etching rate of the first insulating layer 310' in the second wet etching process. In some embodiments, the etchant used in the second wet etching process includes aluminum acid, copper acid, oxalic acid, silver acid or other suitable etchants or a combination of the foregoing.

In this embodiment, the second source/drain 220 is retracted due to side etching to form a groove 222 formed by the bottom surface of the intermediate insulating structure 320", the sidewall of the second source/drain 220 and the top surface of the first insulating layer 310'. In some embodiments, the depth D2 of the groove 222 is 0.1 micron to 0.5 micron. The depth D2 is the horizontal distance between the sidewall of the second source/drain 220 and the sidewall of the intermediate insulating structure 320".

In some embodiments, the patterned photoresist layer PR, the intermediate insulating structure 320″ and the first insulating layer 310′ may also be partially etched in the second wet etching process. However, since the etching rate of the second conductive layer 220′ in the second wet etching process is significantly faster than the etching rate of the intermediate insulating structure 320″ and the first insulating layer 310′ in the second wet etching process, it is beneficial to the formation of the groove 222.

In this embodiment, the second source/drain 220 has a second through hole H2. The groove 222 can be regarded as a part of the second through hole H2.

In this embodiment, the third source/drain 230 may also be further etched in the second wet etching process, so that the depth of the groove 232' is further increased to the depth D1'. In some embodiments, the depth D1' of the groove 232' is 0.1 micron to 1 micron.

Please refer to FIG. 15B to remove the patterned photoresist layer PR. The third source/drain 230 is used as a mask to perform a third dry etching process on the intermediate insulating structure 320” to obtain the second insulating structure 320. The second source/drain 220 is used as a mask to perform a fourth dry etching process on the first insulating layer 310’ to obtain the first insulating structure 310. In some embodiments, the third dry etching process and the fourth dry etching process are performed simultaneously.

In this embodiment, since the manufacturing process of the first insulating structure 310, the second source/drain 220, the second insulating structure 320 and the third source/drain 230 uses the same patterned photoresist layer PR, the first through hole H1 of the first insulating structure 310, the second through hole H2 of the second source/drain 220, the third through hole H3 of the second insulating structure 320 and the fourth through hole H4 of the third source/drain 230 have better symmetry. For example, the first through hole H1, the second through hole H2, the third through hole H3 and the fourth through hole H4 have a left-right symmetric structure based on the center line CL. In some embodiments, the center of the first through hole H1, the center of the second through hole H2, the center of the third through hole H3, and the center of the fourth through hole H4 are aligned with each other.

Finally, the steps shown in FIG. 14G to FIG. 14I are performed to form the semiconductor structure 400, the gate dielectric layer 300 and the gate 500.

In summary, in the semiconductor device of the embodiment of the present invention, the first source/drain, the first insulating structure, the second source/drain, the second insulating structure and the third source/drain are stacked, thereby effectively reducing the area required for setting up the semiconductor device.

10: Semiconductor devices

100: Substrate

210: First source/drain

210t,230t:Top

210w, 310w, 220w, 320w, 230w: outer side wall

220: Second source/drain

230: Third source/drain

310: First insulation structure

320: Second insulation structure

330: Gate dielectric layer

400:Semiconductor structure

410: First semiconductor layer

420: Second semiconductor layer

430: Third semiconductor layer

500: Gate

H1: First through hole

H2: Second through hole

H3: The third through hole

H4: Fourth through hole

ND: Normal direction

Claims (10)

A semiconductor device, comprising: a first source/drain, located on a substrate; a first insulating structure, located on the first source/drain, and having a first through hole overlapping the top surface of the first source/drain, wherein the orthographic projection pattern of the first through hole on the substrate is completely located within the orthographic projection pattern of the first source/drain on the substrate; a second source/drain, located on the first insulating structure, and having a second through hole overlapping the first through hole; a second insulating structure, located on the second source/drain, and having a third through hole overlapping the second through hole; A third source/drain, located on the second insulating structure and having a fourth through hole overlapping the third through hole; A semiconductor structure, extending upward from the top surface of the first source/drain in the first through hole along the side wall of the first through hole, and continuously and sequentially extending along the side wall of the second through hole, the side wall of the third through hole and the side wall of the fourth through hole to the top surface of the third source/drain; A gate dielectric layer, located on the semiconductor structure; and A gate, located on the gate dielectric layer. A semiconductor device as described in claim 1, wherein the width of the first through hole is less than or equal to the width of the second through hole, the width of the second through hole is less than the width of the third through hole, and the width of the third through hole is less than or equal to the width of the fourth through hole. A semiconductor device as described in claim 1, wherein the semiconductor structure includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer stacked in sequence above the first source/drain. A method for manufacturing a semiconductor device, comprising: Sequentially forming a first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer and a third conductive layer; Performing multiple etching processes on the first conductive layer, the first insulating layer, the second conductive layer, the second insulating layer and the third conductive layer to obtain a first source/drain, a first insulating structure with a first through hole, a second source/drain with a second through hole, a second insulating structure with a third through hole and a third source/drain with a fourth through hole, wherein the method for performing the multiple etching processes comprises: Forming a patterned photoresist layer on the third conductive layer; Performing a first wet etching process on the third conductive layer using the patterned photoresist layer as a mask to obtain the third source/drain; Performing a first dry etching process on the second insulating layer using the patterned photoresist layer as a mask to obtain an intermediate insulating structure, wherein the intermediate insulating structure has an opening overlapping the fourth through hole, and the width of the opening is smaller than the width of the fourth through hole; Performing a second dry etching process or a second wet etching process on the second conductive layer with the intermediate insulating structure and the patterned photoresist layer as masks to obtain the second source/drain; Removing the patterned photoresist layer; Performing a third dry etching process on the intermediate insulating structure with the third source/drain as masks to obtain the second insulating structure; and Performing a fourth dry etching process on the first insulating layer with the second source/drain as masks to obtain the first insulating structure; Forming a semiconductor structure in the first through hole, the second through hole, the third through hole and the fourth through hole; forming a gate dielectric layer on the semiconductor structure; and forming a gate electrode on the gate dielectric layer. A manufacturing method as described in claim 4, wherein the third dry etching process and the fourth dry etching process are performed simultaneously. A manufacturing method as described in claim 4, wherein the center of the fourth through hole is aligned with the center of the second through hole. A manufacturing method as described in claim 4, wherein the difference between the width of the fourth through hole and the width of the second through hole is 2 microns to 3 microns. A method for manufacturing a semiconductor device, comprising: Sequentially forming a first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer and a third conductive layer; Performing multiple etching processes on the first conductive layer, the first insulating layer, the second conductive layer, the second insulating layer and the third conductive layer to obtain a first source/drain, a first insulating structure with a first through hole, a second source/drain with a second through hole, a second insulating structure with a third through hole and a third source/drain with a fourth through hole, wherein the method for performing the multiple etching processes comprises: A first patterned photoresist layer is formed on the second conductive layer; A first etching process is performed on the second conductive layer using the first patterned photoresist layer as a mask to obtain the second source/drain; A second etching process is performed on the first insulating layer using the second source/drain as a mask to obtain the first insulating structure; The second insulating layer and the third conductive layer are sequentially formed above the second source/drain; A second patterned photoresist layer is formed on the third conductive layer; Performing a third etching process on the third conductive layer with the second patterned photoresist layer as a mask to obtain the third source/drain; Performing a fourth etching process on the second insulating layer with the third source/drain as a mask to obtain the second insulating structure; Forming a semiconductor structure in the first through hole, the second through hole, the third through hole and the fourth through hole; Forming a gate dielectric layer on the semiconductor structure; and Forming a gate on the gate dielectric layer. A manufacturing method as described in claim 8, wherein the second insulating layer is filled into the second through hole and the first through hole. The manufacturing method as described in claim 8, wherein the step of forming the semiconductor structure includes: Forming a first semiconductor material layer on the top surface of the first source/drain, the sidewalls of the first through hole, the sidewalls of the second through hole, the sidewalls of the third through hole, the sidewalls of the fourth through hole, and the top surface of the third source/drain; Forming a second semiconductor material layer on the first semiconductor material layer; Forming a third semiconductor material layer on the second semiconductor material layer; and Patterning the first semiconductor material layer, the second semiconductor material layer, and the third semiconductor material layer to form the semiconductor structure including a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer.