TWI867965B - Active device substrate and manufacturing thereof - Google Patents

Abstract

An active device substrate includes a substrate, a gate driving circuit and a pixel control circuit. A pull-up transistor of the gate driving circuit includes a first semiconductor layer, a first gate dielectric portion, a first gate electrode, a first source electrode and a first drain electrode. A driving transistor of the pixel control circuit includes a second semiconductor layer, a second gate dielectric portion, a second gate electrode, a second source electrode and a second drain electrode. The thickness of the first semiconductor layer is greater than the thickness of the second semiconductor layer. The thickness of the second gate dielectric portion is greater than the thickness of the first gate dielectric portion.

Description

Active element substrate and manufacturing method thereof

The present invention relates to an active element substrate and a manufacturing method thereof.

Thin film transistor (TFT) is a field effect transistor that is often used in electronic devices such as displays, photo sensors, antennas, etc. Generally speaking, a thin film transistor includes a gate, a semiconductor layer, a source, and a drain. The gate is used to control the carriers in the semiconductor layer so that current can flow between the source and the drain. The advantages of thin film transistors are low power consumption, high speed, high reliability, low cost, and easy integration. The application range of thin film transistors is very wide. In order to make thin film transistors suitable for different devices, many manufacturers are committed to developing new thin film transistor structures.

The present invention provides an active element substrate and a manufacturing method thereof, which has the advantages of improving the reliability of the pull-up transistor and also enables the driving transistor to control the driving current more accurately.

At least one embodiment of the present invention provides an active element substrate, which includes a substrate, a gate drive circuit and a pixel control circuit. The gate drive circuit includes a first transistor, a second transistor, a third transistor and a pull-up transistor located on the substrate. The pull-up transistor includes a first semiconductor layer, a first gate dielectric portion, a first gate, a first source and a first drain. The first gate dielectric portion contacts the top surface of the first semiconductor layer. The first gate contacts the top surface of the first gate dielectric portion and overlaps the first semiconductor layer. The first gate is electrically connected to the first transistor and the second transistor. The first source and the first drain contact the first semiconductor layer. One of the first source and the first drain is electrically connected to the third transistor. The pixel control circuit is electrically connected to the gate drive circuit and includes a switch transistor and a drive transistor located on the substrate. The drive transistor includes a second semiconductor layer, a second gate dielectric portion, a second gate, a second source and a second drain. The patterned semiconductor layer includes a first semiconductor layer and a second semiconductor layer, and the thickness of the first semiconductor layer is greater than the thickness of the second semiconductor layer. The second gate dielectric portion contacts the top surface of the second semiconductor layer. The patterned insulating layer includes a first gate dielectric portion and a second gate dielectric portion, and the thickness of the second gate dielectric portion is greater than the thickness of the first gate dielectric portion. Based on the top surface of the substrate, the top surface of the first gate dielectric portion and the top surface of the second gate dielectric portion are located at different height positions, and the bottom surface of the first semiconductor layer and the bottom surface of the second semiconductor layer are located at the same height position. The second gate contacts the top surface of the second gate dielectric portion and overlaps the second semiconductor layer. The second gate is electrically connected to the switch transistor. The second source and the second drain contact the second semiconductor layer.

At least one embodiment of the present invention provides a method for manufacturing an active element substrate, comprising the following steps. A semiconductor material layer is formed on a substrate. A first photoresist pattern layer is formed on the semiconductor material layer, wherein the first photoresist pattern layer includes a first mask portion and a second mask portion, wherein the thickness of the first mask portion is greater than the thickness of the second mask portion. A first etching process is performed on the semiconductor material layer using the first mask portion and the second mask portion as masks to form a semiconductor pattern layer. The semiconductor pattern layer includes a first semiconductor layer and a second semiconductor layer, and the thickness of the first semiconductor layer is greater than the thickness of the second semiconductor layer. An insulating material layer is formed on the substrate. A second photoresist pattern layer is formed on the insulating material layer, wherein the second photoresist pattern layer includes a first covering portion overlapping the first semiconductor layer and a second covering portion overlapping the second semiconductor layer, wherein the thickness of the second covering portion is greater than the thickness of the first covering portion. A second etching process is performed on the insulating material layer using the second photoresist pattern layer as a mask to form a patterned insulating layer, wherein the patterned insulating layer includes a first gate dielectric portion overlapping the first semiconductor layer and a second gate dielectric portion overlapping the second semiconductor layer, and the thickness of the second gate dielectric portion is greater than the thickness of the first gate dielectric portion. A first gate and a second gate are formed, wherein the first gate and the second gate are respectively located on the first gate dielectric portion and the second gate dielectric portion. A first source and a first drain are formed which are electrically connected to the first semiconductor layer. A second source and a second drain are formed which are electrically connected to the second semiconductor layer.

FIG1 is a cross-sectional schematic diagram of a pull-up transistor PUT and a drive transistor DT of an active element substrate 10 according to an embodiment of the present invention. FIG1 shows the pull-up transistor PUT and the drive transistor DT in the active element substrate 10, and omits other components. Referring to FIG1 , the pull-up transistor PUT and the drive transistor DT are disposed on a substrate 100.

The substrate 100 is, for example, a rigid substrate, and its material may be glass, quartz, organic polymer or other applicable materials. However, the present invention is not limited thereto, and in other embodiments, the substrate 100 may also be a flexible substrate or a stretchable substrate. For example, the materials of the flexible substrate and the stretchable substrate include polyimide (PI), polydimethylsiloxane (PDMS), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyester (PES), polymethylmethacrylate (PMMA), polycarbonate (PC), polyurethane PU or other suitable materials.

The pull-up transistor PUT includes a first semiconductor layer 210, a first gate dielectric portion 101, a first gate 220, a first source 232, and a first drain 234. The drive transistor DT includes a second semiconductor layer 310, a second gate dielectric portion 102, a second gate 320, a second source 332, and a second drain 334.

In some embodiments, the first semiconductor layer 210 and the second semiconductor layer 310 are formed by the same deposition process and have different thicknesses through an etching process. For example, the patterned semiconductor layer SM includes the first semiconductor layer 210 and the second semiconductor layer 310, wherein the thickness T1 of the first semiconductor layer 210 is greater than the thickness T2 of the second semiconductor layer 310. In some embodiments, the thickness T1 is 20 nm to 100 nm, and the thickness T2 is 10 nm to 100 nm.

In some embodiments, the patterned semiconductor layer SM has a single-layer structure, which includes amorphous silicon, polycrystalline silicon, microcrystalline silicon, single crystal silicon, organic semiconductor materials, oxide semiconductor materials (e.g., indium zinc oxide, indium gallium zinc oxide, or other suitable materials, or a combination of the above materials) or other suitable materials. In some embodiments, the first semiconductor layer 210 and the second semiconductor layer 310 are subjected to a doping process (e.g., an ion implantation process or a hydrogen plasma process), so that the first semiconductor layer 210 and the second semiconductor layer 310 each include regions with different resistivities. For example, when the first semiconductor layer 210 includes a silicon semiconductor, an ion implantation process is performed on the first semiconductor layer 210 to form a source region 202 and a drain region 206 with a lower resistivity, and a channel region 204 with a higher resistivity is located between the source region 202 and the drain region 206. Similarly, when the second semiconductor layer 310 includes a silicon semiconductor, an ion implantation process is performed on the second semiconductor layer 310 to form a source region 302 and a drain region 306 with a lower resistivity, and a channel region 304 with a higher resistivity is located between the source region 302 and the drain region 306. On the other hand, when the first semiconductor layer 210 and the second semiconductor layer 310 include metal oxide semiconductors, a hydrogen plasma process is performed on the first semiconductor layer 210 and the second semiconductor layer 310 to form the source region 202, the drain region 206, the source region 302, and the drain region 306.

In the present embodiment, the bottom surface of the first semiconductor layer 210 and the bottom surface of the second semiconductor layer 310 are located at the same height position based on the top surface 100t of the substrate 100. In the present embodiment, the bottom surface 210b of the first semiconductor layer 210 and the bottom surface 310b of the second semiconductor layer 310 both contact the top surface 100t of the substrate 100, but the present invention is not limited thereto. In other embodiments, a buffer layer (not shown) is disposed between the substrate 100 and the first semiconductor layer 210 and between the substrate 100 and the second semiconductor layer 310, so that the bottom surface 210b of the first semiconductor layer 210 and the bottom surface 310b of the second semiconductor layer 310 both contact the top surface of the buffer layer.

In some embodiments, the first gate dielectric portion 101 and the second gate dielectric portion 102 are formed by the same deposition process and have different thicknesses through an etching process. For example, the patterned insulating layer 110 includes the first gate dielectric portion 101 and the second gate dielectric portion 102, wherein the thickness T4 of the second gate dielectric portion 102 is greater than the thickness T3 of the first gate dielectric portion 101. In some embodiments, the thickness T3 is 10 nm to 300 nm, and the thickness T4 is 20 nm to 350 nm.

In some embodiments, the patterned insulating layer 110 further includes a connecting portion 103. The connecting portion 103 connects the first gate dielectric portion 101 and the second gate dielectric portion 102.

The first gate dielectric portion 101 contacts the top surface 210t of the first semiconductor layer 210. In the present embodiment, a portion of the connection portion 103 extends along the sidewall 210s of the first semiconductor layer 210 to the top surface 210t of the first semiconductor layer 210, and a portion of the connection portion 103 extends along the sidewall 310s of the second semiconductor layer 310 to the top surface 310t of the second semiconductor layer 310. In the present embodiment, the thickness T5 of the connection portion 103 is greater than the thickness T3 of the first gate dielectric portion 101, and the connection portion 103 and the first gate dielectric portion 101 contact the top surface 210t of the first semiconductor layer 210. In other embodiments, the connection portion 103 does not extend to the top surface 210 t of the first semiconductor layer 210 . In other words, the patterned insulating layer 110 on the top surface 210 t of the first semiconductor layer 210 has only the first gate dielectric portion 101 .

The second gate dielectric portion 102 contacts the top surface 310t of the second semiconductor layer 310. In this embodiment, the thickness T4 of the second gate dielectric portion 102 is substantially equal to the thickness T5 of the connecting portion 103, but the present invention is not limited thereto. In other embodiments, the thickness T5 of the connecting portion 103 is different from the thickness T3 of the first gate dielectric portion 101 and the thickness T4 of the second gate dielectric portion 102.

In some embodiments, the patterned insulating layer 110 has a single-layer structure. In some embodiments, the material of the patterned insulating layer 110 includes silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, einsteinium oxide or other suitable materials.

In the present embodiment, based on the top surface 100t of the substrate 100, a height position H1 of a top surface 101t of the first gate dielectric portion 101 is different from a height position H2 of a top surface 102t of the second gate dielectric portion 102.

The first gate 220 and the second gate 320 are located on the patterned insulating layer 110. The first gate 220 contacts the top surface 101t of the first gate dielectric portion 101 and overlaps the channel region 204 of the first semiconductor layer 210. In some embodiments, the width of the first gate dielectric portion 101 is greater than or equal to the width of the first gate 220. The second gate 320 contacts the top surface 102t of the second gate dielectric portion 102 and overlaps the channel region 304 of the second semiconductor layer 310. In some embodiments, the width of the second gate dielectric portion 102 is greater than or equal to the width of the second gate 320.

In some embodiments, the first gate 220 and the second gate 320 each have a single-layer or multi-layer structure. In some embodiments, the materials of the first gate 220 and the second gate 320 include metals such as chromium, gold, silver, copper, tin, lead, cobalt, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, nickel, their alloys, their metal oxides, their metal nitrides, or their combinations or other conductive materials.

The planarization layer 120 is located on the first gate 220, the second gate 320 and the patterned insulating layer 110, and covers the first gate 220 and the second gate 320. In some embodiments, the material of the planarization layer 120 includes an organic insulating material or an inorganic insulating material (such as silicon oxide, silicon nitride, silicon oxynitride or other suitable materials).

The first source 232, the first drain 234, the second source 332 and the second drain 334 are located on the planar layer 120. The first source 232 and the first drain 234 contact the source region 202 and the drain region 206 of the first semiconductor layer 210, respectively, and the second source 332 and the second drain 334 contact the source region 302 and the drain region 306 of the second semiconductor layer 310, respectively.

In some embodiments, the first source 232, the first drain 234, the second source 332, and the second drain 334 each have a single-layer or multi-layer structure. In some embodiments, the materials of the first source 232, the first drain 234, the second source 332, and the second drain 334 include metals such as chromium, gold, silver, copper, tin, lead, cobalt, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, nickel, their alloys, their metal oxides, their metal nitrides, or combinations thereof, or other conductive materials.

2A to 2N are cross-sectional schematic diagrams of a method for manufacturing the active device substrate 10 of FIG1. Referring to FIG2A, a semiconductor material layer SM' is formed on a substrate 100. In some embodiments, a buffer layer (not shown) is further included between the semiconductor material layer SM' and the substrate 100.

Referring to FIG. 2B and FIG. 2C , a photoresist material layer PRM1 is formed on the semiconductor material layer SM’. Then, the photoresist material layer PRM1 is exposed using masks MKa and MKb. Then, the exposed photoresist material layer PRM1 is developed to form a first photoresist pattern layer PR1 on the semiconductor material layer SM’.

In the present embodiment, the method for forming the first photoresist pattern layer PR1 includes a half-tone mask process. Specifically, the mask MKa, MKb includes a first mask area R1, a second mask area R2, and a third mask area R3 with different transmittances. By adjusting the transmittances of the first mask area R1, the second mask area R2, and the third mask area R3, the exposure amount of the photoresist material layer PRM1 is controlled, so that the obtained first photoresist pattern layer PR1 includes different thicknesses. In some embodiments, the mask MKa, MKb shown in FIG. 2B are different masks or different areas on the same mask.

The first photoresist pattern layer PR1 includes a first mask portion PR1a and a second mask portion PR1b. A thickness t1 of the first mask portion PR1a is greater than a thickness t2 of the second mask portion PR1b. In some embodiments, the first mask portion PR1a and the second mask portion PR1b are separated from each other.

Please refer to Figures 2C, 2D and 2E, the first etching process is performed on the semiconductor material layer SM' using the first mask portion PR1a and the second mask portion PR1b as masks to form a semiconductor pattern layer SM.

Since the thickness t1 of the first mask portion PR1a is greater than the thickness t2 of the second mask portion PR1b, the first mask portion PR1a can provide a longer protection for the semiconductor material layer SM' located thereunder in the first etching process. Even if the second mask portion PR1b has been completely removed in the first etching process, a portion of the first mask portion PR1a still remains on the semiconductor material layer SM'. Therefore, the semiconductor pattern layer SM finally formed includes the first semiconductor layer 210 and the second semiconductor layer 310 having different thicknesses. The thickness T1 of the first semiconductor layer 210 corresponding to the first mask portion PR1a is greater than the thickness T2 of the second semiconductor layer 310 corresponding to the second mask portion PR1b.

In some embodiments, after the first etching process, a portion of the first photoresist pattern layer PR1 still remains on the semiconductor pattern layer SM. In this case, an ashing process or other suitable processes can be used to remove the remaining first photoresist pattern layer PR1.

2F , an insulating material layer 110 ′ is formed on the substrate 100 . The insulating material layer 110 ′ covers the first semiconductor layer 210 and the second semiconductor layer 310 .

Referring to FIG. 2G and FIG. 2H , a photoresist material layer PRM2 is formed on the insulating material layer 110 ′. Then, the photoresist material layer PRM2 is exposed using masks MK1 and MK2. Then, the exposed photoresist material layer PRM2 is developed to form a second photoresist pattern layer PR2 on the insulating material layer 110 ′.

In the present embodiment, the masks MK1 and MK2 include a fourth mask region R4 and a fifth mask region R5 with different transmittances. By adjusting the transmittances of the fourth mask region R4 and the fifth mask region R5, the exposure amount of the photoresist material layer PRM2 is controlled, so that the obtained second photoresist pattern layer PR2 includes different thicknesses. In some embodiments, the masks MK1 and MK2 shown in FIG. 2G are different masks or different regions on the same mask. In some embodiments, the method for forming the second photoresist pattern layer PR2 includes a half-tone mask process, and the masks MK1 and MK2 further include other mask regions with different transmittances from the fourth mask region R4 and the fifth mask region R5.

The second photoresist pattern layer PR2 includes a first covering portion PR2a overlapping the first semiconductor layer 210 and a second covering portion PR2b overlapping the second semiconductor layer 310, wherein the thickness t4 of the second covering portion PR2b is greater than the thickness t3 of the first covering portion PR2a. In the present embodiment, the second photoresist pattern layer PR2 further includes a third covering portion PR2c, wherein the third covering portion PR2c connects the first covering portion PR2a and the second covering portion PR2b. In some embodiments, the thickness t5 of the third covering portion PR2c is the same as the thickness t4 of the second covering portion PR2b, but the present invention is not limited thereto. In other embodiments, the thickness t5 of the third covering portion PR2c is different from the thickness t3 and the thickness t4.

2H, 2I and 2J, a second etching process is performed on the insulating material layer 110' using the second photoresist pattern layer PR2 as a mask to form a patterned insulating layer 110.

Since the thickness t4 of the second covering portion PR2b is greater than the thickness t3 of the first covering portion PR2a, the second covering portion PR2b can provide a longer protection for the insulating material layer 110' located thereunder in the second etching process. Even if the first covering portion PR2a has been completely removed in the second etching process, a portion of the second covering portion PR2b still remains on the insulating material layer 110'. Therefore, the patterned insulating layer 110 finally formed includes the first gate dielectric portion 101 and the second gate dielectric portion 102 having different thicknesses. The thickness T4 of the second gate dielectric portion 102 corresponding to the second covering portion PR2b is greater than the thickness T3 of the first gate dielectric portion 101 corresponding to the first covering portion PR2a.

In some embodiments, the thickness t5 of the third covering portion PR2c is also greater than the thickness t3 of the first covering portion PR2a. The third covering portion PR2c can provide a longer protection for the insulating material layer 110' located therebelow during the second etching process. Even if the first covering portion PR2a has been completely removed during the second etching process, a portion of the third covering portion PR2c still remains on the insulating material layer 110'. Therefore, the thickness T5 of the connecting portion 103 corresponding to the third covering portion PR2c is greater than the thickness T3 of the first gate dielectric portion 101 corresponding to the first covering portion PR2a. In some embodiments, the thickness t5 of the third cover portion PR2c is also greater than the thickness t4 of the second cover portion PR2b, and the thickness T5 of the connecting portion 103 is greater than the thickness T4 of the second gate dielectric portion 102.

In some embodiments, after the second etching process, a portion of the second photoresist pattern layer PR2 still remains on the patterned insulating layer 110. In this case, an ashing process or other suitable processes may be used to remove the remaining second photoresist pattern layer PR2.

2K , a first gate 220 and a second gate 320 are formed on the patterned insulating layer 110. The first gate 220 and the second gate 320 are respectively located on the first gate dielectric portion 101 and the second gate dielectric portion 102. In some embodiments, a blanket conductive material layer is first formed on the patterned insulating layer 110, and then the conductive material layer is patterned to form the first gate 220 and the second gate 320.

In some embodiments, after forming the first gate 220 and the second gate 320, a doping process (such as an ion implantation process or a hydrogen plasma process) may be optionally performed on the first semiconductor layer 210 and the second semiconductor layer 310, so that the first semiconductor layer 210 and the second semiconductor layer 310 each include regions with different resistivities. For example, the first semiconductor layer 210 includes a source region 202, a drain region 206, and a channel region 204, and the second semiconductor layer 310 includes a source region 302, a drain region 306, and a channel region 304. In some embodiments, the aforementioned doping process is performed with the first gate 220 and the second gate 320 as masks, so that the channel region 204 and the channel region 304 are respectively aligned with the first gate 220 and the second gate 320. In some embodiments, the aforementioned doping process may be omitted.

2L and 2M , a third photoresist pattern layer PR3 is formed on the patterned insulating layer 110, the first gate 220, and the second gate 320. A third etching process is performed on the patterned insulating layer 110 using the third photoresist pattern layer PR3 as a mask to form a first opening O1 and a second opening O2 located on both sides of the first gate 220 and exposing the first semiconductor layer 210, and a third opening O3 and a fourth opening O4 located on both sides of the second gate 320 and exposing the second semiconductor layer 310 in the patterned insulating layer 110.

2N , a planarization layer 120 is formed on the first gate 220, the second gate 320, and the patterned insulating layer 110. In some embodiments, a first through hole TH1, a second through hole TH2, a third through hole TH3, and a fourth through hole TH4 are formed in the planarization layer 120 by an etching process.

Finally, please return to FIG. 1 to form a first source 232, a first drain 234, a second source 332, and a second drain 334 on the planar layer 120. The first source 232 is filled into the first through hole TH1 and the first opening O1 to be electrically connected to the source region 202 of the first semiconductor layer 210. The first drain 234 is filled into the second through hole TH2 and the second opening O2 to be electrically connected to the drain region 206 of the first semiconductor layer 210. The second source 332 is filled into the third through hole TH3 and the third opening O3 to be electrically connected to the source region 302 of the second semiconductor layer 310. The second drain electrode 334 is filled into the fourth through hole TH4 and the fourth opening O4 to be electrically connected to the drain region 306 of the second semiconductor layer 310 .

In the present embodiment, in the pull-up transistor PUT, the thickness T1 of the first semiconductor layer 210 is thicker and the thickness T3 of the first gate dielectric portion 101 is thinner, and therefore, the pull-up transistor PUT has the advantage of high reliability.

Table 1 shows the output current of thin film transistors with gate dielectric portions of different thicknesses (e.g., the first gate dielectric portion 101 and the second gate dielectric portion 102 in FIG. 1 ). In the thin film transistors of Example 1 and Example 2 in Table 1 , the effective channel width of the semiconductor layer is 160 microns, the effective channel length is 6 microns, and the thickness of the semiconductor layer is 10 nanometers to 100 nanometers. In Table 1 , Vds represents the voltage difference between the source and the drain, the output current represents the current flowing through the semiconductor layer, and Vg represents the voltage on the gate. Table 1 Embodiment 1 Embodiment 2 Gate dielectric thickness ( Angstroms ) 1400 1100 Output current (A) Vds=0.1V Vds=10V Vds=0.1V Vds=10V Vg=0V 1.97E-07 1.73E-06 2.90E-07 2.27E-06 Vg=5V 2.38E-06 8.35E-05 4.11E-06 1.41E-04 Vg=22V 1.02E-05 9.20E-04 2.01E-05 1.84E-03

By comparing the first embodiment and the second embodiment in Table 1, it can be known that when the thickness of the gate dielectric portion is thinner, the output current of the thin film transistor can be effectively improved. For example, when the thickness of the gate dielectric portion is reduced by 20%, the output current can be increased by about 54%, and the actual increase ratio will vary with the material and thickness of the gate dielectric portion. The results in Table 1 can prove that in the embodiment of Figure 1, by reducing the thickness T3 of the first gate dielectric portion 101 of the pull-up transistor PUT, the output current of the pull-up transistor PUT can be effectively improved.

Table 2 shows the critical voltage Vth of thin film transistors with semiconductor layers of different thicknesses (e.g., the first semiconductor layer 210 and the second semiconductor layer 310 in FIG. 1 ) and the output current generated under different gate voltages Vg. In the thin film transistors of Example 3 and Example 4 in Table 2, the material of the semiconductor layer is indium gallium zinc oxide. Table 2 Embodiment 3 Embodiment 4 Semiconductor layer thickness ( angstroms ) 300 450 Vds is 0.1V Vth (V) 0.17 0.18 Output current (A) when Vg is 5V 5.44E-06 5.50E-06 Output current (A) when Vg is 20V 5.85E-06 5.93E-06 Saturated carrier mobility (cm ² /V s) 20.63 20.97

By comparing Example 3 and Example 4 in Table 2, it can be seen that by increasing the thickness of the semiconductor layer, the output current of the thin film transistor can still be maintained at a similar level. For example, when the thickness of the semiconductor layer increases by 60%, the output current can still be maintained at a similar level. Generally speaking, the thicker the semiconductor layer, the smaller the degradation of the semiconductor layer after high voltage operation. Therefore, in the embodiment of Figure 1, by thickening the thickness T1 of the first semiconductor layer 210 of the pull-up transistor PUT, the degradation of the pull-up transistor PUT after high voltage operation can be effectively avoided, thereby improving the reliability of the pull-up transistor PUT.

On the other hand, since the driving transistor DT does not require a high output current, the driving current output by the driving transistor DT can be more accurately controlled by reducing the thickness T2 of the second semiconductor layer 310 and increasing the thickness T4 of the second gate dielectric portion 102.

FIG3A is a circuit diagram of a gate drive circuit GOA according to an embodiment of the present invention. The gate drive circuit GOA includes a first transistor M1, a second transistor M2, a third transistor M3, a pull-up transistor PUT and a first capacitor C1 located on a substrate. In FIG3A , the structure and formation method of the pull-up transistor PUT can refer to FIGS. 1 to 2N and related descriptions thereof, and will not be repeated here. The first transistor M1, the second transistor M2 and the third transistor M3 can be transistors of any type. For example, the first transistor M1, the second transistor M2 and the third transistor M3 each have the same structure as the pull-up transistor PUT in FIG1 or have the same structure as the drive transistor DT in FIG1 .

3A , the first gate of the pull-up transistor PUT (such as the first gate 220 of FIG. 1 ) is electrically connected to the first transistor M1 and the second transistor M2. The first gate of the pull-up transistor PUT, the first transistor M1 and the second transistor M2 are electrically connected to the Q point.

One of the first source and the first drain of the pull-up transistor PUT is connected to the clock signal CK, and the other is connected to the gate output signal S(N) of the gate driving circuit GOA.

One of the source and the drain of the first transistor M1 is electrically connected to the gate of the first transistor M1, and the other is electrically connected to the Q point. The gate of the first transistor M1 is connected to the start signal SP. In this embodiment, the source of the first transistor M1 is electrically connected to the gate of the first transistor M1, but the present invention is not limited thereto. In other embodiments, the source of the first transistor M1 is not connected to the gate of the first transistor M1.

The gate of the second transistor M2 and the gate of the third transistor M3 are connected to the gate output signal S(N+1) of the next-stage gate driving circuit. One of the source and the drain of the second transistor M2 is connected to the first working voltage signal VSS, and the other is electrically connected to the Q point.

One of the source and the drain of the third transistor M3 is connected to the first working voltage signal VSS, and the other is electrically connected to the gate output signal S(N) of the gate driving circuit GOA. One of the first source and the first drain of the pull-up transistor PUT is electrically connected to the third transistor M3.

One end of the first capacitor C1 is electrically connected to the Q point, and the other end of the first capacitor C1 is electrically connected to the gate output signal S(N) of the gate driving circuit GOA.

FIG. 3B is a circuit diagram of a pixel control circuit PC according to an embodiment of the present invention. The pixel control circuit PC includes a switch transistor ST, a drive transistor DT and a second capacitor C2 located on a substrate. The pixel control circuit PC is electrically connected to a gate drive circuit (for example, the gate output signal S(N) of the gate drive circuit GOA of FIG. 3A is transmitted to the pixel control circuit PC via a scan line scan). In FIG. 3B , the structure and formation method of the drive transistor DT can refer to FIG. 1 to FIG. 2N and related descriptions thereof, and will not be repeated here. The switch transistor ST can be any type of transistor. For example, the switch transistor ST has the same structure as the pull-up transistor PUT in FIG. 1 or has the same structure as the drive transistor DT in FIG. 1 .

Referring to FIG3B , the gate of the switch transistor ST is electrically connected to the scan line scan, and is electrically connected to the corresponding gate drive circuit through the scan line scan. One of the source and the drain of the switch transistor ST is electrically connected to the data line data, and the other is electrically connected to the second gate of the drive transistor DT (such as the second gate 320 in FIG1 ).

One of the second source and the second drain (such as the second source 332 and the second drain 334 in FIG. 1 ) of the driving transistor DT is electrically connected to the light emitting element L, and the other is electrically connected to the second working voltage signal VDD.

One end of the light emitting element L is electrically connected to the driving transistor DT, and the other end is electrically connected to the first working voltage signal VSS.

3A and 3B, in some embodiments, the pixel control circuit PC is disposed in the display region of the active device substrate, and the gate drive circuit GOA is disposed in the peripheral region of the active device substrate, wherein the peripheral region is located at least on one side of the display region. In some embodiments, the active device substrate includes a plurality of pixel control circuits PC arrayed in the display region, and a plurality of gate drive circuits GOA are also disposed in the peripheral region of the active device substrate.

FIG. 4 is a cross-sectional schematic diagram of a first transistor, a second transistor, and a third transistor of an active element substrate 10 according to an embodiment of the present invention. Referring to FIG. 1 , FIG. 3A , and FIG. 4 , a first transistor M1, a second transistor M2, and a third transistor M3 are formed. In this embodiment, the formation method of the first transistor M1, the second transistor M2, and the third transistor M3 is the same as that of the pull-up transistor PUT of FIG. 1 to FIG. 2N . The first transistor M1, the second transistor M2, the third transistor M3, and the pull-up transistor PUT each include a first semiconductor layer 210, a first gate dielectric portion 101, a first gate electrode 220, a first source electrode 232, and a first drain electrode 234.

In the present embodiment, the first transistor M1, the second transistor M2, and the third transistor M3 have the same structure as the pull-up transistor PUT, but the present invention is not limited thereto. In other embodiments, the first transistor M1, the second transistor M2, and the third transistor M3 have different structures from the pull-up transistor PUT. For example, one or more of the first transistor M1, the second transistor M2, and the third transistor M3 may have the same structure as the driving transistor DT.

FIG5 is a schematic cross-sectional view of a switch transistor of an active element substrate 10 according to an embodiment of the present invention. Referring to FIG1, FIG3B and FIG5, a switch transistor ST is formed. In this embodiment, the method of forming the switch transistor ST is the same as that of the drive transistor DT of FIG1 to FIG2N. The switch transistor ST and the drive transistor DT each include a second semiconductor layer 310, a second gate dielectric portion 102, a second gate electrode 320, a second source electrode 332 and a second drain electrode 334. .

In this embodiment, the switch transistor ST and the drive transistor DT have the same structure as an example, but the present invention is not limited thereto. In other embodiments, the switch transistor ST and the drive transistor DT have different structures. For example, the switch transistor ST may have the same structure as the pull-up transistor PUT.

FIG6 is a cross-sectional schematic diagram of a pull-up transistor PUTA and a drive transistor DTA of an active element substrate 20 according to another embodiment of the present invention. It must be noted that the embodiment of FIG6 uses the component numbers and partial contents of the embodiments of FIG1 to FIG5, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.

Referring to FIG. 6 , in this embodiment, an interlayer dielectric layer 115 is further included between the patterned insulating layer 110 and the planar layer 120. In this embodiment, the planar layer 120 includes an organic insulating material, and the interlayer dielectric layer 115 includes an inorganic insulating material (e.g., silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, etc.). The interlayer dielectric layer 115 is used to separate the first gate 220 from the planar layer 120 and the second gate 320 from the planar layer 120.

7A to 7G are cross-sectional schematic diagrams of a manufacturing method of a pull-up transistor PUT and a driving transistor DT of an active element substrate 30 according to another embodiment of the present invention. Referring to FIG. 7A and FIG. 7B, following the step of FIG. 2F, a photoresist material layer PRM2 is formed on the insulating material layer 110'. Then, the photoresist material layer PRM2 is exposed using masks MK1 and MK2. Then, a development process is performed on the exposed photoresist material layer PRM2 to form a second photoresist pattern layer PR2 on the insulating material layer 110'.

In the present embodiment, the mask MK1, MK2 includes a fourth mask area R4, a fifth mask area R5, a sixth mask area R6, and a seventh mask area R7 with different transmittances. By adjusting the transmittances of the fourth mask area R4, the fifth mask area R5, the sixth mask area R6, and the seventh mask area R7, the exposure amount of the photoresist material layer PRM2 is controlled, so that the obtained second photoresist pattern layer PR2 includes different thicknesses. In some embodiments, the mask MK1, MK2 shown in FIG. 7A are different masks or different areas on the same mask. In some embodiments, the method for forming the second photoresist pattern layer PR2 includes a half-tone mask process, and the mask MK1, MK2 further includes other mask areas with different transmittances from the fourth mask area R4, the fifth mask area R5, the sixth mask area R6, and the seventh mask area R7.

In this embodiment, the second photoresist pattern layer PR2 includes a first covering portion PR2a and two optional fourth covering regions PR2d overlapping the first semiconductor layer 210. The thickness t6 of the fourth covering region PR2d is less than the thickness t3 of the first covering portion PR2a. In some embodiments, the second photoresist pattern layer PR2 may not include the fourth covering region PR2d and directly expose a portion of the insulating material layer 110'. In other words, the fourth covering region PR2d can be completely removed during the exposure process.

In the present embodiment, the second photoresist pattern layer PR2 further includes a second covering portion PR2b and two fifth covering regions PR2e overlapping the second semiconductor layer 310. The thickness t4 of the second covering portion PR2b is greater than the thickness t3 of the first covering portion PR2a. The thickness t7 of the fifth covering region PR2e is less than the thickness t4 of the second covering portion PR2b. In some embodiments, the thickness t7 of the fifth covering region PR2e is equal to the thickness t6 of the fourth covering region PR2d. In some embodiments, the second photoresist pattern layer PR2 may also not include the fifth covering region PR2e and directly expose a portion of the insulating material layer 110'. In other words, the fifth covering region PR2e can be completely removed during the exposure process.

In the present embodiment, the second photoresist pattern layer PR2 further includes a third covering portion PR2c, wherein the third covering portion PR2c connects the first covering portion PR2a, the second covering portion PR2b, the fourth covering region PR2d, and the fifth covering region PR2e. For example, the shapes of the fourth covering region PR2d and the fifth covering region PR2e vertically projected on the substrate 100 include a circle, an ellipse, or other geometric shapes, wherein the third covering portion PR2c and the first covering portion PR2a surround the fourth covering region PR2d, and the third covering portion PR2c and the second covering portion PR2b surround the fifth covering region PR2e.

In some embodiments, the thickness t5 of the third cover portion PR2c is greater than or equal to the thickness t4 of the second cover portion PR2b.

7C and 7D , a second etching process is performed on the insulating material layer 110′ using the second photoresist pattern layer PR2 as a mask to form a patterned insulating layer 110.

Since the fourth covering region PR2d and the fifth covering region PR2e are the thinnest, the fourth covering region PR2d and the fifth covering region PR2e are removed first in the second etching process, so that the insulating material layer 110' below the fourth covering region PR2d and the fifth covering region PR2e is etched for a longer time in the second etching process, thereby forming the first opening O1 and the second opening O2 exposing the first semiconductor layer 210 and the third opening O3 and the fourth opening O4 exposing the second semiconductor layer 310. In some embodiments, the first opening O1 and the second opening O2 correspond to the positions of the two fourth covering regions PR2d, respectively, and the third opening O3 and the fourth opening O4 correspond to the positions of the two fifth covering regions PR2e, respectively.

In addition, since the thickness t4 of the second covering portion PR2b is greater than the thickness t3 of the first covering portion PR2a, the second covering portion PR2b can provide a longer protection for the insulating material layer 110' thereunder in the second etching process than the first covering portion PR2a. Even if the first covering portion PR2a has been completely removed in the second etching process, a portion of the second covering portion PR2b still remains on the insulating material layer 110'. Therefore, the finally formed patterned insulating layer 110 includes the first gate dielectric portion 101 and the second gate dielectric portion 102 having different thicknesses. The thickness T4 of the second gate dielectric portion 102 corresponding to the second covering portion PR2b is greater than the thickness T3 of the first gate dielectric portion 101 corresponding to the first covering portion PR2a.

In this embodiment, the first opening O1 and the second opening O2 are located at two sides of the first gate dielectric portion 101 , and the third opening O3 and the fourth opening O4 are located at two sides of the second gate dielectric portion 102 .

In some embodiments, the third covering portion PR2c has the thickest thickness t5. Therefore, after the first covering portion PR2a, the second covering portion PR2b, the fourth covering region PR2d and the fifth covering region PR2e are removed, a portion of the third covering portion PR2c still remains on the patterned insulating layer 110, so that the connecting portion 103 corresponding to the third covering portion PR2c has a thicker thickness than the second gate dielectric portion 102.

In some embodiments, after the second etching process, a portion of the second photoresist pattern layer PR2 still remains on the patterned insulating layer 110. In this case, an ashing process or other suitable processes may be used to remove the remaining second photoresist pattern layer PR2.

7E , a first gate 220 and a second gate 320 are formed on the patterned insulating layer 110. The first gate 220 and the second gate 320 are respectively located on the first gate dielectric portion 101 and the second gate dielectric portion 102. In some embodiments, a blanket conductive material layer is first formed on the patterned insulating layer 110, and then the conductive material layer is patterned to form the first gate 220 and the second gate 320.

In some embodiments, after forming the first gate 220 and the second gate 320, a doping process (such as an ion implantation process or a hydrogen plasma process) may be optionally performed on the first semiconductor layer 210 and the second semiconductor layer 310, so that the first semiconductor layer 210 and the second semiconductor layer 310 each include regions with different resistivities. For example, the first semiconductor layer 210 includes a source region 202, a drain region 206, and a channel region 204, and the second semiconductor layer 310 includes a source region 302, a drain region 306, and a channel region 304. In some embodiments, the aforementioned doping process is performed with the first gate 220 and the second gate 320 as masks, so that the channel region 204 and the channel region 304 are respectively aligned with the first gate 220 and the second gate 320. In some embodiments, the aforementioned doping process may be omitted.

7F , a planarization layer 120 is formed on the first gate 220, the second gate 320, and the patterned insulating layer 110. In some embodiments, a first through hole TH1, a second through hole TH2, a third through hole TH3, and a fourth through hole TH4 are formed in the planarization layer 120 by an etching process.

Finally, referring to FIG. 7G , a first source 232, a first drain 234, a second source 332, and a second drain 334 are formed on the planar layer 120. The first source 232 is filled into the first through hole TH1 and the first opening O1 to be electrically connected to the source region 202 of the first semiconductor layer 210. The first drain 234 is filled into the second through hole TH2 and the second opening O2 to be electrically connected to the drain region 206 of the first semiconductor layer 210. The second source 332 is filled into the third through hole TH3 and the third opening O3 to be electrically connected to the source region 302 of the second semiconductor layer 310. The second drain electrode 334 is filled into the fourth through hole TH4 and the fourth opening O4 to be electrically connected to the drain region 306 of the second semiconductor layer 310 .

In this embodiment, in the pull-up transistor PUT, the thickness T1 of the first semiconductor layer 210 is thicker and the thickness T3 of the first gate dielectric portion 101 is thinner, so the pull-up transistor PUT has the advantages of high output current and high reliability. On the other hand, by reducing the thickness T2 of the second semiconductor layer 310 and increasing the thickness T4 of the second gate dielectric portion 102, the driving current output by the driving transistor DT can be more accurately controlled.

FIG8 is a top view schematic diagram of a pull-up transistor and a driving transistor of an active element substrate 10 according to an embodiment of the present invention. It must be noted that the embodiment of FIG8 uses the component numbers and part of the contents of the embodiments of FIG1 to FIG5, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.

Please refer to FIG8 . In this embodiment, the connection portion 103 covers a portion of the top surface of the first semiconductor layer 210, and the first opening O1 and the second opening O2 in the patterned insulating layer 110 pass through the connection portion 103. Similarly, the connection portion 103 covers a portion of the top surface of the second semiconductor layer 310, and the third opening O3 and the fourth opening O4 in the patterned insulating layer 110 pass through the connection portion 103. In this embodiment, the vertical projection shape of the first gate dielectric portion 101 and the second gate dielectric portion 102 on the substrate is a rectangle, but the present invention is not limited thereto. In other embodiments, the vertical projection shape of the first gate dielectric portion 101 and the second gate dielectric portion 102 on the substrate is a circle, an ellipse, or other suitable geometric shapes. In addition, in this embodiment, the connecting portion 103 surrounds the first gate dielectric portion 101 and the second gate dielectric portion 102 .

FIG9 is a top view schematic diagram of a pull-up transistor and a driving transistor of an active element substrate 30 according to another embodiment of the present invention. It must be noted that the embodiment of FIG9 uses the component numbers and part of the contents of the embodiments of FIG1 to FIG5 , wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can refer to the aforementioned embodiments, and will not be repeated here.

9 , in this embodiment, the connection portion 103 does not cover a portion of the top surface of the first semiconductor layer 210, and the first gate dielectric portion 101 covers the top surface and sidewalls of the first semiconductor layer 210. The first opening O1 and the second opening O2 in the patterned insulating layer 110 pass through the first gate dielectric portion 101. Similarly, the connection portion 103 does not cover a portion of the top surface of the second semiconductor layer 310, and the second gate dielectric portion 102 covers the top surface and sidewalls of the second semiconductor layer 310. The third opening O3 and the fourth opening O4 in the patterned insulating layer 110 pass through the second gate dielectric portion 102. In this embodiment, the vertical projection shape of the first gate dielectric portion 101 and the second gate dielectric portion 102 on the substrate is a rectangle, but the present invention is not limited thereto. In other embodiments, the vertical projection shape of the first gate dielectric portion 101 and the second gate dielectric portion 102 on the substrate is a circle, an ellipse or other suitable geometric shapes. In addition, in this embodiment, the connecting portion 103 surrounds the first gate dielectric portion 101 and the second gate dielectric portion 102.

In this embodiment, the thickness of the first semiconductor layer 210 is greater than the thickness of the second semiconductor layer 310. In this embodiment, the thickness of the second gate dielectric portion 102 is greater than the thickness of the first gate dielectric portion 101, and the thickness of the connecting portion 103 is greater than or equal to the thickness of the second gate dielectric portion 102.

In summary, the present invention adjusts the thickness of the first semiconductor layer and the first gate dielectric portion of the pull-up transistor to make the pull-up transistor have a higher reliability. On the other hand, by adjusting the thickness of the second semiconductor layer and the second gate dielectric portion of the drive transistor, the drive current of the drive transistor can be more accurately controlled.

10,20,30: Active element substrate 100: Substrate 100t,101t,102t,210t,310t: Top surface 101: First gate dielectric part 102: Second gate dielectric part 103: Connecting part 110: Patterned insulating layer 110': Insulating material layer 115: Interlayer dielectric layer 120: Flat layer 202: Source region 204: Channel region 206: Drain region 210: First semiconductor layer 210b,310b: Bottom surface 210s,310s: Sidewall 220: First gate 232: First source 234: First drain 302: Source region 304: Channel region 306: Drain region 310: Second semiconductor layer 320: Second gate 332: Second source 334: Second drain C1: First capacitor C2: Second capacitor CK: Clock signal data: Data line DT, DTA: Drive transistor GOA: Gate drive circuit H1, H2: Height position L: Light-emitting element M1: First transistor M2: Second transistor M3: Third transistor MKa, MKb, MK1, MK2: Mask O1: First opening O2: Second opening O3: Third opening O4: Fourth opening PC: Pixel control circuit PR1: first photoresist pattern layer PR2: second photoresist pattern layer PR3: third photoresist pattern layer PR1a: first mask part PR1b: second mask part PR2a: first cover part PR2b: second cover part PR2c: third cover part PR2d: fourth cover part PR2e: fifth cover part PRM1, PRM2: photoresist material layer PUT, PUTA: pull-up transistor R1: first mask area R2: second mask area R3: third mask area R4: fourth mask area R5: fifth mask area scan: scan line S(N), S(N+1): gate output signal SM: patterned semiconductor layer SM’: semiconductor material layer SP: start signal ST: switching transistor T1, T2, T3, T4, T5, t1, t2, t3, t4, t5, t6, t7: thickness TH1: first through hole TH2: second through hole TH3: third through hole TH4: fourth through hole VSS: first operating voltage signal VDD: second operating voltage signal

FIG. 1 is a schematic cross-sectional view of a pull-up transistor and a driving transistor of an active element substrate according to an embodiment of the present invention. FIG. 2A to FIG. 2N are schematic cross-sectional views of a method for manufacturing the active element substrate of FIG. 1 . FIG. 3A is a circuit diagram of a gate driving circuit according to an embodiment of the present invention. FIG. 3B is a circuit diagram of a pixel control circuit according to an embodiment of the present invention. FIG. 4 is a schematic cross-sectional view of a first transistor, a second transistor, and a third transistor of an active element substrate according to an embodiment of the present invention. FIG. 5 is a schematic cross-sectional view of a switch transistor of an active element substrate according to an embodiment of the present invention. FIG. 6 is a schematic cross-sectional view of a pull-up transistor and a driving transistor of an active element substrate according to another embodiment of the present invention. Figures 7A to 7G are cross-sectional schematic diagrams of a method for manufacturing a pull-up transistor and a drive transistor of an active element substrate according to another embodiment of the present invention. Figure 8 is a top view schematic diagram of a pull-up transistor and a drive transistor of an active element substrate according to an embodiment of the present invention. Figure 9 is a top view schematic diagram of a pull-up transistor and a drive transistor of an active element substrate according to another embodiment of the present invention.

10: Active component substrate

100: Substrate

100t,101t,102t,210t,310t: Top surface

101: First gate dielectric part

102: Second gate dielectric part

103: Connection part

110: Patterned insulating layer

120: Flat layer

202: Source region

204: Channel area

206: Drainage area

210: First semiconductor layer

210b,310b: bottom surface

210s,310s: side wall

220: First Gate

232: The First Source

234: First Drain

302: Source area

304: Channel area

306: Drain area

310: Second semiconductor layer

320: Second gate

332: The Second Source

334: Second Drain

DT:Drive transistor

H1,H2: height position

PUT: Pull-up transistor

SM: Patterned semiconductor layer

T1, T2, T3, T4, T5: thickness

Claims (10)

An active element substrate comprises: a substrate; a gate drive circuit comprising: a first transistor, a second transistor and a third transistor, located on the substrate; a pull-up transistor, located on the substrate and comprising: a first semiconductor layer; a first gate dielectric portion, contacting the top surface of the first semiconductor layer; and a first gate, contacting the top surface of the first gate dielectric portion and overlapping the first semiconductor layer, wherein the first gate is electrically connected to the first transistor and the second transistor; and A first source and a first drain contacting the first semiconductor layer, wherein one of the first source and the first drain is electrically connected to the third transistor; and A pixel control circuit electrically connected to the gate drive circuit and comprising: A switch transistor located on the substrate; and A drive transistor located on the substrate and comprising: A second semiconductor layer, wherein a patterned semiconductor layer includes the first semiconductor layer and the second semiconductor layer, and the thickness of the first semiconductor layer is greater than the thickness of the second semiconductor layer; A second gate dielectric portion, contacting the top surface of the second semiconductor layer, wherein a patterned insulating layer includes the first gate dielectric portion and the second gate dielectric portion, and the thickness of the second gate dielectric portion is greater than the thickness of the first gate dielectric portion, wherein based on the top surface of the substrate, the top surface of the first gate dielectric portion and the top surface of the second gate dielectric portion are located at different height positions, and the bottom surface of the first semiconductor layer and the bottom surface of the second semiconductor layer are located at the same height position; A second gate electrode, contacting the top surface of the second gate dielectric portion and overlapping the second semiconductor layer, wherein the second gate electrode is electrically connected to the switch transistor; and A second source and a second drain contact the second semiconductor layer. An active device substrate as described in claim 1, wherein the patterned insulating layer has a single-layer structure. An active device substrate as described in claim 1, wherein the patterned semiconductor layer has a single-layer structure. The active device substrate as described in claim 1, wherein the patterned insulating layer further comprises: A connecting portion connecting the first gate dielectric portion and the second gate dielectric portion, wherein the thickness of the connecting portion is different from the thickness of the first gate dielectric portion and the thickness of the second gate dielectric portion. The active device substrate as described in claim 1, wherein the patterned insulating layer further includes: A connecting portion connecting the first gate dielectric portion and the second gate dielectric portion, wherein the thickness of the connecting portion is greater than the thickness of the first gate dielectric portion, and the connecting portion and the first gate dielectric portion contact the top surface of the first semiconductor layer. A method for manufacturing an active element substrate, comprising: Forming a semiconductor material layer on a substrate; Forming a first photoresist pattern layer on the semiconductor material layer, wherein the first photoresist pattern layer includes a first mask portion and a second mask portion, wherein the thickness of the first mask portion is greater than the thickness of the second mask portion; Performing a first etching process on the semiconductor material layer using the first mask portion and the second mask portion as masks to form a semiconductor pattern layer, wherein the semiconductor pattern layer includes a first semiconductor layer and a second semiconductor layer, and the thickness of the first semiconductor layer is greater than the thickness of the second semiconductor layer; Forming an insulating material layer on the substrate; Forming a second photoresist pattern layer on the insulating material layer, wherein the second photoresist pattern layer includes a first covering portion overlapping the first semiconductor layer and a second covering portion overlapping the second semiconductor layer, wherein the thickness of the second covering portion is greater than the thickness of the first covering portion; Performing a second etching process on the insulating material layer using the second photoresist pattern layer as a mask to form a patterned insulating layer, wherein the patterned insulating layer includes a first gate dielectric portion overlapping the first semiconductor layer and a second gate dielectric portion overlapping the second semiconductor layer, and the thickness of the second gate dielectric portion is greater than the thickness of the first gate dielectric portion; Forming a first gate and a second gate, wherein the first gate and the second gate are respectively located on the first gate dielectric portion and the second gate dielectric portion; Forming a first source and a first drain electrically connected to the first semiconductor layer; and Forming a second source and a second drain electrically connected to the second semiconductor layer. The manufacturing method of the active element substrate as described in claim 6 further includes: forming a first transistor and a second transistor electrically connected to the first gate; forming a third transistor electrically connected to one of the first source and the first drain; and forming a switch transistor electrically connected to the second gate. A method for manufacturing an active element substrate as described in claim 6, wherein the first mask portion and the second mask portion are separated from each other, and the second photoresist pattern layer further includes a third covering portion, wherein the third covering portion connects the first covering portion and the second covering portion. A method for manufacturing an active component substrate as described in claim 6, wherein the second etching process forms a first opening and a second opening in the patterned insulating layer, which are located on both sides of the first gate dielectric portion and expose the first semiconductor layer, and a third opening and a fourth opening, which are located on both sides of the second gate dielectric portion and expose the second semiconductor layer, wherein the first source and the first drain are filled in the first opening and the second opening, respectively, and the second source and the second drain are filled in the third opening and the fourth opening, respectively. The manufacturing method of the active device substrate as described in claim 6 further includes: forming a third photoresist pattern layer above the patterned insulating layer, the first gate and the second gate; and A third etching process is performed on the patterned insulating layer using the third photoresist pattern layer as a mask to form a first opening and a second opening in the patterned insulating layer, which are located on both sides of the first gate and expose the first semiconductor layer, and the third etching process forms a third opening and a fourth opening in the patterned insulating layer, which are located on both sides of the second gate and expose the second semiconductor layer, wherein the first source and the first drain are filled in the first opening and the second opening respectively, and the second source and the second drain are filled in the third opening and the fourth opening respectively.

Images