TWI897585B - Method for measuring critical size of feature pattern - Google Patents

Abstract

The present disclosure provides a method for measuring a critical size of a feature pattern, which includes following steps. A feature pattern is provided, where. A reference pattern is provided, wherein the reference pattern is formed to have a structure topography with a step height. The size of the structure topography is measured at an angle with respect to the normal line of the top surface of the reference pattern, wherein the size of the structure topography is corresponded to the size of the feature pattern.

Description

Method for measuring the critical size of feature patterns

The present invention relates to a method for measuring the critical size of a feature pattern.

In the semiconductor manufacturing process (line), the measurement of critical dimensions of feature patterns can include, for example, in-line measurement and off-line measurement in other processes separate from the line. Generally speaking, in-line measurement is required not to damage the chip/wafer. Therefore, in-line measurement can only be performed from a top-down perspective, and cannot measure the cross-section of the feature pattern by slicing. Doing so will be affected by the shape of the feature pattern, which is narrow at the top and wide at the bottom, making it impossible to measure the precise feature size. Furthermore, although a feature pattern may have a cross-section at its end (such as a line end), in photolithography, the diffraction effect on the feature pattern during the exposure process is more pronounced at the end, causing the feature's dimensions at the end to differ from its actual size. Therefore, researchers in this field continue to improve metrology methods used in production lines.

The present invention provides a method for measuring the critical dimensions of a feature pattern. A reference pattern is placed in an active region and formed into a stepped structural feature. The dimensions of the structural feature are measured at an angle relative to the normal to the top surface of the reference pattern (the dimensions of the structural feature correspond to the dimensions of the feature pattern). This method not only avoids the ends, which are significantly affected by diffraction during photolithography, but also allows for clear observation of the cross-section of the structural feature by tilting the reference pattern at an angle, ensuring that the measured results accurately and faithfully reflect the actual dimensions of the feature pattern.

One embodiment of the present invention provides a method for measuring a critical dimension of a feature pattern, comprising: providing a feature pattern in an active region; providing a reference pattern in the active region, wherein the reference pattern is formed as a structural feature with a stepped height; and measuring the dimension of the structural feature at an angle tilted relative to a normal to a top surface of the reference pattern, wherein the dimension of the structural feature corresponds to the dimension of the feature pattern.

In some embodiments, the angle is about 15° to about 75°.

In some embodiments, the reference pattern includes a portion formed on an isolation structure, the isolation structure defining the active region in a substrate and including a top surface higher than a top surface of the substrate, and the structural feature having a step height extends from the top surface of the isolation structure to the top surface of the substrate.

In some embodiments, the isolation structure extends in a first direction, and the reference pattern extends in a second direction intersecting the first direction.

In some embodiments, the feature pattern comprises a first portion of a polysilicon pattern formed on the substrate, and the reference pattern is formed as a second portion of the polysilicon pattern.

In some embodiments, the feature pattern includes a well implant layer formed in the substrate, and the reference pattern is a portion of a photoresist pattern used to define the well implant layer.

In some embodiments, the reference pattern includes a portion formed on a polysilicon pattern formed on a substrate, and the structural feature having a step height extends from a top surface of the polysilicon pattern to a top surface of the substrate.

In some embodiments, the polysilicon pattern extends in a first direction, and the reference pattern extends in a second direction intersecting the first direction.

In some embodiments, the feature pattern includes a source/drain layer formed in the substrate, and the reference pattern is a portion of a photoresist pattern used to define the source/drain layer.

In some embodiments, the feature pattern includes a conductive contact electrically connected to a source/drain layer formed in the substrate, and the reference pattern is a portion of a conductive layer formed on the polysilicon pattern.

In some embodiments, the reference pattern includes a portion formed on a conductive layer in an interconnect layer, the conductive layer being formed on a dielectric layer in the interconnect layer, and the structural feature having a step height extends from a top surface of the conductive layer to a top surface of the dielectric layer.

In some embodiments, the conductive layer extends in a first direction, and the reference pattern extends in a second direction intersecting the first direction.

In some embodiments, the feature pattern includes a conductive via formed in the interconnect layer, and the reference pattern is a portion of a conductive material layer used to form the conductive via.

In some embodiments, the feature pattern is a conductive layer in an interconnect layer, the conductive layer extends in a first direction, the interconnect layer includes a conductive via below the conductive layer, and the conductive layer is formed above the conductive via to form the structural topography having a stepped height as the reference pattern.

Based on the above, in the aforementioned method for measuring the critical dimensions of a feature, a reference pattern is designed in the active region and formed into a structural feature with stepped heights. This allows the dimensions of the structural feature to be measured at an angle relative to the normal to the top surface of the reference pattern (the size of the structural feature corresponds to the size of the feature). This not only avoids the ends, which are significantly affected by diffraction during the photolithography process, but also allows the cross-section of the structural feature to be clearly observed by tilting the reference pattern at an angle, ensuring that the measured results accurately and truly reflect the actual dimensions of the feature.

100: Base

110: Isolation Structure

120, 130, 150, 170, 180, 190r: Reference pattern

140, 160: Polysilicon pattern

172, 190: Conductive layer

D1: First Direction

D2: Second Direction

FIG1A is a schematic top view of a method for measuring the critical size of a feature pattern according to a first embodiment of the present invention.

Figure 1B is a schematic cross-sectional view taken along line A-A’ of Figure 1A.

Figure 2A is a schematic top view of a method for measuring the critical size of a feature pattern according to a second embodiment of the present invention.

Figure 2B is a schematic cross-sectional view taken along line A-A’ of Figure 2A.

FIG3A is a schematic top view of a method for measuring the critical size of a feature pattern according to a third embodiment of the present invention.

Figure 3B is a schematic cross-sectional view taken along line A-A’ of Figure 3A.

FIG4 is a schematic top view of a method for measuring the critical size of a feature pattern according to a fourth embodiment of the present invention.

FIG5 is a schematic top view of a method for measuring the critical size of a feature pattern according to a fifth embodiment of the present invention.

FIG6 is a schematic top view of a method for measuring the critical size of a feature pattern according to a sixth embodiment of the present invention.

The present invention will be more fully described with reference to the drawings of the present embodiment. However, the present invention may be embodied in various forms and should not be limited to the embodiments described herein. The thickness of layers and regions in the drawings may be exaggerated for clarity. Identical or similar reference numbers denote identical or similar elements, and detailed descriptions will not be repeated in the following paragraphs.

It should be understood that when an element is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element, or intervening elements may be present. When an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements. As used herein, "connected" can refer to physical and/or electrical connections, and "electrically connected" or "coupled" can mean the presence of other elements between two elements. As used herein, "electrically connected" can include both physical connections (e.g., wired connections) and physical disconnections (e.g., wireless connections).

As used herein, "approximately," "substantially," or "approximately" includes the referenced value and the average within an acceptable range of deviation from the specified value as determined by one of ordinary skill in the art, taking into account the measurement in question and the specific amount of error associated with the measurement (i.e., the limitations of the measurement system). For example, "approximately" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, or ±5%. Furthermore, as used herein, "approximately," "substantially," or "approximately" may be used to select a more acceptable range of deviation or standard deviation depending on the optical, etching, or other properties, rather than applying a single standard deviation to all properties.

The terms used herein are intended to describe exemplary embodiments only and are not intended to limit the present disclosure. In this context, the singular includes the plural unless the context otherwise requires.

FIG1A is a schematic top view of a method for measuring a critical dimension of a feature pattern according to a first embodiment of the present invention. FIG1B is a schematic cross-sectional view taken along line A-A' of FIG1A .

Referring to Figures 1A and 1B , a method for measuring a critical dimension of a feature pattern may include: providing a feature pattern in an active region; providing a reference pattern (e.g., reference pattern 120 shown in Figures 1A and 1B ) in the active region, wherein the reference pattern is formed as a structural feature with a step height; and measuring a dimension of the structural feature at an angle relative to a normal to a top surface of the reference pattern, wherein the dimension of the structural feature corresponds to a dimension of the feature pattern. In some embodiments, the angle may be approximately 15° to approximately 75°. For example, the angle may be approximately 45°.

Because the reference pattern is designed in the active area and forms a stepped structure, the dimensions of the structure can be measured at an angle relative to the normal to the top of the reference pattern (the size of the structure corresponds to the size of the feature pattern). This not only avoids the ends that are significantly affected by diffraction during the photolithography process, but also allows the cross-section of the structure to be clearly observed by tilting the angle, ensuring that the measured results accurately and truly reflect the actual size of the feature pattern.

In this embodiment, the active region may be defined by an isolation structure 110 formed in a substrate 100. In some embodiments, the substrate 100 may include a semiconductor substrate or a semiconductor-on-insulator (SOI) substrate. The semiconductor material in the semiconductor substrate or SOI substrate may include elemental semiconductors, alloy semiconductors, or compound semiconductors. For example, elemental semiconductors may include Si or Ge. Alloy semiconductors may include SiGe, SiGeC, etc. Compound semiconductors may include SiC, Group III-V semiconductor materials, or Group II-VI semiconductor materials. The III-V semiconductor materials may include GaN, GaP, GaAs, AlN, AlP, AlAs, InN, InP, InAs, GaNPs, GaNAs, GaPAs, AlNPs, AlNAs, AlPAs, InNPs, InNAs, InPAs, GaAlNPs, GaAlNAs, GaAlPAs, GaInNPs, GaInNAs, GaInPAs, InAlNPs, InAlNAs or InAlPAs. Group II-VI semiconductor materials may include CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, HgS, HgSe, HgTe, CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdZnS e. CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe or HgZnSTe. The semiconductor material may be doped with a dopant of a first conductivity type or a dopant of a second conductivity type complementary to the first conductivity type. For example, the first conductivity type may be P-type, and the second conductivity type may be N-type. The isolation structure 110 may include a material suitable for an isolation structure, such as silicon oxide. In some embodiments, the isolation structure 110 may be a shallow trench isolation (STI) structure.

In this embodiment, as shown in Figures 1A and 1B, the reference pattern 120 may include a portion formed on the isolation structure 110, wherein the isolation structure 110 may define the active area in the substrate 100 and include a top surface higher than the top surface of the substrate 100. The stepped structural features of the reference pattern 120 may extend from the top surface of the isolation structure 110 to the top surface of the substrate 100. In this embodiment, the isolation structure 110 may extend in a first direction D1, and the reference pattern 120 may extend in a second direction D2 that intersects the first direction D1. In some embodiments, the first direction D1 may be perpendicular to the second direction D2.

In this embodiment, the feature pattern may comprise a first portion of a polysilicon pattern formed on substrate 100, while reference pattern 120 may be formed as a second portion of the polysilicon pattern. In other words, reference pattern 120 may be formed of polysilicon. In this embodiment, the polysilicon pattern may correspond to a gate pattern of a metal oxide semiconductor field effect transistor (MOSFET). In other words, this embodiment can measure the dimensions of a structural feature (which may correspond to the dimensions of the gate pattern) by tilting the surface at an angle relative to the normal to the top surface of the reference pattern 120. This not only avoids the ends, which are significantly affected by diffraction during the photolithography process, but also allows for clear observation of the cross-section of the structural feature, ensuring that the measured results accurately and faithfully reflect the actual dimensions of the gate pattern.

For the sake of brevity, this embodiment omits further detailed description of the shape, structure, and/or position of the feature pattern (in this embodiment, the first portion of the polysilicon pattern). Various polysilicon pattern shapes, structures, and/or positions used to form the gate of a MOSFET are applicable to this embodiment, as long as the feature pattern and reference pattern 120 are formed using the same layout. In other words, if the patentable features of this embodiment are only relevant to the reference pattern, for example, the feature pattern may be omitted from the drawings.

Figure 2A is a schematic top view of a method for measuring the critical dimension of a feature pattern according to a second embodiment of the present invention. Figure 2B is a schematic cross-sectional view taken along line A-A' in Figure 2A . The second embodiment shown in Figures 2A and 2B is substantially similar to the first embodiment shown in Figures 1A and 1B , differing only in that the reference pattern 130 and its corresponding feature pattern in the second embodiment are different from the reference pattern 120 and its corresponding feature pattern in the first embodiment. The following description will omit the portions identical to those of the first embodiment.

Referring to Figures 2A and 2B , a method for measuring a critical dimension of a feature pattern may include: providing a feature pattern in an active region; providing a reference pattern (e.g., reference pattern 130 shown in Figures 2A and 2B ) in the active region, wherein the reference pattern is formed as a structural feature with a step height; and measuring a dimension of the structural feature at an angle tilted relative to a normal to a top surface of the reference pattern, wherein the dimension of the structural feature corresponds to a dimension of the feature pattern.

As shown in Figures 2A and 2B, reference pattern 130 may include a portion formed on isolation structure 110. Isolation structure 110 may define the active region in substrate 100 and include a top surface higher than the top surface of substrate 100. The structural features having a step height extend from the top surface of isolation structure 110 to the top surface of substrate 100. In this embodiment, the feature pattern may include a well implant layer formed in substrate 100, and reference pattern 130 may be a portion of a photoresist pattern used to define the well implant layer. In other words, reference pattern 130 may be formed of photoresist. In this embodiment, the photoresist pattern may be a mask pattern used to form a well implant layer (e.g., a well region of the first conductivity type or the second conductivity type formed in substrate 100) for forming a MOSFET. In other words, this embodiment can measure the dimensions of the structural features (the dimensions of the structural features corresponding to the dimensions of the well implant layer) by tilting the surface at an angle relative to the normal to the top surface of the reference pattern 130. This not only avoids the ends that are significantly affected by diffraction during the photolithography process, but also allows for clear observation of the cross-section of the structural features by tilting the surface at an angle, ensuring that the measured results accurately and truly reflect the actual dimensions of the well implant layer.

For the sake of brevity, this embodiment omits further detailed description of the shape, structure, and/or location of the feature pattern (in this embodiment, the well implant layer formed in substrate 100). Various shapes, structures, and/or locations of well implant layers used to form MOSFETs are applicable to this embodiment, as long as the feature pattern is formed using the same layout as the photoresist pattern including reference pattern 130. In other words, if the patentable features of this embodiment are only related to the reference pattern, for example, the feature pattern may be omitted from the drawings.

Figure 3A is a schematic top view of a method for measuring critical dimensions of a feature pattern according to a third embodiment of the present invention. Figure 3B is a schematic cross-sectional view taken along line A-A' in Figure 3A. The third embodiment shown in Figures 3A and 3B is substantially similar to the first embodiment shown in Figures 1A and 1B, differing only in that reference pattern 150 and its corresponding feature pattern in the third embodiment differ from reference pattern 120 and its corresponding feature pattern in the first embodiment. The following description will omit the portions identical to those of the first embodiment.

Referring to FIG. 3A and FIG. 3B , a method for measuring a critical dimension of a feature pattern may include: providing a feature pattern in an active region; providing a reference pattern (e.g., reference pattern 150 shown in FIG. 3A and FIG. 3B ) in the active region, wherein the reference pattern is formed as a structural feature having a step height; and measuring a dimension of the structural feature at an angle tilted relative to a normal to a top surface of the reference pattern, wherein the dimension of the structural feature corresponds to a dimension of the feature pattern.

As shown in Figures 3A and 3B, the reference pattern 150 may include a portion formed on the polysilicon pattern 140, wherein the polysilicon pattern 140 may be formed on the substrate 100, and the structural features having the step height may extend from the top surface of the polysilicon pattern 140 to the top surface of the substrate 100. In this embodiment, the polysilicon pattern 140 may be located at the same level as the gate pattern forming the MOSFET or may be part of the gate pattern. In this embodiment, the polysilicon pattern 140 may extend in a first direction D1, and the reference pattern 150 may extend in a second direction D2 that intersects the first direction D1. The feature pattern may include a source/drain layer formed in substrate 100, and reference pattern 150 may be a portion of a photoresist pattern used to define the source/drain layer. In other words, reference pattern 150 may be formed from photoresist. In this embodiment, the photoresist pattern may be a mask pattern used to form the source/drain layer of a MOSFET (e.g., formed in substrate 100 and having source/drain regions of the first conductivity type or the second conductivity type and/or lightly doped regions). In other words, this embodiment can measure the dimensions of the structural features (the dimensions of the structural features corresponding to the dimensions of the source/drain layers) by tilting the surface at an angle relative to the normal to the top surface of the reference pattern 150. This not only avoids the ends that are significantly affected by diffraction during the photolithography process, but also allows for clear observation of the cross-section of the structural features by tilting the surface at an angle, ensuring that the measured results accurately and truly reflect the actual dimensions of the source/drain layers.

For the sake of brevity, this embodiment omits further detailed description of the shape, structure, and/or location of the feature pattern (in this embodiment, the source/drain layer formed in substrate 100). Various shapes, structures, and/or locations of source/drain layers used to form MOSFETs are applicable to this embodiment, as long as the feature pattern is formed using the same photoresist pattern as reference pattern 150 in the same layout. In other words, if the patentable features of this embodiment are only related to the reference pattern, for example, the feature pattern may be omitted from the drawings.

Figure 4 is a schematic top view of a method for measuring the critical dimensions of a feature pattern according to a fourth embodiment of the present invention. The fourth embodiment shown in Figure 4 is substantially similar to the first embodiment shown in Figures 1A and 1B , differing only in that reference pattern 170 and its corresponding feature pattern in the fourth embodiment are different from reference pattern 120 and its corresponding feature pattern in the first embodiment. The following description will omit the parts identical to those in the first embodiment.

Referring to FIG. 4 , a method for measuring a critical dimension of a feature pattern may include: providing a feature pattern in an active region; providing a reference pattern (e.g., reference pattern 170 shown in FIG. 4 ) in the active region, wherein the reference pattern is formed as a structural feature with a step height; and measuring a dimension of the structural feature at an angle tilted relative to a normal to a top surface of the reference pattern, wherein the dimension of the structural feature corresponds to a dimension of the feature pattern.

As shown in FIG4 , the reference pattern 170 may include a portion formed on the polysilicon pattern 160, wherein the polysilicon pattern 160 may be formed on the substrate 100, and the structural features having step heights may extend from the top surface of the polysilicon pattern 160 to above the top surface of the substrate 100 (in this embodiment, the structural features having step heights of the reference pattern 170 may extend from the top surface of the polysilicon pattern 160 to the top surface of the dielectric layer described below). In this embodiment, the polysilicon pattern 160 may be, for example, located at the same level as a gate pattern forming a MOSFET or may be part of the gate pattern. In this embodiment, the polysilicon pattern 160 may extend in a first direction D1, while the reference pattern 170 may extend in a second direction D2 that intersects the first direction D1. The feature pattern may include conductive contacts electrically connected to a source/drain layer formed in substrate 100, and reference pattern 170 may be part of a conductive layer formed on polysilicon pattern 160. In other words, reference pattern 170 may be formed of a conductive material. In some embodiments, the conductive material may include a metal or a metal nitride. For example, the metal may include aluminum (Al) or tungsten (W). The metal nitride may include WN, TiSiN, WSiN, TiN, TaN, or combinations thereof.

In this embodiment, reference pattern 170 may be a portion of a conductive layer used to form conductive contacts electrically connected to the source/drain layers of a MOSFET. For example, after forming the MOSFET, a dielectric layer (ILD0) is formed on substrate 100 to cover the MOSFET. A hole is formed in the dielectric layer to expose the source/drain layers of the MOSFET. A conductive layer is then formed on the dielectric layer, where the conductive layer fills the hole to form a conductive contact electrically connected to the source/drain layers of the MOSFET. Reference pattern 170 is a portion of the conductive layer formed on the dielectric layer. That is, in this embodiment, the step-height structure of the reference pattern 170 extends from the top surface of the polysilicon pattern 160 to the top surface of the dielectric layer. In some embodiments, the dielectric layer (ILD0) may be a suitable dielectric material such as oxide.

This embodiment can measure the dimensions of a structural feature (corresponding to the dimensions of the conductive contact) by tilting the surface at an angle relative to the normal to the top surface of reference pattern 170. This not only avoids the ends, which are significantly affected by diffraction during the photolithography process, but also allows for clear observation of the cross-section of the structural feature by tilting the surface at an angle, ensuring that the measured results accurately and truly reflect the actual dimensions of the conductive contact.

For the sake of brevity, this embodiment omits further detailed description of the shape, structure, and/or location of the feature pattern (in this embodiment, the conductive contact electrically connected to the source/drain layer formed in the substrate 100). Various shapes, structures, and/or locations of the conductive contacts electrically connected to the source/drain layer of the MOSFET are applicable to this embodiment, as long as the feature pattern and the reference pattern 170 are formed using the same layout. In other words, if a patentable feature of this embodiment is only relevant to the reference pattern, for example, the feature pattern may be omitted from the drawings.

Figure 5 is a schematic top view of a method for measuring the critical dimensions of a feature pattern according to a fifth embodiment of the present invention. The fifth embodiment shown in Figure 5 is substantially similar to the fourth embodiment shown in Figure 4 , differing only in that reference pattern 180 and its corresponding feature pattern in the fifth embodiment are different from reference pattern 170 and its corresponding feature pattern in the fourth embodiment. The following description will omit the parts identical to those in the fourth embodiment.

Referring to FIG. 5 , a method for measuring a critical dimension of a feature pattern may include: providing a feature pattern in an active region; providing a reference pattern (e.g., reference pattern 180 shown in FIG. 4 ) in the active region, wherein the reference pattern is formed as a structural feature having a step height; and measuring a dimension of the structural feature at an angle tilted relative to a normal to a top surface of the reference pattern, wherein the dimension of the structural feature corresponds to a dimension of the feature pattern.

As shown in FIG5 , reference pattern 180 may include a portion of a conductive layer 172 formed in an interconnect layer. Conductive layer 172 may be formed on a dielectric layer (e.g., ILD1 or ILDn) in the interconnect layer, and the step-height structure may extend from the top surface of conductive layer 172 to the top surface of the dielectric layer. In this embodiment, conductive layer 172 may extend in a first direction D1, and reference pattern 180 may extend in a second direction D2 that intersects first direction D1. In some embodiments, conductive layer 172 may include a conductive material such as a metal or a metal nitride. For example, the metal may include a metallic material such as aluminum (Al) or tungsten (W). The metal nitride may include metal nitrides such as WN, TiSiN, WSiN, TiN, TaN, or combinations thereof.

The interconnect layer may, for example, be formed at a level above the MOSFET. For example, the interconnect layer may be formed on a dielectric layer (ILD0) having conductive contacts electrically connected to the source/drain layers of the MOSFET. In this embodiment, the feature pattern may include conductive vias in the interconnect layer, and reference pattern 180 may be a portion of a conductive material layer used to form the conductive vias. In other words, reference pattern 180 may be formed of a conductive material. In some embodiments, the conductive material may include a conductive material such as a metal or a metal nitride. For example, the metal may include aluminum (Al) or tungsten (W). The metal nitride may include a metal nitride such as WN, TiSiN, WSiN, TiN, TaN, or a combination thereof.

In this embodiment, reference pattern 180 may be a portion of a conductive material layer used to form a conductive via electrically connected to conductive layer 172. For example, during the step of forming the interconnect layer, a dielectric layer may be formed covering conductive layer 172, and a via hole exposing conductive layer 172 may be formed in the dielectric layer. Subsequently, a conductive material layer may be formed on the dielectric layer, where the conductive material layer fills the via hole to form a conductive via electrically connected to conductive layer 172. Reference pattern 180 is a portion of the conductive material layer formed on the dielectric layer. That is, in this embodiment, the structure with a stepped height of the reference pattern 180 may extend from the top surface of the conductive layer 172 to the top surface of the dielectric layer.

This embodiment can measure the dimensions of a structural feature (corresponding to the dimensions of a conductive via) by tilting the surface at an angle relative to the normal to the top surface of reference pattern 180. This not only avoids the ends, which are significantly affected by diffraction during the photolithography process, but also allows for clear observation of the cross-section of the structural feature by tilting the surface at an angle, ensuring that the measured results accurately and truly reflect the actual dimensions of the conductive via.

For the sake of brevity, this embodiment omits further detailed description of the shape, structure, and/or location of the feature pattern (in this embodiment, the conductive via formed in the interconnect layer). Various shapes, structures, and/or locations for forming the conductive via in the interconnect layer are applicable to this embodiment, as long as the feature pattern and reference pattern 180 are formed using the same layout. In other words, if a patentable feature of this embodiment is only relevant to the reference pattern, for example, the feature pattern may be omitted from the drawings.

Figure 6 is a schematic top view of a method for measuring the critical dimensions of a feature pattern according to a sixth embodiment of the present invention. The sixth embodiment shown in Figure 6 is substantially similar to the fifth embodiment shown in Figure 5 , differing only in that reference pattern 190r and its corresponding feature pattern in the sixth embodiment are different from reference pattern 180 and its corresponding feature pattern in the fifth embodiment. The following description will omit the portions identical to those of the fourth embodiment.

Referring to FIG. 5 , the characteristic pattern is a conductive layer 190 in an interconnect layer. Conductive layer 190 extends in a first direction D1, includes a conductive via below conductive layer 190, and has a stepped structural topography, referred to as reference pattern 190r, formed above the conductive via. In this embodiment, if conductive layer 190 has a relatively large width (e.g., a width in a second direction D2), the conductive material layer filled into the via hole may not completely fill the via hole, forming a recess above the conductive via. This recess, due to its stepped structural topography, serves as reference pattern 190r. In other words, this embodiment can measure the dimensions of a structural feature (the dimensions of the structural feature corresponding to the dimensions of the conductive layer 190 in the second direction D2) by tilting the surface at an angle relative to the normal to the top surface of reference pattern 190r. This not only avoids the ends that are significantly affected by diffraction during photolithography, but also allows for clear observation of the cross-section of the structural feature, ensuring that the measured results accurately and faithfully reflect the actual dimensions of the conductive layer 190. In some embodiments, the conductive layer 190 may comprise a conductive material such as a metal or metal nitride. For example, the metal may include aluminum (Al) or tungsten (W). The metal nitride may include metal nitrides such as WN, TiSiN, WSiN, TiN, TaN, or combinations thereof.

In summary, in the method for measuring the critical dimensions of a feature pattern described in the above embodiment, a reference pattern is designed in the active region and formed into a stepped structural feature. This allows the dimensions of the structural feature to be measured at an angle relative to the normal to the top surface of the reference pattern (the size of the structural feature corresponds to the size of the feature pattern). This not only avoids the ends, which are significantly affected by diffraction during the photolithography process, but also allows the cross-section of the structural feature to be clearly observed by tilting the reference pattern at an angle, ensuring that the measured results accurately and truly reflect the actual dimensions of the feature pattern.

100: Base

110: Isolation Structure

120: Reference pattern

Claims (14)

A method for measuring a critical size of a feature pattern comprises: providing a feature pattern in an active area; providing a reference pattern in the active area, wherein the reference pattern is formed as a structural topography having a stepped height; and measuring the size of the structural topography at an angle tilted relative to a normal to a top surface of the reference pattern, wherein the size of the structural topography corresponds to the size of the feature pattern, wherein the feature pattern and the reference pattern are formed under the same layout. The method of claim 1 , wherein the angle is from about 15° to about 75°. A method as described in claim 1, wherein the reference pattern includes a portion formed on an isolation structure, the isolation structure defining the active area in the substrate and including a top surface higher than the top surface of the substrate, and the structural morphology having a step height extends from the top surface of the isolation structure to the top surface of the substrate. A method as described in claim 3, wherein the isolation structure extends in a first direction and the reference pattern extends in a second direction intersecting the first direction. The method of claim 4, wherein the feature pattern comprises a first portion of a polysilicon pattern formed on the substrate, and the reference pattern is formed as a second portion of the polysilicon pattern. The method of claim 4, wherein the feature pattern comprises a well implant layer formed in the substrate, and the reference pattern is a portion of a photoresist pattern used to define the well implant layer. The method of claim 1, wherein the reference pattern includes a portion formed on a polysilicon pattern, the polysilicon pattern is formed on a substrate, and the structural morphology having a step height extends from a top surface of the polysilicon pattern to a top surface of the substrate. The method of claim 7, wherein the polysilicon pattern extends in a first direction and the reference pattern extends in a second direction intersecting the first direction. The method of claim 8, wherein the feature pattern comprises a source/drain layer formed in the substrate, and the reference pattern is a portion of a photoresist pattern used to define the source/drain layer. The method of claim 8, wherein the feature pattern comprises a conductive contact electrically connected to a source/drain layer formed in the substrate, and the reference pattern is a portion of a conductive layer formed on the polysilicon pattern. The method of claim 1, wherein the reference pattern comprises a portion formed on a conductive layer in an interconnect layer, the conductive layer being formed on a dielectric layer in the interconnect layer, and the structural feature having a step height extends from a top surface of the conductive layer to a top surface of the dielectric layer. The method of claim 11, wherein the conductive layer extends in a first direction and the reference pattern extends in a second direction intersecting the first direction. The method of claim 12, wherein the feature pattern comprises a conductive via formed in the interconnect layer, and the reference pattern is a portion of a conductive material layer used to form the conductive via. A method as described in claim 1, wherein the feature pattern is a conductive layer in an interconnect layer, the conductive layer extends in a first direction, the interconnect layer includes a conductive via below the conductive layer, and the conductive layer is formed at a position above the conductive via into the structural morphology having a step height of the reference pattern.