TWI870249B - Method for forming semiconductor device - Google Patents

Abstract

The present disclosure provides a method for forming a semiconductor device, which includes following steps. A bit line material layer is formed on a substrate including a cell region and pick-up regions adjacent to the cell region at opposite sides of the cell region in a horizontal direction. The bit line material layer includes a body portion and extension portions extending in the horizontal direction from the body portion and arranged in a vertical direction. The bit line material layer is patterned to form bit lines extending in the horizontal direction and arranged in the vertical direction. Each bit line includes a line pattern and a landing pad pattern connecting to one end of the line pattern.

Description

Method for forming semiconductor device

The present invention relates to a method of forming a semiconductor device, and more particularly to a method of forming a semiconductor memory device.

As the size of electronic devices continues to shrink and users' requirements for the performance of electronic devices continue to increase, how to make electronic devices include more components while maintaining the existing horizontal area, or how to make them have a small horizontal area while maintaining the existing number of components, has become one of the goals that technicians in this field are eager to work on. However, the above situations will reduce the spacing between wires (such as the spacing between bit lines), making the conductive contacts that directly contact the wires (such as bit line contacts) more stringent in terms of critical dimension (CD) and overlay requirements, resulting in insufficient process margin.

The present invention provides a method for forming a semiconductor device, wherein a bit line is formed to include a line pattern and a landing pad pattern connected to one end of the line pattern, so that a bit line contact can be formed on the landing pad pattern having an area and a pitch larger than that of the line pattern, thereby improving the process margin of the bit line contact.

An embodiment of the present invention provides a method for forming a semiconductor device, comprising: forming a bit line material layer on a substrate, the substrate comprising a cell region and a pickup region adjacent to the cell region and located at an opposite side of the cell region in a horizontal direction, wherein the bit line material layer comprises a main body portion and a plurality of extension portions extending from the main body portion in a horizontal direction and arranged in a vertical direction; and patterning the bit line material layer to form a plurality of bit lines extending in a horizontal direction and arranged in a vertical direction. Each bit line comprises a line pattern and a landing pad pattern connected to one end of the line pattern.

In some embodiments, the landing pad pattern and the other end of the line pattern are alternately arranged in the vertical direction.

In some embodiments, each landing pad pattern includes a first surface connected to the line pattern and a second surface horizontally opposite to the first surface, wherein the profile of the second surface is different from the profile of the first surface.

In some embodiments, the second surface has a circular profile.

In some embodiments, each landing pad pattern includes a third surface and a fourth surface that are opposite to each other in a vertical direction, and a profile of the third surface is the same as a profile of the fourth surface.

In some embodiments, the angle between the first surface and the third surface or the fourth surface includes a blunt angle, a sharp angle, or a right angle.

In some embodiments, patterning the bit line material layer includes: forming a plurality of first mask patterns extending in a horizontal direction and arranged in a vertical direction on the bit line material layer; forming spacers on side walls of each of the first mask patterns, wherein each of the spacers includes an annular pattern, the annular pattern includes a plurality of line portions and a plurality of curved portions connecting ends of the line portions; removing the plurality of first mask patterns; forming a second mask pattern covering the curved portions of the spacers on the bit line material layer, wherein the second mask pattern exposes a main portion of the bit line material layer and a portion of each of the extending portions; and removing a portion of the bit line material layer exposed by the spacers and the second mask pattern to form a plurality of bit lines.

In some embodiments, the plurality of extensions include a plurality of first extensions formed on a first side of the main body and a plurality of second extensions formed on a second side of the main body opposite to the first side, and each first mask pattern covers one of the plurality of first extensions and one of the plurality of second extensions.

In some embodiments, the method of forming a semiconductor device further includes: removing the spacer and the second mask pattern after forming a plurality of bit lines; and forming a plurality of conductive contacts arranged in a horizontal direction between two adjacent bit lines.

In some embodiments, the method of forming a semiconductor device further includes: forming a bit line contact overlapping the landing pad pattern on each landing pad pattern, wherein the bit line contact is spaced apart from the outermost conductive contact in a horizontal direction.

Based on the above, in the above method of forming a semiconductor device, the bit line is formed to include a line pattern and a landing pad pattern connected to one end of the line pattern, so that the bit line contact can be formed on the landing pad pattern whose area and pitch are larger than the line pattern, thereby improving the process margin of the bit line contact.

The present invention is more fully described with reference to the drawings of the present embodiment. However, the present invention may be embodied in various forms and should not be limited to the embodiments described herein. The thickness of layers and regions in the drawings are exaggerated for clarity. The same or similar reference numbers represent the same or similar elements, and the following paragraphs will not be repeated one by one.

It should be understood that when an element is referred to as being "on" or "connected to" another element, it may be directly on or connected to another element, or there may be an intermediate element. If an element is referred to as being "directly on" or "directly connected to" another element, there are no intermediate elements. As used herein, "connection" may refer to physical and/or electrical connection, and "electrical connection" or "coupling" may be the presence of other elements between two elements. As used herein, "electrical connection" may include physical connection (e.g., wired connection) and physical disconnection (e.g., wireless connection).

As used herein, "about", "approximately" or "substantially" includes the referenced value and the average value within an acceptable deviation range of a specific value that can be determined by a person of ordinary skill in the art, taking into account the measurement in question and the specific amount of error associated with the measurement (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, as used herein, "about", "approximately" or "substantially" can select a more acceptable deviation range or standard deviation depending on the optical properties, etching properties or other properties, and can apply to all properties without a single standard deviation.

The terms used herein are used to describe exemplary embodiments only, rather than to limit the present disclosure. In this case, unless otherwise explained in the context, the singular form includes the plural form.

1A to 1H are schematic top views of a method for forming a semiconductor device according to an embodiment of the present invention. FIG. 2 is a schematic top view of a landing pad pattern of FIG. 1H. FIG. 3 is a schematic top view of a landing pad pattern according to another embodiment of the present invention. FIG. 4 is a schematic top view of a landing pad pattern according to yet another embodiment of the present invention. FIG. 5 is a schematic top view of a semiconductor device according to an embodiment of the present invention.

First, referring to FIG. 1A , a bit line material layer 102 is formed on a substrate. The substrate may include a cell region (e.g., the cell region R1 shown in FIG. 1G ) and a pickup region (e.g., the pickup region R2 shown in FIG. 1G ) adjacent to the cell region and located at an opposite side of the cell region in a horizontal direction D1. The bit line material layer 102 includes a main body 102a and a plurality of extensions 102b extending from the main body 102a in a horizontal direction D1 and arranged in a vertical direction D2.

The substrate may include a semiconductor substrate, a semiconductor on insulator (SOI) substrate, and/or a component layer and an interconnect layer formed on the semiconductor substrate or SOI substrate. The semiconductor material in the semiconductor substrate or SOI substrate may include an elemental semiconductor, an alloy semiconductor, or a compound semiconductor. For example, the elemental semiconductor may include Si or Ge. The alloy semiconductor may include SiGe, SiGeC, etc. The compound semiconductor may include SiC, a III-V semiconductor material, or a II-VI semiconductor material. Group III-V semiconductor materials may include GaN, GaP, GaAs, AlN, AlP, AlAs, InN, InP, InAs, GaNPs, GaNAs, GaPAs, AlNPs, AlNAs, AlPAs, InNPs, InNAs, InPAs, GaAlNPs, GaAlNAs, GaAlPAs, GaInNPs, GaInNAs, GaInPAs, InAlNPs, InAlNAs or InAlPAs. Group II-VI semiconductor materials may include CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, HgS, HgSe, HgTe, CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdZnS e. CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe or HgZnSTe. The semiconductor material may be doped with a first conductivity type dopant or a second conductivity type dopant complementary to the first conductivity type. For example, the first conductivity type may be P type and the second conductivity type may be N type.

The component layer may include active components such as metal oxide semiconductor field effect transistors (MOSFET), passive components such as resistors, inductors or capacitors, or a combination thereof. The interconnect layer may include a dielectric layer formed by a front-end-of-line (FEOL) and/or a back-end-of-line (BEOL) process and/or a conductor layer and/or conductive vias buried therein. The dielectric layer may include a dielectric material such as an oxide (e.g., silicon oxide) or a nitride (e.g., silicon nitride). The conductor layer and the conductive via may each include a conductive material such as a metal or a metal alloy. The metal and the metal alloy may be, for example, Cu, Al, Ti, Ta, W, Pt, Cr, Mo or an alloy thereof.

The bit line material layer 102 may include a conductive material such as a metal or a metal alloy. The metal or metal alloy may be, for example, Cu, Al, Ti, Ta, W, Pt, Cr, Mo or alloys thereof.

Then, the bit line material layer 102 is patterned to form a plurality of bit lines (eg, bit line 104 shown in FIG. 1F ) extending in the horizontal direction D1 and arranged in the vertical direction D2. In some embodiments, the bit line material layer 102 may be patterned by the following steps.

First, referring to FIG. 1A and FIG. 1B , a plurality of first mask patterns PR1 extending in a horizontal direction D1 and arranged in a vertical direction D2 are formed on a bit line material layer 102. In some embodiments, the extension portion 102b of the bit line material layer 102 includes a plurality of first extension portions 102b formed on a first side of the main portion 102a (e.g., the right side of the main portion 102a) and a plurality of second extension portions 102b formed on a second side of the main portion 102a opposite to the first side (e.g., the left side of the main portion 102a), and each of the first mask patterns PR1 covers one of the plurality of first extension portions 102b and one of the plurality of second extension portions 102b.

Next, referring to FIG. 1B and FIG. 1C , a spacer SP1 is formed on the sidewall of each first mask pattern PR1, wherein each spacer SP1 includes an annular pattern surrounding each first mask pattern PR1. In some embodiments, the annular pattern includes a plurality of line portions and a plurality of curved portions connecting the ends of the line portions. For example, as shown in FIG. 1C , the spacer SP1 having an annular pattern includes two upper and lower line portions, a left curved portion connecting the left ends of the upper and lower line portions, and a right curved portion connecting the right ends of the upper and lower line portions. Then, referring to FIG. 1C and FIG. 1D , the plurality of first mask patterns PR1 are removed to form a mask pattern including the spacer SP1. The spacer SP1 may be a single layer or multiple layers and may include materials for the spacer such as silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, amorphous carbon-containing compounds, crystalline carbon-containing compounds, diamond-like carbon coating or combinations thereof.

Then, referring to FIG. 1D and FIG. 1E , a second mask pattern PR2 is formed on the bit line material layer 102 to cover the bent portion of the spacer SP1, wherein the second mask pattern PR2 exposes the main portion 102a of the bit line material layer 102 and a portion of each extension portion 102b (e.g., a rounded portion at the end of each extension portion 102b).

1E and 1F, a mask pattern including the spacer SP1 and the second mask pattern PR2 are used as etching masks to remove a portion of the bit line material layer 102 exposed by the spacer SP1 and the second mask pattern PR2 to form a plurality of bit lines 104 and a plurality of dummy bit lines 106. In some embodiments, the dummy bit lines 106 are formed at opposite sides of the plurality of bit lines 104 in the vertical direction D2 to sandwich the plurality of bit lines 104 therebetween. In some embodiments, each bit line 104 is formed to include a line pattern 104a and a landing pad pattern 104b connected to one end of the line pattern 104a, so that a bit line contact (such as a bit line contact 110 shown in FIG. 1H ) formed subsequently can be landed on the landing pad pattern 104b having a larger area and pitch than the line pattern 104a, thereby improving the process margin of the bit line contact. In some embodiments, the landing pad pattern 104b and the other end of the line pattern 104a (e.g., the end without the landing pad pattern 104b) are alternately arranged in the vertical direction D2.

In some embodiments, each landing pad pattern 104b includes a first surface connected to the line pattern 104a and a second surface opposite to the first surface in the horizontal direction D1, wherein the profile of the second surface is different from the profile of the first surface (as shown in FIGS. 2 to 4). In some embodiments, the second surface of the landing pad pattern 104b is a circular profile (as shown in FIGS. 2 to 4). In some embodiments, each landing pad pattern 104b includes a third surface and a fourth surface opposite to each other in the vertical direction D2, wherein the profile of the third surface is the same as the profile of the fourth surface. In some embodiments, the third surface and the fourth surface of the landing pad pattern 104b connect the first surface and the second surface of the landing pad pattern 104b together. In some embodiments, the angle between the first surface of each landing pad pattern 104b and the third surface or the fourth surface (e.g., the angle θ1 shown in FIGS. 2 to 3) includes a right angle (as shown in FIG. 2), a blunt angle (as shown in FIG. 3), or a sharp angle (as shown in FIG. 4). In some embodiments, the angle between the first surface of each landing pad pattern 104b and the third surface or the fourth surface is about 70° to about 140°. In some embodiments, the width W1 of the line pattern 104a is about 8 nm to about 12 nm.

Next, referring to FIG. 1F and FIG. 1G , after forming a plurality of bit lines 104, the spacer SP1 and the second mask pattern PR2 are removed. Then, a plurality of conductive contacts 108 arranged in the horizontal direction D1 are formed between two adjacent bit lines 104. In some embodiments, the conductive contact 108a formed in the cell region R1 is electrically connected to the memory cell formed in the cell region R1. In some embodiments, the conductive contact 108a formed in the cell region R1 may be a storage node contact (SN contact). In some embodiments, the conductive contact 108b formed in the pickup region R2 may be a storage node contact. The conductive contact 108 may include a conductive material such as a metal or a metal alloy. The metal or metal alloy may be, for example, Cu, Al, Ti, Ta, W, Pt, Cr, Mo or an alloy thereof.

Afterwards, referring to FIG. 1G and FIG. 1H , a bit line contact 110 is formed on each landing pad pattern 104b to overlap the landing pad pattern 104b, wherein the bit line contact 110 is separated from the outermost conductive contact 108 in the horizontal direction D1. It can be seen that the bit line contact 110 can be landed on the landing pad pattern 104b having a larger area and a larger spacing than the line pattern 104a, thereby avoiding problems such as short circuits caused by alignment errors, and the critical size requirements for the bit line contact 110 are relatively loose, so that the bit line contact 110 has a good process margin.

In some embodiments, as shown in FIG. 5 , the semiconductor device may include an element isolation structure 112 formed in a substrate, wherein the landing pad pattern 104 b of the bit line 104 can be formed on the element isolation structure 112. The element isolation structure 112 may include a material for an element isolation structure such as silicon oxide. In some embodiments, the element isolation structure 112 may be a shallow trench isolation (STI) structure.

In summary, in the method of forming a semiconductor device of the above-mentioned embodiment, the bit line is formed to include a line pattern and a landing pad pattern connected to one end of the line pattern, so that the bit line contact can be formed on the landing pad pattern whose area and pitch are larger than those of the line pattern, thereby improving the process margin of the bit line contact.

102: Bit line material layer 102a: Main body 102b: Extension 104: Bit line 104a: Line pattern 104b: Landing pad pattern 106: Virtual bit line 108, 108a, 108b: Conductive contacts 110: Bit line contacts 112: Component isolation structure D1: Horizontal direction D2: Vertical direction PR1: First mask pattern PR2: Second mask pattern R1: Cell region R2: Pickup region SP1: Spacer W1: Width θ1: Angle

1A to 1H are schematic top views of a method for forming a semiconductor device according to an embodiment of the present invention. FIG. 2 is a schematic top view of a landing pad pattern of FIG. 1H. FIG. 3 is a schematic top view of a landing pad pattern according to another embodiment of the present invention. FIG. 4 is a schematic top view of a landing pad pattern according to yet another embodiment of the present invention. FIG. 5 is a schematic top view of a semiconductor device according to an embodiment of the present invention.

104: Bit line

104a: Line pattern

104b: Landing pad pattern

106: Virtual bit line

108, 108a, 108b: conductive contacts

110: Bit line contacts

D1: Horizontal direction

D2: vertical direction

R1: Cell area

R2: Pickup Area

Claims (10)

A method for forming a semiconductor device, comprising: forming a bit line material layer on a substrate, the substrate comprising a cell region and a pickup region adjacent to the cell region and located at an opposite side of the cell region in the horizontal direction, wherein the bit line material layer comprises a main body portion and a plurality of extension portions extending from the main body portion in the horizontal direction and arranged in the vertical direction; and patterning the bit line material layer to form a plurality of bit lines extending in the horizontal direction and arranged in the vertical direction, wherein each of the bit lines comprises a line pattern and a landing pad pattern connected to one end of the line pattern. A method as described in claim 1, wherein the landing pad pattern and the other end of the line pattern are arranged alternately in the vertical direction. A method as described in claim 1, wherein each of the landing pad patterns includes a first surface connected to the line pattern and a second surface opposite to the first surface in the horizontal direction, and the contour of the second surface is different from the contour of the first surface. A method as described in claim 3, wherein the second surface has a circular contour. A method as described in claim 3, wherein each of the landing pad patterns includes a third surface and a fourth surface opposite to each other in the vertical direction, and the profile of the third surface is the same as the profile of the fourth surface. A method as described in claim 5, wherein the angle between the first surface and the third surface or the fourth surface includes a blunt angle, a sharp angle or a right angle. The method as described in claim 1, wherein patterning the bit line material layer comprises: forming a plurality of first mask patterns extending in the horizontal direction and arranged in the vertical direction on the bit line material layer; forming spacers on the side walls of each of the first mask patterns, wherein each of the spacers comprises an annular pattern, wherein the annular pattern comprises a plurality of line portions and a plurality of curved portions connecting the ends of the line portions; removing a plurality of the first mask patterns; forming a second mask pattern covering the curved portions of the spacers on the bit line material layer, wherein the second mask pattern exposes the main portion of the bit line material layer and a portion of each of the extension portions; and removing a portion of the bit line material layer exposed by the spacers and the second mask pattern to form a plurality of the bit lines. A method as described in claim 7, wherein the multiple extension portions include a plurality of first extension portions formed on a first side of the main portion and a plurality of second extension portions formed on a second side of the main portion opposite to the first side, and each of the first mask patterns covers one of the multiple first extension portions and one of the multiple second extension portions. The method as described in claim 7 further includes: After forming a plurality of the bit lines, removing the spacer and the second mask pattern; and forming a plurality of conductive contacts arranged in the horizontal direction between two adjacent bit lines. The method of claim 9 further comprises: forming a bit line contact overlapping the landing pad pattern on each of the landing pad patterns, wherein the bit line contact is separated from the outermost conductive contact in the horizontal direction.