TWI893929B - Method for forming semiconductor device - Google Patents

Abstract

The present disclosure provides a method for forming a semiconductor device, which includes following steps. A planarization layer is formed on a driving substrate. A glue layer and a reflection layer are formed on the planarization layer in sequence. A mask pattern is formed on the reflection layer, wherein the mask pattern includes a first mask material layer formed on the reflection layer, a second mask material pattern formed on the first mask material layer, and a third mask material layer formed on a top surface and sidewalls of the second mask material pattern. A portion of the first mask material layer exposed by the second mask material pattern and the third mask material layer and the reflection layer and the glue layer under the portion, so as to form a reflection pattern array exposing the planarization layer. The mask pattern is removed and a passivation layer is formed on the planarization layer to cover the reflection pattern array, wherein the passivation layer fills into a gap pattern defining the reflection pattern array.

Description

Method for forming semiconductor device

The present invention relates to a method for forming a semiconductor device, and more particularly to a method for forming a spectroscopic device such as liquid crystal on silicon (LCOS).

Liquid crystal on silicon (LCOS) is a technology that integrates semiconductor and liquid crystal manufacturing processes and is currently one of the mainstream micro-projection technologies. Generally speaking, LCOS can be formed through the following steps. First, a driver substrate is formed on a silicon wafer through semiconductor processes such as front-end of line (FEOL) and/or back-end of line (BEOL). The reflector is then fabricated by forming a metal material on the driver substrate and performing a planarization process such as chemical mechanical polishing (CMP). Next, a glass substrate is bonded to the driver substrate, liquid crystal is injected, and packaging is performed to complete the LCOS process.

However, defects caused by planarization processes such as CMP on the metal material used as the reflector can affect the surface roughness of the reflector. As electronic devices continue to shrink in size and user demands for higher performance, these effects may make it difficult to meet current and future demands.

The present invention provides a method for forming a semiconductor device, wherein a reflective pattern array is formed by removing a portion of a first mask material layer exposed by a second mask material pattern and a third mask material layer, as well as the reflective layer and adhesive layer beneath the portion. In other words, the reflective pattern array is not affected by defects caused by planarization processes such as CMP. This improves the surface roughness of the reflective pattern array, resulting in good reflectivity.

One embodiment of the present invention provides a method for forming a semiconductor device, comprising: forming a planar layer on a driving substrate; sequentially forming a glue layer on the planar layer; layer) and a reflective layer; forming a mask pattern on the reflective layer, wherein the mask pattern includes a first mask material layer formed on the reflective layer, a second mask material pattern formed on the first mask material layer, and a third mask material layer formed on the top surface and sidewalls of the second mask material pattern; removing a portion of the first mask material layer exposed by the second mask material pattern and the third mask material layer, as well as the reflective layer and the adhesive layer below the portion, to form a reflective pattern array exposing the planar layer; and removing the mask pattern and forming a passivation layer on the planar layer to cover the reflective pattern array, wherein the passivation layer fills the gap pattern defining the reflective pattern array.

In some embodiments, the step of forming the reflective pattern array does not include a planarization process.

In some embodiments, the planarization process includes a chemical mechanical polishing (CMP) process.

In some embodiments, the first mask material layer is in direct contact with the reflective layer.

In some embodiments, the reflective pattern array includes a plurality of stacked structures arranged in an array, each stacked structure including a patterned adhesive layer and a patterned reflective layer formed on the patterned adhesive layer, wherein the thickness of the patterned reflective layer is approximately equal to the thickness of the reflective layer, and the thickness of the patterned adhesive layer is approximately equal to the thickness of the adhesive layer.

In some embodiments, the portion of the passivation layer formed in the spacer pattern is not subjected to a planarization process.

In some embodiments, the adhesive layer includes a metal nitride and the reflective layer includes a metal material.

In some embodiments, the first mask material layer includes a bottom anti-reflection coating (BARC), the second mask material pattern includes a photoresist material, and the third mask material layer includes an organic material.

In some embodiments, the reflective pattern array is electrically connected to active devices formed in the driving substrate.

In some embodiments, the method of forming a semiconductor device further includes forming a liquid crystal substrate covering the passivation layer above the driving substrate.

Based on the above, in the aforementioned method for forming a semiconductor device, the reflective pattern array is formed by removing a portion of the first mask material layer exposed by the second mask material pattern and the third mask material layer, as well as the reflective layer and adhesive layer beneath the portion. In other words, the reflective pattern array is not subjected to a planarization process such as CMP and is not affected by the defects associated with such a process. This improves the surface roughness of the reflective pattern array, resulting in excellent reflectivity.

10: Drive substrate

12: Active components

14: Conductive vias

100: Flat layer

110: Adhesive layer

112: Patterned adhesive layer

120: Reflective layer

122: Patterned reflective layer

130: First mask material layer

132: Second mask material pattern

134: Third mask material layer

140: Passivation layer

GP: Gap Pattern

MP: Mask pattern

RP: Reflective Pattern Array

Figures 1 to 7 are schematic cross-sectional views of a method for forming a semiconductor device according to an embodiment of the present invention.

The present invention will be more fully described with reference to the drawings of the present embodiment. However, the present invention may be embodied in various forms and should not be limited to the embodiments described herein. The thickness of layers and regions in the drawings may be exaggerated for clarity. Identical or similar reference numbers denote identical or similar elements, and detailed descriptions will not be repeated in the following paragraphs.

It should be understood that when an element is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element, or intervening elements may be present. When an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements. As used herein, "connected" can refer to physical and/or electrical connections, and "electrically connected" or "coupled" can mean the presence of other elements between two elements. As used herein, "electrically connected" can include both physical connections (e.g., wired connections) and physical disconnections (e.g., wireless connections).

As used herein, "about," "approximately," or "substantially" encompasses the stated value and the average within an acceptable range of deviation from the specified value as determined by one of ordinary skill in the art, taking into account the measurement in question and the specific amount of error associated with the measurement (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, or ±5%. Furthermore, as used herein, "about," "approximately," or "substantially" may be used to select an acceptable range of deviation or standard deviation depending on the optical, etching, or other properties, rather than applying a single standard deviation to all properties.

The terms used herein are intended to describe exemplary embodiments only and are not intended to limit the present disclosure. In this context, the singular includes the plural unless the context otherwise requires.

Figures 1 to 7 are schematic cross-sectional views of a method for forming a semiconductor device according to an embodiment of the present invention. Figure 6 is an upper view of Figure 5 according to an embodiment. To clearly illustrate the pattern of the reflective pattern array RP, Figure 6 omits the passivation layer 140.

First, referring to Figures 1 and 7 , a planar layer 100 is formed on a driver substrate 10. In some embodiments, the driver substrate 10 may include a semiconductor substrate or a semiconductor on insulator (SOI) substrate, a device layer formed on the semiconductor substrate or SOI substrate, and an interconnect layer/interconnect structure formed on the device layer. The planar layer 100 may include a dielectric material such as an oxide (e.g., silicon oxide).

The semiconductor material in the semiconductor substrate or SOI substrate may include elemental semiconductors, alloy semiconductors, or compound semiconductors. For example, elemental semiconductors may include Si or Ge. Alloy semiconductors may include SiGe, SiGeC, etc. Compound semiconductors may include SiC, Group III-V semiconductor materials, or Group II-VI semiconductor materials. Group III-V semiconductor materials may include GaN, GaP, GaAs, AlN, AlP, AlAs, InN, InP, InAs, GaNPs, GaNAs, GaPAs, AlNPs, AlNAs, AlPAs, InNPs, InNAs, InPAs, GaAlNPs, GaAlNAs, GaAlPAs, GaInNPs, GaInNAs, GaInPAs, InAlNPs, InAlNAs, or InAlPAs. Group II-VI semiconductor materials may include CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, HgS, HgSe, HgTe, CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdZnS e. CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe or HgZnSTe. The semiconductor material may be doped with a dopant of a first conductivity type or a dopant of a second conductivity type that is complementary to the first conductivity type. For example, the first conductivity type may be P-type and the second conductivity type may be N-type.

The device layer may include active devices 12 such as N-type metal oxide semiconductors (NMOS), P-type metal oxide semiconductors (PMOS), or complementary metal oxide semiconductors (CMOS). The interconnect layer/interconnect structure may include dielectric layers, conductive layers, and conductive vias (such as conductive via 14 shown in FIG. 7 ) formed through back-end of line (BEOL) processes. The dielectric layer may include an oxide, such as tetraethyl orthosilicate (TEOS), borophosphosilicate glass (BPSG), an oxide formed using high-density plasma (HDP), undoped silicate glass (USG), phosphosilicate glass (PSG), an oxide formed using spin-on techniques such as spin-on glass (SOG) and spin-on dielectric (SOD), or an oxide formed using a high aspect ratio process (HARP). The conductive layer and/or conductive via may include a conductive material such as a metal or metal alloy. Examples of the metal and metal alloy include Cu, Al, Ti, Ta, W, Pt, Cr, Mo, or alloys thereof.

Next, referring to Figure 1 , a glue layer 110 and a reflective layer 120 are sequentially formed on the planar layer 100. In some embodiments, the glue layer 110 may comprise a metal nitride, and the reflective layer 120 may comprise a metal material. The metal nitride may comprise titanium nitride (TiN). The metal material may comprise aluminum (Al). In some embodiments, the reflective layer 120 may be formed, for example, by a deposition process at room temperature. This can reduce the grain size of the metal material (e.g., aluminum) in the reflective layer 120, thereby improving the reflectivity of the reflective layer 120. In some embodiments, the glue layer 110 may have a thickness of approximately 100 Å. In some embodiments, the reflective layer 120 may have a thickness of approximately 500 Å.

Then, referring to Figures 2 and 3, a mask pattern MP is formed on the reflective layer 120, wherein the mask pattern MP includes a first mask material layer 130 formed on the reflective layer 120, a second mask material pattern 132 formed on the first mask material layer 130, and a third mask material layer 134 formed on the top surface and sidewalls of the second mask material pattern 132. In some embodiments, the first mask material layer 130 may be in direct contact with the reflective layer 120. In some embodiments, the first mask material layer 130 may include a material for a bottom anti-reflection coating (BARC), the second mask material pattern 132 may include a photoresist material, and the third mask material layer 134 may include an organic material. In some embodiments, the organic material used in the third mask material layer 134 reacts only with the photoresist material and not with the material used for the BARC. In other words, the third mask material layer 134 adheres only to the top and sidewalls of the second mask material pattern 132, while the portion on the surface of the first mask material layer 130 is removed (e.g., washed away) during the step of forming the third mask material layer 134. In some embodiments, the step of forming the third mask material layer 134 may include the following steps: First, a reactive reagent is applied to the surfaces of the first mask material layer 130 and the second mask material pattern 132 by spin coating. Next, a third mask material layer 134 is formed through a resolution-enhanced lithography assisted by chemical shrink (RELACS) process. In some embodiments, the reaction reagent material is, for example, a commercially available RELACS reagent (AZ R200T, Anzhi Electronic Materials Co., Ltd.).

Next, referring to Figures 3 and 4 , a portion of the first mask material layer 130 exposed by the second mask material pattern 132 and the third mask material layer 134, as well as the reflective layer 120 and the adhesive layer 110 beneath the portion, are removed to form a reflective pattern array RP that exposes the planar layer 100. Subsequently, referring to Figures 4 and 5 , the mask pattern MP is removed, and a passivation layer 140 is formed on the planar layer 100 to cover the reflective pattern array RP. The passivation layer 140 fills the gap pattern GP that defines the reflective pattern array RP. In some embodiments, the passivation layer 140 may include a material commonly used for a passivation layer 140, such as an oxide (e.g., silicon oxide). In some embodiments, the passivation layer 140 may be formed by deposition. In some embodiments, the passivation layer 140 may be deposited at a rate of approximately 50 Å/s to approximately 100 Å/s to improve the surface roughness of the passivation layer 140 , thereby reducing the impact on the reflectivity of the reflective pattern array RP.

In some embodiments, because the step of forming the reflective pattern array RP does not include a planarization process, the reflective pattern array RP is not affected by defects generated by the planarization process. This improves the surface roughness of the reflective pattern array RP, resulting in good reflectivity. In some embodiments, the planarization process may include a chemical mechanical polishing (CMP) process. In this embodiment, the portion of the passivation layer 140 formed within the gap pattern GP is also not subjected to the planarization process.

In some embodiments, as shown in Figures 5 and 6 , the reflective pattern array RP may include a plurality of stacked structures arranged in an array. Each stacked structure includes a patterned adhesive layer 112 and a patterned reflective layer 122 formed on the patterned adhesive layer 112. The thickness of the patterned reflective layer 122 is approximately equal to the thickness of the reflective layer 120, and the thickness of the patterned adhesive layer 112 is approximately equal to the thickness of the adhesive layer 110. In other words, the thickness of the reflective pattern array RP is not adjusted through a planarization process such as CMP. This ensures that the formed reflective pattern array RP is not affected by defects generated by the planarization process, thereby improving the surface roughness of the reflective pattern array RP and achieving good reflectivity.

The above-described step of forming the reflective pattern array RP can further reduce the critical dimension (CD) of the gap pattern GP. This can increase the overall reflectivity of the LCOS by increasing the area of the reflective pattern array RP. In some embodiments, the reflectivity of the LCOS can be determined by the surface roughness of the reflective pattern array RP, which affects the reflectivity of the reflective pattern array RP, and the surface roughness of the passivation layer 140, which also affects the reflectivity of the reflective pattern array RP. The above-described method of forming a semiconductor device can effectively improve the surface roughness of the reflective pattern array RP and the passivation layer 140, thereby significantly increasing the reflectivity of the LCOS. As a result, when LCOS is used in projectors or digital cameras, for example, the projectors or digital cameras can achieve excellent imaging brightness due to the excellent reflectivity of LCOS.

In some embodiments, the step of forming the reflective pattern array RP can further reduce the aspect ratio of the gap pattern GP, allowing the passivation layer 140 to well fill the gap pattern GP without affecting its surface roughness, thereby reducing the impact on the reflectivity of the underlying reflective pattern array RP.

In some embodiments, as shown in FIG7 , the reflective pattern array RP is electrically connected to the active device 12 formed in the driver substrate 10 . In some embodiments, the reflective pattern array RP can be electrically connected to the active device 12 via a conductive via 14 formed in the interconnect structure of the driver substrate 10 .

In some embodiments, as shown in FIG7 , a liquid crystal substrate 20 is formed over a drive substrate 10 and overlying a passivation layer 140. In some embodiments, the liquid crystal substrate 20 may include spacers (not shown) for defining locations for filling the liquid crystal, an upper alignment layer (not shown) and a lower alignment layer (not shown) formed at the upper and lower ends of the liquid crystal, a front electrode (not shown) formed on the upper alignment layer and used to control the liquid crystal, and a glass substrate (not shown) formed on the front electrode.

In summary, in the method for forming a semiconductor device according to the above embodiment, the reflective pattern array is formed by removing a portion of the first mask material layer exposed by the second mask material pattern and the third mask material layer, as well as the reflective layer and adhesive layer beneath the portion. In other words, the reflective pattern array is not subjected to a planarization process such as CMP and is not affected by the defects associated with such a process. This improves the surface roughness of the reflective pattern array, resulting in good reflectivity.

100: Flat layer

110: Adhesive layer

120: Reflective layer

130: First mask material layer

132: Second mask material pattern

134: Third mask material layer

MP: Mask pattern

Claims (10)

A method for forming a semiconductor device comprises: forming a planar layer on a driving substrate; sequentially forming a glue layer and a reflective layer on the planar layer; forming a mask pattern on the reflective layer, wherein the mask pattern comprises a first mask material layer formed on the reflective layer, a second mask material pattern formed on the first mask material layer, and a third mask material layer formed on the top and sidewalls of the second mask material pattern; removing a portion of the first mask material layer exposed by the second mask material pattern and the third mask material layer, and removing the reflective layer and the glue layer below the portion to form a reflective pattern array exposing the planar layer; and The mask pattern is removed and a passivation layer covering the reflective pattern array is formed on the planar layer, wherein the passivation layer fills the gap pattern defining the reflective pattern array. The method of claim 1, wherein the step of forming the reflective pattern array does not include a planarization process. The method of claim 2, wherein the planarization process comprises a chemical mechanical polishing (CMP) process. The method of claim 1, wherein the first mask material layer is in direct contact with the reflective layer. A method as described in claim 1, wherein the reflective pattern array includes a plurality of stacked structures arranged in an array, each stacked structure includes a patterned adhesive layer and a patterned reflective layer formed on the patterned adhesive layer, wherein the thickness of the patterned reflective layer is approximately equal to the thickness of the reflective layer, and the thickness of the patterned adhesive layer is approximately equal to the thickness of the adhesive layer. The method of claim 1, wherein a portion of the passivation layer formed in the gap pattern is not subjected to a planarization process. The method of claim 1, wherein the adhesive layer comprises metal nitride and the reflective layer comprises a metal material. The method of claim 1, wherein the first mask material layer comprises a bottom anti-reflection coating (BARC), the second mask material pattern comprises a photoresist material, and the third mask material layer comprises an organic material. The method of claim 1, wherein the reflective pattern array is electrically connected to an active device formed in the driving substrate. The method of claim 1 further includes: forming a liquid crystal substrate overlying the passivation layer above the driving substrate.