TWI858955B - Semiconductor device and method of forming the same - Google Patents

Abstract

The present disclosure provides a semiconductor device and a method of forming the same. The method includes following steps. An epitaxial layer is formed on a substrate including a cell region and a connection region adjacent to the cell region. The epitaxial layer includes a first well adjacent to the substrate and a second well on the first well. The epitaxial layer includes first trenches formed in the cell region and extending from a top surface of the epitaxial layer into the second region and second trenches formed in the connection region and extending from the top surface of the epitaxial layer into the first well. A first doped region is formed in the second region within the cell region through sidewalls of each first trench. The first doped region is spaced apart from the first well by a portion of the second well disposed therebetween. A second doped region is formed in the second region within the connection region through sidewalls of each second trench, and the second doped region extends into the first well.

Description

Semiconductor device and method for forming the same

The present invention relates to a semiconductor device and a method for forming the same.

Power semiconductor devices, such as metal oxide semiconductor field effect transistors (MOSFET), are power devices commonly used in analog and/or digital circuits, and can be divided into planar power semiconductor devices and vertical power semiconductor devices according to the direction of current flow. Vertical power semiconductor devices can be, for example, power MOSFETs that operate at low voltages, such as trench gate power MOSFETs or split gate power MOSFETs.

As device sizes continue to shrink and users' requirements for electronic device performance continue to increase, existing power MOSFETs may not be able to meet the needs of current or future high-voltage devices in terms of certain performance (such as voltage resistance), and the manufacturing cost is becoming increasingly expensive, making it difficult to commercialize.

The present invention provides a semiconductor device and a method for forming the same, wherein a first doped region is formed in a second well region in a cell region through the side walls of each first trench, and a second doped region is formed in a second well region in a connection region through the side walls of each second trench, the first doped region and the first well region are separated by a portion of the second well region disposed therebetween, and the second doped region extends into the first well region. In this way, a super junction can be formed between two adjacent first trenches and/or between two adjacent second trenches, so that the semiconductor device can form full depletion between the two adjacent first trenches and/or between the two adjacent second trenches by applying a bias to the super junction, thereby improving the withstand voltage performance of the semiconductor device.

An embodiment of the present invention provides a method for forming a semiconductor device, comprising: forming an epitaxial layer on a substrate, wherein the substrate comprises a cell region and a connection region adjacent to the cell region, the epitaxial layer comprises a first well region adjacent to the substrate and a second well region on the first well region, the epitaxial layer comprises a plurality of first trenches formed in the cell region and extending from a top surface of the epitaxial layer to the second well region, and a plurality of first trenches formed in the connection region and extending from a top surface of the epitaxial layer to the second well region. The top surface of the epitaxial layer extends to a plurality of second trenches in the first well region; a first doped region is formed in the second well region in the cell region through the side walls of each first trench, wherein the first doped region is separated from the first well region by a portion of the second well region disposed therebetween; and a second doped region is formed in the second well region in the connection region through the side walls of each second trench, and the second doped region extends to the first well region.

In one embodiment of the present invention, the substrate, the first well region, the first doped region and the second doped region have a first conductivity type, and the second well region has a second conductivity type different from the first conductivity type.

In one embodiment of the present invention, the bottom surface of the first trench is higher than the bottom surface of the second trench.

In one embodiment of the present invention, the method for forming a semiconductor device further includes: vertically removing a second well region of the epitaxial layer and a portion of the first well region thereunder through a plurality of first trenches to form a plurality of third trenches; and vertically removing a portion of the first well region of the epitaxial layer through a plurality of second trenches to form a plurality of fourth trenches.

In one embodiment of the present invention, the method for forming a semiconductor device further includes: forming a gate dielectric layer on the sidewalls and bottom surface of each third trench and each fourth trench; forming a gate on the gate dielectric layer, wherein the top surface of the gate is higher than the bottom of the first doped region and the second doped region; and forming an insulating layer on the gate.

In one embodiment of the present invention, the method for forming a semiconductor device further includes: forming a third doped region in the second well region extending from the top surface of the epitaxial layer to the top of the first doped region and the second doped region, wherein the first well region, the first doped region and the second doped region have a first conductivity type, and the second well region and the third doped region have a second conductivity type different from the first conductivity type.

In one embodiment of the present invention, the method for forming a semiconductor device further includes: forming a dielectric layer on the epitaxial layer; forming a contact opening in the dielectric layer to expose the top surface of the epitaxial layer; and forming a fourth doped region in the second well region of the epitaxial layer through the contact opening, wherein the fourth doped region has a second conductivity type and is formed between two adjacent third trenches and between two adjacent fourth trenches.

The present invention provides a semiconductor device, which includes a substrate, an epitaxial layer, a first doping region and a second doping region. The substrate includes a cell region and a connecting region adjacent to the cell region. The epitaxial layer is arranged on the substrate and includes a first well region adjacent to the substrate and a second well region on the first well region. The epitaxial layer includes a plurality of first trenches in the cell region and extending to the first well region and a plurality of second trenches in the connecting region and extending to the first well region. The bottom surface of the first trench is higher than the bottom surface of the second trench. The first doping region is arranged in the second well region adjacent to the side wall of the first trench, wherein the first doping region and the first well region are separated by a portion of the second well region arranged therebetween. The second doped region is disposed in the second well region adjacent to the sidewall of the second trench and extends from the second well region to the first well region.

In one embodiment of the present invention, the substrate, the first well region, the first doped region and the second doped region have a first conductivity type, and the second well region has a second conductivity type different from the first conductivity type.

In one embodiment of the present invention, the semiconductor device further includes a third doped region disposed in the second well region and extending from the top surface of the epitaxial layer to the top of the first doped region and the second doped region, wherein the third doped region has the second conductivity type.

In one embodiment of the present invention, a dielectric layer, a conductive contact and a fourth doped region are further included. The dielectric layer is disposed on the epitaxial layer. The conductive contact is disposed in the dielectric layer and contacts the top surface of the epitaxial layer. The fourth doped region is disposed in the second well region of the epitaxial layer and contacts the conductive contact, wherein the fourth doped region has a second conductivity type and is disposed between two adjacent first trenches and between two adjacent second trenches.

Based on the above, in the semiconductor device and the method for forming the same of the above embodiments, the first doped region is formed in the second well region in the cell region through the side walls of each first trench, and the second doped region is formed in the second well region in the connection region through the side walls of each second trench, the first doped region and the first well region are separated by a portion of the second well region disposed therebetween, and the second doped region extends into the first well region. In this way, a super junction can be formed between two adjacent first trenches and/or between two adjacent second trenches, so that the semiconductor device can form full depletion between the two adjacent first trenches and/or between the two adjacent second trenches by applying a bias to the super junction, thereby improving the withstand voltage performance of the semiconductor device.

The present invention is more fully described with reference to the drawings of the present embodiment. However, the present invention may be embodied in various forms and should not be limited to the embodiments described herein. The thickness of layers and regions in the drawings are exaggerated for clarity. The same or similar reference numbers represent the same or similar elements, and the following paragraphs will not be repeated one by one.

It should be understood that when an element is referred to as being "on" or "connected to" another element, it may be directly on or connected to another element, or there may be an intermediate element. If an element is referred to as being "directly on" or "directly connected to" another element, there are no intermediate elements. As used herein, "connection" may refer to physical and/or electrical connection, and "electrical connection" or "coupling" may be the presence of other elements between two elements. As used herein, "electrical connection" may include physical connection (e.g., wired connection) and physical disconnection (e.g., wireless connection).

As used herein, "about", "approximately" or "substantially" includes the referenced value and the average value within an acceptable deviation range of a specific value that can be determined by a person of ordinary skill in the art, taking into account the measurement in question and the specific amount of error associated with the measurement (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, as used herein, "about", "approximately" or "substantially" can select a more acceptable deviation range or standard deviation depending on the optical properties, etching properties or other properties, and can apply to all properties without a single standard deviation.

The terms used herein are used to describe exemplary embodiments only, rather than to limit the present disclosure. In this case, unless otherwise explained in the context, the singular form includes the plural form.

Figures 1 to 9 are cross-sectional schematic diagrams of a method for forming a semiconductor device according to an embodiment of the present invention. Figure 10 is a diagram showing a path of current in a cell region of a semiconductor device according to an embodiment of the present invention when the gate is open.

First, referring to FIG. 1 , an epitaxial layer 110 is formed on a substrate 100. The substrate 100 may include a cell region R1 and a connection region R2. The cell region R1 may be, for example, a region where active elements such as MOS are formed. The connection region R2 may be, for example, a region formed by connecting the first doping region 120a in the cell region R1 and connecting it to a wiring pattern of a corresponding structure/pattern. In some embodiments, the connection region R2 may be adjacent to the cell region R1. The epitaxial layer 110 includes a first well region PW adjacent to the substrate 100 and a second well region ND on the first well region PW. In some embodiments, the epitaxial layer 110 may be formed by an epitaxial growth process. The substrate 100 may be doped with a dopant of the first conductivity type to have the first conductivity type or may be doped with a dopant of the second conductivity type complementary to the first conductivity type to have the second conductivity type. In some embodiments, the first conductivity type may be a P type and the second conductivity type may be an N type, but is not limited thereto. The substrate 100 may have the first conductivity type. The first well region PW of the epitaxial layer 110 may have the first conductivity type, and the second well region ND of the epitaxial layer 110 may have the second conductivity type different from the first conductivity type.

The substrate 100 may include a semiconductor substrate. The semiconductor material in the semiconductor substrate may include an elemental semiconductor, an alloy semiconductor, or a compound semiconductor. For example, the elemental semiconductor may include Si or Ge. The alloy semiconductor may include SiGe, SiGeC, etc. The compound semiconductor may include SiC, a III-V semiconductor material, or a II-VI semiconductor material. The III-V semiconductor material may include GaN, GaP, GaAs, AlN, AlP, AlAs, InN, InP, InAs, GaNP, GaNAs, GaPAs, AlNP, AlNAs, AlPAs, InNP, InNAs, InPAs, GaAlNP, GaAlNAs, GaAlPAs, GaInNP, GaInNAs, GaInPAs, InAlNP, InAlNAs, or InAlPAs. Group II-VI semiconductor materials may include CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, HgS, HgSe, HgTe, CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdZnS e. CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe or HgZnSTe. The semiconductor material may be doped with a dopant of a first conductivity type or a dopant of a second conductivity type that is complementary to the first conductivity type.

Next, a protection layer PL is formed on the epitaxial layer 110. The protection layer PL may include a dielectric material such as tetraethyl orthosilicate (TEOS).

Then, a plurality of first trenches T1 in the cell region R1 and a plurality of second trenches T2 in the connection region R2 are formed in the epitaxial layer 110. That is, the epitaxial layer 110 includes a plurality of first trenches T1 formed in the cell region R1 and extending from the top surface of the epitaxial layer 110 to the second well region ND and a plurality of second trenches T2 formed in the connection region R2 and extending from the top surface of the epitaxial layer 110 to the first well region PW. The bottom surface of the first trench T1 is higher than the bottom surface of the second trench T2. In some embodiments, the first trench T1 and the second trench T2 can be formed simultaneously in the same process.

Then, a first doping region 120a is formed in the second well region ND in the cell region R1 through the sidewalls of each first trench T1, wherein the first doping region 120a and the first well region PW are separated by a portion of the second well region ND disposed therebetween. The first well region PW and the first doping region 120a have a first conductivity type (e.g., P-type), and the second well region ND has a second conductivity type (e.g., N-type) different from the first conductivity type. The first doping region 120a may be formed by a tilt implantation process. In some embodiments, the first doping region 120a may not be formed on the bottom surface of the first trench T1. In some embodiments, the first doped region 120a may include a top (or referred to as a top end) and a bottom (or referred to as a bottom end) opposite to each other on a surface perpendicular to the substrate 100, wherein the top of the first doped region 120a is lower than the top surface of the epitaxial layer 110, and the bottom of the first doped region 120a is higher than the interface where the first well region PW and the second well region ND contact each other. For example, in a direction perpendicular to the surface of the substrate 100, a portion of the second well region ND is located between the top of the first doped region 120a and the top surface of the epitaxial layer 110, and another portion of the second well region ND is located between the bottom of the first doped region 120a and the interface where the first well region PW and the second well region ND contact each other.

Furthermore, a second doped region 120b is formed in the second well region ND in the connection region R2 through the sidewalls of each second trench T2, and the second doped region 120b extends into the first well region PW. The first well region PW and the second doped region 120b have a first conductivity type (e.g., P type), and the second well region ND has a second conductivity type (e.g., N type) different from the first conductivity type. The second doped region 120b can be formed by a tilt implantation process. In this embodiment, the first doped region 120a and the second doped region 120b can be formed by the same ion implantation process. In the present embodiment, the protection layer PL can prevent dopants from being implanted into undesired locations during the process of forming the first doped region 120a and/or the second doped region 120b, such as locations in the second well region ND where the first doped region 120a and/or the second doped region 120b are not formed as shown in FIG. 1 .

In some embodiments, the second doped region 120b may include a top (or referred to as a top end) and a bottom (or referred to as a bottom end) opposite to each other on a surface perpendicular to the substrate 100, wherein the top of the second doped region 120b is lower than the top surface of the epitaxial layer 110, and the bottom of the first doped region 120a is lower than the interface where the first well region PW and the second well region ND contact each other. For example, in a direction perpendicular to the surface of the substrate 100, a portion of the second well region ND is located between the top of the second doped region 120b and the top surface of the epitaxial layer 110, and the second doped region 120b extends toward the substrate 100 and passes through the interface where the first well region PW and the second well region ND contact each other, so that the bottom of the second doped region 120b is formed in the first well region PW. In this embodiment, the bottom of the second doped region 120b is lower than the bottom of the first doped region 120a.

Based on the above, as shown in FIG. 1 , the first doped region 120 a and the second well region ND form a super junction (e.g., a PNP super junction) between two adjacent first trenches T1, and the second doped region 120 b forms a super junction (e.g., a PNP super junction) between two adjacent second trenches T2, so that the semiconductor device can form full depletion between the two adjacent first trenches T1 and/or between the two adjacent second trenches T2 by applying a bias to the super junction, thereby improving the withstand voltage performance of the semiconductor device.

Then, referring to FIG. 1 and FIG. 2 , a plurality of third trenches T11 are formed by vertically removing a portion of the second well region ND of the epitaxial layer 110 and a portion of the first well region PW thereunder through a plurality of first trenches T1, and a portion of the first well region PW of the epitaxial layer 110 is vertically removed through a plurality of second trenches T2 to form a plurality of fourth trenches T22. The bottom of the third trench T11 is higher than the bottom of the fourth trench T22. In some embodiments, the third trench T11 and the fourth trench T22 can be formed simultaneously in the same process.

Next, referring to FIG. 2 and FIG. 3 , after forming the third trench T11 and the fourth trench T22, the protection layer PL is removed and a gate dielectric material layer 130 is formed on the sidewalls and bottom surfaces of each of the third trenches T11 and each of the fourth trenches T22. In some embodiments, the gate dielectric material layer 130 is conformally formed on the top surface of the epitaxial layer 110 and on the surfaces of the third trenches T11 and the fourth trenches T22. The gate dielectric material layer 130 may include any material suitable for a gate dielectric layer, such as silicon oxide.

Thereafter, a gate material layer 140 is formed on the gate dielectric material layer 130. The gate material layer 140 may be filled in the third trench T11 and the fourth trench T22 and formed on the top surface of the epitaxial layer 110. The gate material layer 140 may include a material suitable for a gate, such as polysilicon.

Then, referring to FIG3 and FIG4, a portion of the gate material layer 140 formed on the top surface of the epitaxial layer 110 and the gate material layer 140 formed in the third trench T11 and the fourth trench T22 is removed to form a gate 142 located at the bottom of the third trench T11 and the fourth trench T22. In some embodiments, the gate material layer 140 formed on the top surface of the epitaxial layer 110 and the gate material layer 140 formed in the third trench T11 and the fourth trench T22 can be removed by etching back. In some embodiments, a top surface of the gate 142 may be higher than bottoms of the first and second doped regions 120a and 120b.

Afterwards, referring to FIG. 4 and FIG. 5 , an insulating material layer (not shown) is formed on the gate 142 in the third trench T11 and the fourth trench T22, wherein the insulating material layer may fill the third trench T11 and the fourth trench T22 and be formed on the gate dielectric material layer 130 above the epitaxial layer 110. In some embodiments, the insulating material layer may include an insulating material such as TEOS. Then, the gate dielectric material layer 130 and the insulating material layer above the epitaxial layer 110 are removed to form the gate dielectric layer 132 and the insulating layer 150. In some embodiments, the gate dielectric material layer 130 and the insulating material layer above the epitaxial layer 110 may be removed by etching back. In some embodiments, the top surface of the gate dielectric layer 132, the top surface of the insulating layer 150, and the top surface of the epitaxial layer 110 are coplanar.

Then, referring to FIG. 5 and FIG. 6 , a third doped region 160 is formed in the second well region ND, extending from the top surface of the epitaxial layer 110 to the top of the first doped region 120a and the second doped region 120b. The first well region PW, the first doped region 120a, and the second doped region 120b have a first conductivity type (e.g., P type), while the second well region ND and the third doped region 160 have a second conductivity type (e.g., N type) different from the first conductivity type. The third doped region 160 may be formed at the upper sidewalls of the third trench T11 and the fourth trench T22 adjacent to the second well region ND. A bottom of the third doped region 160 may be in contact with tops of the first doped region 120a and the second doped region 120b.

Then, referring to FIG. 6 and FIG. 7 , a dielectric layer 170 is formed on the epitaxial layer 110 . The dielectric layer 170 may include a material suitable for an interlayer dielectric (ILD), such as oxide. The dielectric layer 170 covers the second well region ND, the third doped region 160 , the gate dielectric layer 132 , and the insulating layer 150 .

Then, referring to FIG. 7 and FIG. 8 , a contact opening 170h is formed in the dielectric layer 170 to expose the top surface of the epitaxial layer 110. From a top view, the contact opening 170h is formed between two adjacent third trenches T11 and between two adjacent fourth trenches T22. Then, a fourth doped region 180 is formed in the second well region ND of the epitaxial layer 110 through the contact opening 170h. The fourth doped region 180 has a second conductivity type (e.g., N-type) and is formed between two adjacent third trenches T11 and between two adjacent fourth trenches T22. The first well region PW, the first doped region 120a and the second doped region 120b have a first conductivity type (eg, P type), while the second well region ND, the third doped region 160 and the fourth doped region 180 have a second conductivity type (eg, N type) different from the first conductivity type.

Afterwards, referring to FIGS. 8 and 9 , a conductive material is filled into the contact opening 170h to form a conductive contact 190. In some embodiments, when the conductive material is filled into the contact opening 170h and formed on the top surface of the dielectric layer 170, the step of forming the conductive contact 190 may further include a planarization process (e.g., etching back) to remove the conductive material formed on the top surface of the dielectric layer 170. The conductive contact 190 may include a metal, a metal alloy, a metal nitride, a metal silicide, or a combination thereof. In some embodiments, the metal and the metal alloy may be, for example, Cu, Al, Ti, Ta, W, Pt, Cr, Mo, or an alloy thereof. The metal nitride may be, for example, titanium nitride, tungsten nitride, tantalum nitride, tantalum silicon nitride, titanium silicon nitride, tungsten silicon nitride, or a combination thereof. The metal silicide may include tungsten silicide, titanium silicide, cobalt silicide, zirconium silicide, platinum silicide, molybdenum silicide, copper silicide, nickel silicide, or a combination thereof.

Based on the above, the first doped region 120a formed between the two adjacent third trenches T11 and the second doped region 120b formed between the two adjacent fourth trenches T22 can form a super junction such as PNP with the second well region ND, and the super junction can be biased (such as reverse bias) by the conductive contact 190 and the fourth doped region 180 to form full depletion between the two adjacent third trenches T11 and between the two adjacent fourth trenches T22, thereby improving the withstand voltage performance of the semiconductor device.

Referring to FIG. 10 , when the MOS in the cell region R1 is in an on state (e.g., a bias voltage greater than the threshold voltage (Vt) is provided to the gate 142, and the first well region PW is connected to the ground voltage (e.g., 0V)), the current (see path) in the cell region R1 can pass through the second well region ND between the first doped region 120a and the first well region PW and enter the first well region PW below the gate 142. On the other hand, the current in the connection region R2 is blocked by the second doped region 120b extending from the second well region ND to the first well region PW and cannot enter the first well region PW below the gate 142. That is, when the MOS in the cell region R1 is in the on state, the super junction in the cell region R1 will not affect the operation of the MOS, and the super junction in the connection region R2 can also block the current from entering the first well region PW under the gate 142 to avoid causing undesirable effects.

Hereinafter, a semiconductor device according to an embodiment of the present invention will be described by way of example with reference to Fig. 9. In addition, although the method for forming a semiconductor device according to an embodiment of the present invention is described using the above method as an example, the method for forming a semiconductor device according to the present invention is not limited thereto.

Referring to FIG. 9 , the semiconductor device includes a substrate 100, an epitaxial layer 110, a first doped region 120a, and a second doped region 120b. The substrate 100 includes a cell region R1 and a connection region R2 adjacent to the cell region R1. The epitaxial layer 110 is disposed on the substrate 100 and includes a first well region PW adjacent to the substrate 100 and a second well region ND on the first well region PW. The epitaxial layer 110 includes a plurality of first trenches (e.g., T11 shown in FIG. 2 ) in the cell region R1 and extending to the first well region PW, and a plurality of second trenches (e.g., T22 shown in FIG. 2 ) in the connection region R2 and extending to the first well region PW, and the bottom surface of the first trench is higher than the bottom surface of the second trench. The first doped region 120a is disposed in the second well region ND adjacent to the sidewall of the first trench (e.g., T11 shown in FIG. 2 ), wherein the first doped region 120a and the first well region PW are separated by a portion of the second well region ND disposed therebetween. The second doped region 120b is disposed in the second well region ND adjacent to the sidewall of the second trench (e.g., T22 shown in FIG. 2 ) and extends from the second well region ND to the first well region PW.

In some embodiments, the substrate 100, the first well region PW, the first doped region 120a, and the second doped region 120b have a first conductivity type, and the second well region ND has a second conductivity type different from the first conductivity type.

In some embodiments, the semiconductor device further includes a third doped region 160, which is disposed in the second well region ND and extends from the top surface of the epitaxial layer 110 to the top of the first doped region 120a and the second doped region 120b, wherein the third doped region 160 has the second conductivity type.

In some embodiments, the semiconductor device further includes a dielectric layer 170, a conductive contact 190, and a fourth doped region 180. The dielectric layer 170 is disposed on the epitaxial layer 110. The conductive contact 190 is disposed in the dielectric layer 170 and contacts the top surface of the epitaxial layer 110. The fourth doped region 180 is disposed in the second well region ND of the epitaxial layer 110 and contacts the conductive contact 190. The fourth doped region 180 has a second conductivity type and is disposed between two adjacent first trenches (e.g., T11 shown in FIG. 2 ) and between two adjacent second trenches (e.g., T22 shown in FIG. 2 ).

In summary, in the semiconductor device and the method for forming the same of the above-mentioned embodiments, the first doped region is formed in the second well region in the cell region through the side walls of each first trench, and the second doped region is formed in the second well region in the connection region through the side walls of each second trench, the first doped region and the first well region are separated by a portion of the second well region disposed therebetween, and the second doped region extends into the first well region. In this way, a super junction can be formed between two adjacent first trenches and/or between two adjacent second trenches, so that the semiconductor device can form full depletion between the two adjacent first trenches and/or between the two adjacent second trenches by applying a bias to the super junction, thereby improving the withstand voltage performance of the semiconductor device.

100: Base

110: Epitaxial layer

120a: First doping area

120b: Second doping area

130: Gate dielectric material layer

132: Gate dielectric layer

140: Gate material layer

142: Gate

150: Insulation layer

160: The third mixed area

170: Dielectric layer

170h: Contact opening

180: Fourth mixed area

190: Conductive contact

ND: Second Well Area

PW: First Well Area

PL: Protective layer

path:path

R1: Cell area

R2: Connection Area

T1: First channel

T11: The third canal

T2: Second channel

T22: Fourth Channel

Figures 1 to 9 are cross-sectional schematic diagrams of a method for forming a semiconductor device according to an embodiment of the present invention. Figure 10 is a diagram showing the path of current in a cell region of a semiconductor device according to an embodiment of the present invention when the gate is open.

100: Base

110: Epitaxial layer

120a: First mixed zone

120b: Second mixed area

132: Gate dielectric layer

142: Gate

150: Insulation layer

160: The third mixed area

170: Dielectric layer

180: The fourth mixed area

190: Conductive contact

ND: Second well area

PW: First Well Area

R1: Cell area

R2: Connection area

Claims (9)

A method for forming a semiconductor device, comprising: forming an epitaxial layer on a substrate, wherein the substrate comprises a cell region and a connection region adjacent to the cell region, the epitaxial layer comprises a first well region adjacent to the substrate and a second well region on the first well region, the epitaxial layer comprises a plurality of first trenches formed in the cell region and extending from a top surface of the epitaxial layer to the second well region, and a plurality of first trenches formed in the connection region and extending from the top surface of the epitaxial layer to the second well region. A plurality of second trenches extending from the surface to the first well region; a first doped region is formed in the second well region in the cell region through the sidewalls of each of the first trenches, wherein the first doped region is separated from the first well region by a portion of the second well region disposed therebetween; and a second doped region is formed in the second well region in the connection region through the sidewalls of each of the second trenches, and the second doped region extends to the first well region. The method of claim 1, wherein the substrate, the first well region, the first doped region and the second doped region have a first conductivity type, and the second well region has a second conductivity type different from the first conductivity type. A method as described in claim 1, wherein the bottom surface of the first trench is higher than the bottom surface of the second trench. The method of claim 1 further includes: vertically removing the second well region of the epitaxial layer and a portion of the first well region thereunder through a plurality of the first trenches to form a plurality of third trenches; and vertically removing a portion of the first well region of the epitaxial layer through a plurality of the second trenches to form a plurality of fourth trenches. The method described in claim 4 further includes: forming a gate dielectric layer on the sidewalls and bottom surface of each of the third trenches and each of the fourth trenches; forming a gate on the gate dielectric layer, wherein the top surface of the gate is higher than the bottom of the first doped region and the second doped region; and forming an insulating layer on the gate. The method as described in claim 5 further includes: forming a third doped region in the second well region extending from the top surface of the epitaxial layer to the top of the first doped region and the second doped region, wherein the first well region, the first doped region and the second doped region have a first conductivity type, and the second well region and the third doped region have a second conductivity type different from the first conductivity type. The method of claim 6 further includes: forming a dielectric layer on the epitaxial layer; forming a contact opening in the dielectric layer to expose the top surface of the epitaxial layer; and forming a fourth doped region in the second well region of the epitaxial layer through the contact opening, wherein the fourth doped region has the second conductivity type and is formed between two adjacent third trenches and between two adjacent fourth trenches. A semiconductor device comprises: a substrate, comprising a cell region and a connection region adjacent to the cell region; an epitaxial layer, arranged on the substrate and comprising a first well region adjacent to the substrate and a second well region on the first well region, the epitaxial layer comprising a plurality of first trenches in the cell region and extending to the first well region and a plurality of second trenches in the connection region and extending to the first well region, the bottom surface of the first trench being higher than the bottom surface of the second trench; a first doped region, arranged in the second well region adjacent to the sidewall of the first trench, wherein the first doped region and the first well region are arranged A portion of the second well region is separated therebetween; a second doped region is disposed in the second well region adjacent to the sidewall of the second trench and extends from the second well region to the first well region; and a third doped region is disposed in the second well region and extends from the top surface of the epitaxial layer to the top of the first doped region and the second doped region, wherein the substrate, the first well region, the first doped region and the second doped region have a first conductivity type, the second well region has a second conductivity type different from the first conductivity type, and the third doped region has the second conductivity type. The semiconductor device as described in claim 8 further includes: a dielectric layer disposed on the epitaxial layer; a conductive contact disposed in the dielectric layer and contacting the top surface of the epitaxial layer; and a fourth doped region disposed in the second well region of the epitaxial layer and contacting the conductive contact, wherein the fourth doped region has the second conductivity type and is disposed between two adjacent first trenches and between two adjacent second trenches.

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