TWI908361B - Semiconductor structure - Google Patents

Abstract

A semiconductor structure including a substrate, an interconnection layer, and a conductive component. The substrate includes a first surface and a second surface opposite to the first surface. The interconnection layer is disposed on the first surface of the substrate. The conductive component is disposed in the substrate and includes a conductive via structure and a dielectric structure surrounding the conductive via structure. The dielectric structure includes a first dielectric layer adjacent to the substrate and having a first coefficient of thermal expansion (CTE) and a second dielectric layer disposed on the first dielectric layer and having a second CTE. The conductive via structure includes a conductive via having a CTE greater than the second CTE, and the substrate has a CTE lower than the first CTE.

Description

Semiconductor structure

This invention relates to a semiconductor structure, and more particularly to a semiconductor structure including a through-substrate via (TSV).

Because the coefficient of thermal expansion (CTE) of the via material is mismatched with that of the substrate material, stress induced by the via occurs after high-temperature semiconductor manufacturing processes. Furthermore, when this stress is applied to the substrate near the via, it reduces the electrical performance of active components (e.g., transistors). Therefore, current practices involve creating a keep-out zone (KOZ) near the via, with active components not located within this zone, to prevent stress on the active components. However, since the keep-out zone occupies wafer space, minimizing the size of the keep-out zone remains an ongoing goal.

This invention provides a semiconductor structure in which the dielectric structure is designed to include a first dielectric layer having a first coefficient of thermal expansion and a second dielectric layer disposed between the first dielectric layer and a via structure having a second coefficient of thermal expansion greater than the first coefficient of thermal expansion. When the via structure includes a via with a coefficient of thermal expansion greater than the second coefficient of thermal expansion and the coefficient of thermal expansion of the substrate is less than the first coefficient of thermal expansion, the difference in coefficients of thermal expansion between the via structure and the substrate varies gradually. This helps to improve defects caused by coefficient of thermal expansion mismatch and helps to reduce the occupied area of the exclusion zone (KOZ).

One embodiment of the present invention provides a semiconductor structure including a substrate, an interconnect layer, and a conductive component. The substrate includes a first surface and a second surface opposite to the first surface. The interconnect layer is disposed on the first surface of the substrate. The conductive component is disposed in the substrate and includes a conductive via structure and a dielectric structure surrounding the conductive via structure. The dielectric structure includes a first dielectric layer and a second dielectric layer. The first dielectric layer is adjacent to the substrate and has a first coefficient of thermal expansion. The second dielectric layer is disposed between the first dielectric layer and the conductive via structure and has a second coefficient of thermal expansion greater than the first coefficient of thermal expansion. The conductive via structure includes a conductive via with a coefficient of thermal expansion greater than the second coefficient of thermal expansion, and the substrate has a coefficient of thermal expansion less than the first coefficient of thermal expansion.

In some embodiments, the conductive via structure includes an upper portion and a lower portion, with a dielectric structure separating the upper portion of the conductive via structure from the substrate, and the lower portion of the conductive via structure in contact with the substrate.

In some embodiments, the dielectric structure has a first depth extending from the first surface into the substrate, wherein the first depth is equal to or greater than the depth of the region in the substrate where the active element is formed.

In some embodiments, the upper portion of the conductive via structure is disposed in the interconnect layer, and a dielectric structure separates the upper portion of the conductive via structure from the interconnect layer.

In some embodiments, the first dielectric layer includes a portion extending below the bottom surface of the second dielectric layer and contacting the sidewall of the conductive via structure.

In some embodiments, the dielectric structure covers the sidewalls and bottom surface of the conductive via structure.

In some embodiments, the Young’s modulus of the first and second dielectric layers is greater than that of the substrate.

In some embodiments, the dielectric structure further includes a third dielectric layer disposed between the second dielectric layer and the via structure, wherein the third dielectric layer has a third coefficient of thermal expansion that is greater than the second coefficient of thermal expansion and less than the coefficient of thermal expansion of the via.

In some embodiments, the Young's modulus of the first, second, and third dielectric layers is greater than that of the substrate.

In some embodiments, the first dielectric layer includes a portion extending below the bottom surface of the second dielectric layer and contacting the sidewall of the conductive via structure, and the second dielectric layer includes a portion extending below the bottom surface of the third dielectric layer and contacting the sidewall of the conductive via structure.

Based on the above, in the semiconductor structure of this embodiment, the dielectric structure surrounding the via structure is designed to include a first dielectric layer having a first coefficient of thermal expansion and a second dielectric layer disposed between the first dielectric layer and the via structure having a second coefficient of thermal expansion greater than the first coefficient of thermal expansion. Since the via structure includes a via with a coefficient of thermal expansion greater than the second coefficient of thermal expansion and the substrate has a coefficient of thermal expansion less than the first coefficient of thermal expansion, the difference in coefficients of thermal expansion between the via structure and the substrate varies gradually. This can help improve the defects caused by the mismatch of coefficients of thermal expansion and can help reduce the occupied area of the exclusion zone (KOZ).

The invention is described more fully with reference to the figures of this embodiment. However, the invention may be embodied in various different forms and should not be limited to the embodiments described herein. The thickness of layers and regions in the figures is enlarged for clarity. The same or similar reference numerals denote the same or similar elements, which will not be repeated in the following paragraphs.

It should be understood that when a component is referred to as being "on" or "connected" to another component, it may be directly on or connected to the other component, or there may be an intermediate component. If a component is referred to as being "directly on" or "directly connected" to another component, then there is no intermediate component. As used herein, "connection" can refer to a physical and/or electrical connection, while "electrical connection" or "coupling" can refer to the presence of other components between two components. As used herein, "electrical connection" can include physical connections (e.g., wired connections) and physical disconnections (e.g., wireless connections).

As used herein, “about,” “approximately,” or “substantially” includes the value mentioned and the average value within an acceptable range of deviation from a specific value that can be determined by someone of ordinary skill in the art, taking into account the measurement under discussion and a specific number of errors associated with the measurement (i.e., limitations of the measurement system). For example, “about” may mean within one or more standard deviations of the value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, as used herein, “about,” “approximately,” or “substantially” may be used to select a more acceptable range of deviations or standard deviations depending on the optical, etchable, or other properties, rather than applying a single standard deviation to all properties.

The terminology used herein is for illustrative purposes only and is not intended to limit this disclosure. In such cases, the singular form includes the plural form unless otherwise defined in the context.

Figures 1A to 1E are schematic cross-sectional views of a method for forming a semiconductor structure according to an embodiment of the present invention.

In some embodiments, the method of forming a semiconductor structure (such as semiconductor structure 10 shown in FIG1E) may include the following steps.

First, referring to FIG. 1A, a substrate 100 is provided. The substrate 100 may include a first surface and a second surface opposite the first surface. The substrate 100 may include a semiconductor substrate or a semiconductor on insulator (SOI) substrate. The semiconductor material in the semiconductor substrate or SOI substrate may include elemental semiconductors, alloy semiconductors, or compound semiconductors. For example, elemental semiconductors may include Si or Ge. Alloy semiconductors may include SiGe, SiGeC, etc. Compound semiconductors may include SiC, group III-V semiconductor materials, or group II-VI semiconductor materials. III-V group semiconductor materials may include GaN, GaP, GaAs, AlN, AlP, AlAs, InN, InP, InAs, GaNP, GaNAs, GaPAs, AlNP, AlNAs, AlPAs, InNP, InNAs, InPAs, GaAlNP, GaAlNAs, GaAlPAs, GaInNP, GaInNAs, GaInPAs, InAlNP, InAlNAs, or InAlPAs. Group II-VI semiconductor materials may include CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, HgS, HgSe, HgTe, CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdZnS e. CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe or HgZnSTe. Semiconductor materials may be doped with a first conductivity type dopant or a second conductivity type dopant that complements the first conductivity type. For example, the first conductivity type may be P-type, and the second conductivity type may be N-type.

Next, a termination layer 110 and an interconnect layer 120 are sequentially formed on the substrate 100. The termination layer 110 may include a nitride (e.g., silicon nitride or silicon oxynitride). In some embodiments, the termination layer 110 may be, for example, a contact etch stop layer (CESL). The interconnect layer 120 may include a dielectric layer, a conductive layer, and a via formed by a back end of line (BEOL) process. The dielectric layer may include oxides, such as tetraethyl orthosilicate (TEOS), borophosphosilicate glass (BPSG), oxides formed by high-density plasma (HDP), undoped silicate glass (USG), phosphosilicate glass (PSG), oxides formed by spin coating such as spin-on glass (SOG) and spin-on dielectric (SOD), or oxides formed by a high aspect ratio process (HARP). The conductive layer and/or conductive vias may include conductive materials such as metals or metal alloys. Metals and metal alloys may be, for example, Cu, Al, Ti, Ta, W, Pt, Cr, Mo, or alloys thereof. The interconnect layer 120 shown in FIG1A may be a region in which a dielectric layer is formed, while the conductive layer and/or conductive vias of the interconnect layer 120 may be formed in other regions not shown in FIG1A.

Then, a mask pattern PR1 is formed on the interconnect layer 120 to define the location where the via hole VH1 will be formed subsequently. In some embodiments, the mask pattern PR1 may be a photoresist pattern, but is not limited thereto. Next, the portion of the interconnect layer 120 exposed by the mask pattern PR1, as well as the termination layer 110 and the substrate 100 located below said portion, are removed to form the via hole VH1. The via hole VH1 may have a first depth 100d1 in the substrate 100 extending from a first surface of the substrate 100 into the substrate 100. In some embodiments, the first depth 100d1 may be equal to or greater than the depth of the region in the substrate 100 where the active element is formed.

Then, referring to Figures 1A and 1B, after forming the via hole VH1, the masking pattern PR1 is removed. Next, a first dielectric material layer DLM1 and a second dielectric material layer DLM2 are sequentially formed on the interconnect layer 120. The first dielectric material layer DLM1 and the second dielectric material layer DLM2 extend into the via hole VH1 to cover the sidewalls and bottom surface of the via hole VH1. In this embodiment, the first dielectric material layer DLM1 and the second dielectric material layer DLM2 are conformally formed on the top surface of the interconnect layer 120 and the sidewalls and bottom surface of the via hole VH1. The first dielectric material layer DLM1 has a first coefficient of thermal expansion. The second dielectric material layer DLM2 has a second coefficient of thermal expansion greater than the first coefficient of thermal expansion. For example, the first dielectric layer DLM1 may comprise silicon nitride (e.g., _Si3N4 ) with a coefficient of thermal expansion of about 3.1 ppm/ _K , while the second dielectric layer DLM2 may comprise aluminum oxide (e.g., _Al2O3 ) with a coefficient of thermal expansion of about 8 ppm/ _K . In other embodiments, the second dielectric layer DLM2 may also be made of other ceramic materials with a coefficient of thermal expansion greater than that of the first dielectric layer DLM1.

Then, referring to Figures 1B and 1C, the first dielectric material layer DLM1 and the second dielectric material layer DLM2 located on the top surface of the interconnect layer 120 and the first dielectric material layer DLM1 and the second dielectric material layer DLM2 located on the bottom surface of the via hole VH1 can be removed by a process such as etch back to form a dielectric structure 130 containing the first dielectric layer DL1 and the second dielectric layer DL2 and expose the substrate 100.

Then, the via VH2 can be formed by self-alignment. For example, the interconnect layer 120 and the dielectric structure 130 can be used as a mask to remove the exposed substrate 100 through the via VH1 to form the via VH2. The via VH2 may have a second depth 100d2 extending from the first surface of the substrate 100 into the substrate 100. The second depth 100d2 may be greater than the first depth 100d1. The dimension of the via VH2 in the horizontal direction (e.g., the direction horizontal to the first surface of the substrate 100) is smaller than the dimension of the via VH1 in the horizontal direction.

Next, referring to Figures 1C and 1D, a conductive via structure 140 is formed in the via hole VH2. In some embodiments, the conductive via structure 140 may be formed by the following steps: First, a dielectric liner 142 is formed on the sidewalls and bottom surface of the via hole VH2. In some embodiments, the dielectric liner 142 may include an oxide (e.g., silicon oxide). Then, a barrier layer 144 is formed on the dielectric liner 142. In some embodiments, the barrier layer 144 may include titanium, titanium nitride, tantalum, tantalum nitride, or a combination thereof. Then, a conductive via 146 is formed on the barrier layer 144 to fill the remaining space of the via hole VH2. In some embodiments, the conductive via 146 may be formed by the following steps: First, a seed layer (not shown) is formed on the barrier layer 144. Then, the seed layer is grown by an electroplating process to form the conductive via 146 that fills the via hole VH2. In some embodiments, the conductive via 146 may comprise a conductive material such as a metal, for example, copper (Cu).

The coefficient of thermal expansion of the conductive via 146 (e.g., copper with a coefficient of thermal expansion of about 17 ppm/K) is greater than the second coefficient of thermal expansion of the second dielectric layer DL2 (e.g., _Al₂O₃ with a coefficient of thermal expansion of about 8 ppm/K), the second coefficient of thermal expansion of the second dielectric layer DL2 is greater than the first coefficient of thermal expansion of the first dielectric layer DL1 (e.g., _Si₃N₄ with a coefficient of thermal expansion of about 3.1 _ppm / _K ), and the first coefficient of thermal expansion of the first dielectric layer DL1 is greater than the coefficient of thermal expansion of the substrate 100 (e.g., Si with a coefficient of thermal expansion of about 2.5 ppm/K). In this way, the difference in thermal expansion coefficient between the conductive via structure 140 and the substrate 100 changes gradually, which helps to improve the defects caused by thermal expansion coefficient mismatch, thereby reducing the occupied area of the exclusion zone (KOZ).

In this embodiment, the thickness of the dielectric liner 142 and the barrier layer 144 in the conductive via structure 140 is less than the thickness of the dielectric structure 130, and the stress caused by the mismatch of the coefficients of thermal expansion of the dielectric liner 142 and the barrier layer 144 has no significant effect on the exclusion zone (KOZ).

Next, referring to Figures 1D and 1E, a wiring structure 150 is formed on the interconnect layer 120. The wiring structure 150 may include an insulating layer 152 and a wiring layer 154 formed in the insulating layer 152. The insulating layer 152 may include a first layer 152a and a second layer 152b sequentially formed on the interconnect layer 120. The material of the first layer 152a may be different from the material of the second layer 152b. For example, the first layer 152a may include a nitride (e.g., silicon nitride or silicon oxynitride), while the second layer 152b may include an oxide (e.g., silicon oxide or a dielectric with a low dielectric constant). The wiring layer 154 may be electrically connected to the via structure 140. Wiring layer 154 may include any suitable conductive material, such as copper, aluminum, titanium, nickel, gallium (Ga), ruthenium (Ru), tantalum (Ta), combinations or alloys of the above materials, but is not limited thereto. In some alternative embodiments, wiring structure 150 may include a structure formed by stacking more wiring layers and insulation layers.

The semiconductor structure 10 disclosed herein will be illustrated below with reference to Figure 1E. It should be noted that the semiconductor structure disclosed herein is not limited to being manufactured by the method described above for forming a semiconductor structure.

Referring to FIG1E, the semiconductor structure 10 includes a substrate 100, an interconnect layer 120, and a conductive component TSV. The substrate 100 includes a first surface and a second surface opposite to the first surface. The interconnect layer 120 is disposed on the first surface of the substrate 100. The conductive component TSV is disposed in the substrate 100 and includes a conductive via structure 140 and a dielectric structure 130 surrounding the conductive via structure 140. The dielectric structure 130 includes a first dielectric layer DL1 adjacent to the substrate 100 and having a first coefficient of thermal expansion, and a second dielectric layer DL2 disposed between the first dielectric layer DL1 and the conductive via structure 140 and having a second coefficient of thermal expansion greater than the first coefficient of thermal expansion. The via structure 140 includes a via 146 with a coefficient of thermal expansion greater than a second coefficient of thermal expansion, and the substrate 100 has a coefficient of thermal expansion less than a first coefficient of thermal expansion. In this way, the difference in coefficients of thermal expansion between the via structure 140 and the substrate 100 varies gradually, which helps to improve the defects caused by the mismatch of coefficients of thermal expansion, thereby reducing the occupied area of the exclusion zone (KOZ).

In some embodiments, the via structure 140 may include an upper portion and a lower portion, with a dielectric structure 130 separating the upper portion of the via structure 140 from the substrate 100, and the lower portion of the via structure 140 contacting the substrate 100. In this way, the dielectric structure 130 can reduce the impact of stress caused by thermal expansion mismatch on the active element while maintaining the desired resistive-capacitive delay (RC delay). In some embodiments, the dielectric structure 130 has a first depth 100d1 in the substrate 100 extending from the first surface into the substrate 100. The first depth 100d1 is equal to or greater than the depth of the region in the substrate 100 in which the active element is formed. This prevents the active components from being affected by stress caused by thermal expansion coefficient mismatch, thus helping to reduce the occupied area of the exclusion zone (KOZ).

In some embodiments, the conductive component TSV may be, for example, a via-middle substrate via. A via-middle refers to a substrate via formed after the formation of an active component such as a transistor, but this disclosure is not limited thereto. For example, in other embodiments, the conductive component TSV may also be a via-last substrate via, that is, a substrate via formed after the back end of line (BEOL). In some other embodiments, the conductive component TSV may also be a via-first substrate via, that is, a substrate via formed before the formation of an active component such as a transistor.

In this embodiment, the conductive component TSV can be a via-middle substrate through-hole, that is, the upper part of the conductive via structure 140 can be disposed in the interconnect layer 120, and the dielectric structure 130 can separate the upper part of the conductive via structure 140 from the interconnect layer 120.

In some embodiments, the first dielectric layer DL1 may include a portion extending below the bottom surface of the second dielectric layer DL2 and contacting the sidewall of the conductive via structure 140. In some embodiments, the Young's modulus of the first dielectric layer DL1 and the second dielectric layer DL2 may be greater than the Young's modulus of the substrate 100, thereby limiting the stress transmission of the conductive via 146 to the substrate 100. For example, the substrate 100 may include silicon with a Young's modulus of about 162 GPa, the first dielectric layer DL1 may be silicon nitride (e.g., _Si3N4 ) with a Young's modulus of about 300 GPa, and the second dielectric layer DL2 may be aluminum oxide (e.g., _Al2O3 ) with a Young's modulus of about 360 GPa. In _this way, the dielectric structure 130 may have sufficient mechanical strength to suppress _the stress caused by thermal expansion coefficient mismatch from the conductive via 146 to the substrate 100, thereby helping to reduce the occupied area of the exclusion zone (KOZ).

In some embodiments, no air gap is formed in the dielectric structure 130, thus avoiding the problem of poor heat transfer caused by the low thermal conductivity of the air gap (e.g., about 0.024 W/m*K).

Figure 2 is a cross-sectional schematic diagram of a semiconductor structure according to another embodiment of the present invention. The semiconductor structure 20 shown in Figure 2 is substantially the same as the semiconductor structure 10 shown in Figure 1. The only difference is that the dielectric structure 230 of the semiconductor structure 20 is different from the dielectric structure 130 of the semiconductor structure 10. Other identical or similar components are represented by the same or similar element symbols and will not be repeated here.

Referring to Figure 2, the dielectric structure 230 of the semiconductor structure 20 further includes a third dielectric layer DL3 disposed between the second dielectric layer DL2 and the via structure 140. The first dielectric layer DL1 may include a portion extending below the bottom surface of the second dielectric layer DL2 and contacting the sidewall of the via structure 140. The second dielectric layer DL2 may include a portion extending below the bottom surface of the third dielectric layer DL3 and contacting the sidewall of the via structure 140. The third dielectric layer DL3 may have a third coefficient of thermal expansion that is greater than the second coefficient of thermal expansion and less than the coefficient of thermal expansion of the via 146. For example, the conductive via 146 may include copper with a coefficient of thermal expansion of about 17 ppm/K, the third dielectric layer DL3 may include zirconium oxide (e.g., _ZrO2 ) with a coefficient of thermal expansion of about 10 ppm/K, and the second dielectric layer DL2 may include aluminum oxide (e.g., _Al2O3 ) with a coefficient of thermal expansion of about 8 ppm/ _K . In this way, the difference in coefficients of thermal expansion between the conductive via structure 140 and the substrate 100 exhibits a more gradual variation, which helps to mitigate defects caused by coefficient of thermal expansion mismatch, thereby reducing the occupied area of the exclusion zone (KOZ).

In some embodiments, the Young's modulus of the first dielectric layer DL1, the second dielectric layer DL2, and the third dielectric layer DL3 may be greater than the Young's modulus of the substrate 100, thereby limiting stress transmission from the conductive via 146 to the substrate 100. For example, the substrate 100 may include silicon with a Young's modulus of about 162 GPa, the first dielectric layer DL1 may be silicon nitride (e.g., _Si3N4 ) with a Young's modulus of about 300 GPa, the second dielectric layer DL2 may be aluminum oxide (e.g. _{, Al2O3} ) with a Young's modulus of about 360 GPa, and the third dielectric layer DL3 may be zirconium oxide (e.g., _ZrO2 ) with _a Young's modulus of about 250 GPa. In this way, the dielectric structure 230 can have sufficient mechanical strength to suppress the stress caused by thermal expansion coefficient mismatch from the conductive via 146 to the substrate 100, thereby helping to reduce the occupied area of the exclusion zone (KOZ).

Figure 3 is a cross-sectional schematic diagram of a semiconductor structure according to another embodiment of the present invention. The semiconductor structure 30 shown in Figure 3 is substantially the same as the semiconductor structure 10 shown in Figure 1. The only difference is that the dielectric structure 330 and the conductive via structure 240 of the semiconductor structure 30 are different from the dielectric structure 130 and the conductive via structure 140 of the semiconductor structure 10. Other identical or similar components are indicated by the same or similar element symbols and will not be repeated here.

Referring to Figure 3, the dielectric structure 330 of the semiconductor structure 30 extends to the second surface of the substrate 100 to cover the sidewalls and bottom surface of the conductive via structure 240. In this way, the first dielectric layer DL11 and/or the second dielectric layer DL22 of the dielectric structure 330 can also serve as the dielectric lining of the conductive via structure, so that the conductive via structure 240 formed subsequently omits the dielectric lining layer 142 shown in Figure 1E.

In summary, in the semiconductor structure of this embodiment, the dielectric structure is designed to include a first dielectric layer having a first coefficient of thermal expansion and a second dielectric layer disposed between the first dielectric layer and the via structure having a second coefficient of thermal expansion greater than the first coefficient of thermal expansion. When the via structure includes a via with a coefficient of thermal expansion greater than the second coefficient of thermal expansion and the coefficient of thermal expansion of the substrate is less than the first coefficient of thermal expansion, the difference in coefficients of thermal expansion between the via structure and the substrate changes gradually. This helps to improve the defects caused by the mismatch of coefficients of thermal expansion and helps to reduce the occupied area of the exclusion zone (KOZ).

10, 20, 30: Semiconductor structure 100: Substrate 100d1: First depth 100d2: Second depth 110: Termination layer 120: Interconnect layer 130, 230, 330: Dielectric structure 140, 240: Conductive via structure 142: Dielectric liner layer 144: Barrier layer 146: Conductive via 150: Wiring structure 152: Insulation layer 152a: First layer 152b: Second layer 154: Wiring layer DL1, DL11: First dielectric layer DL2, DL22: Second dielectric layer DL3: Third dielectric layer DLM1: First dielectric layer DLM2: Second dielectric layer PR1: Mask pattern TSV: Conductive component VH1, VH2: Through-holes

Figures 1A to 1E are schematic cross-sectional views of a method for forming a semiconductor structure according to one embodiment of the present invention. Figure 2 is a schematic cross-sectional view of a semiconductor structure according to another embodiment of the present invention. Figure 3 is a schematic cross-sectional view of a semiconductor structure according to yet another embodiment of the present invention.

100: Base

100d1: First Depth

100d2: Second Depth

110: Termination layer

120: Interconnect Layer

130: Dielectric structure

140: Conductive via structure

142: Dielectric Liner

144: Barrier Layer

146:Conductive via

DL1: First dielectric layer

DL2: Second dielectric layer

Claims (10)

A semiconductor structure includes: a substrate, including a first surface and a second surface opposite to the first surface; an interconnect layer disposed on the first surface of the substrate; and a conductive component disposed in the substrate and including a conductive via structure and a dielectric structure surrounding the conductive via structure, wherein the dielectric structure includes: a first dielectric layer adjacent to the substrate and having a first coefficient of thermal expansion; and a second dielectric layer disposed between the first dielectric layer and the conductive via structure and having a second coefficient of thermal expansion greater than the first coefficient of thermal expansion, wherein the conductive via structure includes a conductive via with a coefficient of thermal expansion greater than the second coefficient of thermal expansion, and the substrate has a coefficient of thermal expansion less than the first coefficient of thermal expansion. The semiconductor structure as claimed in claim 1, wherein the conductive via structure includes an upper portion and a lower portion, the dielectric structure separating the upper portion of the conductive via structure from the substrate, and the lower portion of the conductive via structure being in contact with the substrate. The semiconductor structure as claimed in claim 2, wherein the dielectric structure has a first depth in the substrate extending from the first surface into the substrate, the first depth being equal to or greater than the depth of the region in the substrate in which the active element is formed. The semiconductor structure as claimed in claim 2, wherein the upper portion of the conductive via structure is disposed in the interconnect layer, and the dielectric structure separates the upper portion of the conductive via structure from the interconnect layer. The semiconductor structure as claimed in claim 1, wherein the first dielectric layer includes a portion extending below the bottom surface of the second dielectric layer and contacting the sidewall of the conductive via structure. The semiconductor structure as described in claim 1, wherein the dielectric structure covers the sidewalls and bottom surface of the conductive via structure. The semiconductor structure as described in claim 1, wherein the Young’s modulus of the first dielectric layer and the second dielectric layer is greater than the Young’s modulus of the substrate and the conductive via. The semiconductor structure as claimed in claim 1, wherein the dielectric structure further includes a third dielectric layer disposed between the second dielectric layer structures, the third dielectric layer having a third coefficient of thermal expansion greater than the second coefficient of thermal expansion and less than the coefficient of thermal expansion of the conductive via. The semiconductor structure as described in claim 8, wherein the Young’s modulus of the first dielectric layer, the second dielectric layer and the third dielectric layer is greater than the Young’s modulus of the substrate. The semiconductor structure as described in claim 8, wherein the first dielectric layer includes a portion extending below the bottom surface of the second dielectric layer and contacting the sidewall of the conductive via structure, and the second dielectric layer includes a portion extending below the bottom surface of the third dielectric layer and contacting the sidewall of the conductive via structure.