TWI867873B - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

A semiconductor device includes a first electrode, a first isolation structure, a second electrode, a semiconductor structure, a gate dielectric layer and a gate electrode. The first isolation structure is located above a top surface of the first electrode. The second electrode is located above the first isolation structure. The semiconductor structure includes a first conductive region in contact with the top surface of the first electrode, a first channel region in contact with a first sidewall of the first isolation structure, and a second conductive region in contact with the second electrode. The gate dielectric layer is located on the semiconductor structure and has an opening. The gate is located on the gate dielectric layer and fills the opening to be electrically connected to the first electrode through the first conductive area.

Description

Semiconductor device and method for manufacturing the same

The present invention relates to a semiconductor device and a method for manufacturing the same.

At present, general thin film transistors usually use amorphous silicon semiconductors as channel materials. Due to the simple process and low cost of amorphous silicon semiconductors, they are widely used in various thin film transistors. However, with the continuous advancement of display technology, the resolution of display panels is also constantly improving. In order to reduce the size of thin film transistors in pixel circuits, many manufacturers are committed to developing semiconductor materials with higher carrier mobility, including metal oxide semiconductor materials.

The research and development of these new semiconductor materials aims to improve the performance of thin film transistors and thus enhance the overall performance of display devices. Metal oxide semiconductor materials have excellent electron mobility and can cope with the ever-increasing resolution requirements. Therefore, manufacturers use metal oxide semiconductors to achieve smaller and more efficient pixel configurations while ensuring continued improvement in display quality. This has also promoted technological innovation and process improvements in the field of semiconductor materials.

The present invention provides a semiconductor device and a method for manufacturing the same, wherein the semiconductor device has the advantage of occupying a small area.

At least one embodiment of the present invention provides a semiconductor device, which includes a first electrode, a first isolation structure, a second electrode, a semiconductor structure, a gate dielectric layer, and a gate. The first electrode is located on a substrate. The first isolation structure is located on a top surface of the first electrode. The second electrode is located on the first isolation structure. The semiconductor structure includes a first conductive region contacting the top surface of the first electrode, a first channel region contacting a first side wall of the first isolation structure, and a second conductive region contacting the second electrode. The gate dielectric layer is located on the semiconductor structure and has an opening. The gate is located on the gate dielectric layer and filled into the opening to be electrically connected to the first electrode through the first conductive region, and the first channel region, the gate dielectric layer and the gate are stacked in sequence on the first sidewall of the first isolation structure parallel to the first direction.

At least one embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising the following steps: forming a first electrode on a substrate; forming a first isolation structure and a second electrode, wherein the first isolation structure and the second electrode are sequentially stacked on the first electrode; forming a semiconductor structure on the second electrode, wherein the semiconductor structure includes a first conductive region contacting the top surface of the first electrode, a first channel region contacting the first sidewall of the first isolation structure, and a second conductive region contacting the second electrode; forming a gate dielectric layer on the semiconductor structure, wherein the gate dielectric layer has an opening. A gate is formed on the gate dielectric layer, wherein the gate is filled in the opening to be electrically connected to the first electrode through the first conductive region, and the first channel region, the gate dielectric layer and the gate are stacked in sequence on the first sidewall of the first isolation structure parallel to the first direction.

10A, 10B, 10C, 10D, 10E, 10F: semiconductor devices

11: First thin film transistor

11A: Thin film transistor series

12,12A: Second thin film transistor

100: Substrate

110: Gate dielectric layer

210: First electrode

210t,222t,224t: Top surface

220’: First conductive layer

222,222F: Second electrode

224,224F: Bottom gate

230’: Second conductive layer

232: Third electrode

240’: The third conductive layer

242: Fourth electrode

250’: Fourth conductive layer

252: Fifth electrode

300A, 300B, 300D, 300F: semiconductor structure

310: First isolation structure

310’: First isolation material layer

311A, 311B, 311D, 311F: First conductive area

312A, 312B, 312D, 312F: Second conductive area

313D,313F: The third conductive region

314D, 314F: Fourth conductive region

315D,315F: Fifth conductive zone

321A, 321B, 321D, 321F: First channel area

322D,322F: Second channel area

323D,323F: Third channel area

324D,324F: Fourth channel area

320: Second isolation structure

320’: Second isolation material layer

330: The third isolation structure

330’: The third isolation material layer

330B,330F: Channel area

340B,340F: Conductive area

340: The fourth isolation structure

340’: Fourth isolation material layer

402: Gate

404: Top Gate

406: Switching structure

500: Insulation structure

500’: Insulation material layer

510: Gate dielectric part

520: Isolation Department

600’: Electrode material layer

610: Source/Drain

D1: First direction

H1: First through hole

H2: Second through hole

HL: Dashed line

L, L1: length

ND: Normal direction

PR: Patterned photoresist layer

PR1: Part 1

PR2: Part 2

S1: First side wall

S2: Second side wall

t1: thickness

TH1: First opening

TH2: Second opening

TH3: The third opening

FIG1A is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

FIG1B is a schematic diagram of an equivalent circuit of the semiconductor device of FIG1A.

FIG2A is a schematic top view of a semiconductor device according to an embodiment of the present invention.

FIG2B is a schematic cross-sectional view along line A-A’ of FIG2A .

FIG3A is a schematic top view of a semiconductor device according to an embodiment of the present invention.

Figure 3B is a schematic cross-sectional view along line B-B’ of Figure 3A.

FIG3C is a schematic diagram of an equivalent circuit of the semiconductor device of FIG3B.

Figures 4A to 4F are cross-sectional schematic diagrams of a method for manufacturing the semiconductor device of Figure 3B.

FIG5A is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

FIG5B is a schematic diagram of an equivalent circuit of the semiconductor device of FIG5A.

FIG6 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

FIG7A is a schematic top view of a semiconductor device according to an embodiment of the present invention.

FIG7B is a schematic diagram of an equivalent circuit of the semiconductor device of FIG7A.

Figures 8A to 8E are cross-sectional schematic diagrams of a method for manufacturing the semiconductor device of Figure 7A.

FIG1A is a cross-sectional schematic diagram of a semiconductor device 10A according to an embodiment of the present invention. FIG1B is an equivalent circuit schematic diagram of the semiconductor device 10A of FIG1A. Referring to FIG1A, the semiconductor device 10A includes a first electrode 210, a first isolation structure 310, a second electrode 222, a semiconductor structure 300A, a gate dielectric layer 110, and a gate 402.

The substrate 100 is, for example, a rigid substrate, and its material may be glass, quartz, organic polymer or opaque/reflective material (e.g., conductive material, metal, wafer, ceramic or other applicable material) or other applicable material. However, the present invention is not limited thereto, and in other embodiments, the substrate 100 may also be a flexible substrate or a stretchable substrate. For example, the materials of the flexible substrate and the stretchable substrate include polyimide (PI), polydimethylsiloxane (PDMS), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyester (PES), polymethylmethacrylate (PMMA), polycarbonate (PC), polyurethane PU or other suitable materials.

The first electrode 210, the first isolation structure 310 and the second electrode 222 are stacked in sequence on the substrate 100 along the normal direction ND of the top surface of the substrate 100. In this embodiment, by stacking the first electrode 210, the first isolation structure 310 and the second electrode 222 on the substrate 100, the area required for setting the semiconductor device 10A can be effectively reduced.

The first electrode 210 is located on the substrate 100. In this embodiment, the first electrode 210 directly contacts the top surface of the substrate 100, but the present invention is not limited thereto. In other embodiments, a buffer layer (not released) may be additionally included between the first electrode 210 and the substrate 100, and the buffer layer is used, for example, as a hydrogen barrier layer and/or a metal ion barrier layer.

The first isolation structure 310 is located on the top surface 210t of the first electrode 210. In this embodiment, the first isolation structure 310 partially overlaps the first electrode 210.

The second electrode 222 is located on the first isolation structure 310. The first isolation structure 310 is located between the first electrode 210 and the second electrode 222.

In some embodiments, the materials of the first electrode 210 and the second electrode 222 include, for example, metals such as chromium, gold, silver, copper, tin, lead, uranium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, nickel, the above alloys, the above metal oxides, the above metal nitrides, or the above combinations or other conductive materials. The materials of the first electrode 210 and the second electrode 222 are the same or different. The first electrode 210 and the second electrode 222 can each have a single-layer structure or a multi-layer structure.

In some embodiments, the material of the first isolation structure 310 includes, for example, silicon oxide, silicon oxynitride, silicon nitride, aluminum oxide, ferrous oxide, zirconium oxide, or other suitable materials or combinations of the foregoing materials. In some embodiments, the material of the first isolation structure 310 includes oxide (e.g., silicon oxide) and can be used as an oxygen storage/oxygen replenishing layer, thereby adjusting the oxygen concentration in the semiconductor structure 300A during the manufacturing process. In some embodiments, the first isolation structure 310 can have a single-layer structure or a multi-layer structure. When the first isolation structure 310 has a multi-layer structure, an oxide layer (e.g., a silicon oxide layer) and a nitride layer (e.g., a silicon nitride layer) can be used in combination to optimize the performance of the semiconductor device 10A. For example, an oxide layer can be used as an oxygen storage/replenishing layer, while a nitride layer can be used as a hydrogen barrier layer or a metal ion barrier layer.

The semiconductor structure 300A extends continuously from the first electrode 210 to the second electrode 222. In this embodiment, the semiconductor structure 300A includes a first conductive region 311A contacting the top surface 210t of the first electrode 210, a first channel region 321A contacting the first sidewall S1 of the first isolation structure 310, and a second conductive region 312A contacting the second electrode 222. In this embodiment, the length L of the first channel region 321A is substantially equal to the thickness of the first isolation structure 310.

The first conductive region 311A, the first channel region 321A, and the second conductive region 312A have the same or different resistivities. In some embodiments, the first isolation structure 310 is used to provide oxygen elements to the first channel region 321A of the semiconductor structure 300A to reduce oxygen vacancies in the first channel region 321A, thereby making the resistivity of the first channel region 321A higher than the resistivity of the first conductive region 311A and the second conductive region 312A. However, the present invention is not limited thereto. In other embodiments, the first conductive region 311A, the first channel region 321A, and the second conductive region 312A have the same resistivity.

In some embodiments, the material of the semiconductor structure 300A includes an oxide containing three or more of gallium (Ga), zinc (Zn), indium (In), tin (Sn), aluminum (Al), and tungsten (W) (e.g., metal oxides such as indium gallium zinc tin oxide (IGZTO), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), aluminum zinc tin oxide (AZTO), indium tungsten zinc oxide (IWZO), and indium gallium oxide (IGO)) or a rare earth doped metal oxide (e.g., Ln-IZO) or other suitable metal oxides or a combination of the above materials. The semiconductor structure 300A has a single-layer structure or a multi-layer structure.

The gate dielectric layer 110 is located on the semiconductor structure 300A and has a first opening TH1. The material of the gate dielectric layer 110 includes silicon oxide, silicon oxynitride, silicon nitride, aluminum oxide, vanadium oxide, zirconium oxide or other suitable materials or a combination of the foregoing materials. In some embodiments, the thickness of the gate dielectric layer 110 is less than the thickness of the first isolation structure 310.

The gate 402 is located on the gate dielectric layer 110. The gate 402 overlaps the semiconductor structure 300A and extends continuously from above the second conductive region 312A to above the first conductive region 311A. The first channel region 321A, the gate dielectric layer 110 and the gate 402 are stacked in sequence on the first sidewall S1 of the first isolation structure 310 parallel to the first direction D1. The first direction D1 is, for example, perpendicular to the normal direction ND.

The gate 402 is filled in the first opening TH1 to be electrically connected to the first electrode 210 through the first conductive region 311A. In this embodiment, the thickness t1 of the first conductive region 311A at the bottom of the first opening TH1 is very thin, so the current can easily pass through the first conductive region 311A between the first electrode 210 and the gate 402 in the first opening TH1, so that the first electrode 210 is substantially electrically connected to the gate 402. In contrast, since the length L of the first channel region 321A is very large, the current can only pass through the first channel region 321A between the first electrode 210 and the second electrode 222 with the help of an external electric field. In some embodiments, the thickness t1 is 5 nm to 50 nm, and the length L is 100 nm to 1000 nm.

In some embodiments, the material of the gate 402 includes, for example, metals such as chromium, gold, silver, copper, tin, lead, uranium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, nickel, the above alloys, the above metal oxides, the above metal nitrides, or the above combinations or other conductive materials. The gate 402 may have a single-layer structure or a multi-layer structure.

In this embodiment, the equivalent circuit diagram of the semiconductor device 10A is shown in FIG1B . The semiconductor device 10A is a thin film transistor, and its gate 402 is electrically connected to the drain or source (i.e., the first electrode 210).

FIG2A is a schematic top view of a semiconductor device 10B according to an embodiment of the present invention. FIG2B is a schematic cross-sectional view along line A-A' of FIG2A. It must be noted that the embodiments of FIG2A and FIG2B use the component numbers and partial contents of the embodiments of FIG1A and FIG1B, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, which will not be elaborated here.

Please refer to FIG. 2A and FIG. 2B. In this embodiment, the first isolation structure 310 includes a first through hole H1 exposing the first sidewall S1. The second electrode 222 includes a second through hole H2 overlapping the first through hole H1 and exposing the second sidewall S2.

The first through hole H1 and the second through hole H2 overlap the first electrode 210, and the semiconductor structure 222 is filled in the first through hole H1 and the second through hole H2, and contacts the first side wall S1 and the second side wall S2. The first opening TH1 of the gate dielectric layer 110 is located in the first through hole H1 and close to the bottom of the first through hole H1. In this embodiment, in the top view, the first through hole H1 and the second through hole H2 are circular, but the present invention is not limited to this. In other embodiments, in the top view, the first through hole H1 and the second through hole H2 are rectangular, triangular, elliptical or other geometric shapes.

In some embodiments, the first isolation structure 310 is formed by etching the isolation material layer using the second electrode 222 as a mask, so that the orthographic projection pattern of the first isolation structure 310 on the substrate 100 is substantially equal to the orthographic projection pattern of the second electrode 222 on the substrate 100.

FIG3A is a schematic top view of a semiconductor device 10C according to an embodiment of the present invention. FIG3B is a schematic cross-sectional view along line B-B' of FIG3A. FIG3C is an equivalent circuit schematic of the semiconductor device 10C of FIG3B. It must be noted that the embodiments of FIG3A to FIG3C use the component numbers and partial contents of the embodiments of FIG1A and FIG1B, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical content is omitted. The description of the omitted part can be referred to the aforementioned embodiment, which will not be elaborated here.

3A and 3B , the semiconductor device 10C includes a first electrode 210, a first isolation structure 310, a second electrode 222, a bottom gate 224, an insulating structure 500, a source/drain 610, a semiconductor structure 300B, a gate dielectric layer 110, a gate 402, and a top gate 404.

The bottom gate 224 and the second electrode 222 are located on the first isolation structure 310. In this embodiment, the bottom gate 224 and the second electrode 222 belong to the same conductive layer. In this embodiment, the bottom gate 224 and the second electrode 222 are actually connected as one body and together define a second through hole H2. The second through hole H2 overlaps the first through hole H1 of the first isolation structure 310. In some embodiments, the bottom gate 224 and the second electrode 222 surround the second through hole H2 together, wherein the portion located on one side of the second through hole H2 (e.g., the portion on the left side of the dotted line HL in FIG. 3B ) is defined as the bottom gate 224, and the portion located on the other side of the second through hole H2 (e.g., the portion on the right side of the dotted line HL in FIG. 3B ) is defined as the second electrode 222.

In this embodiment, in the top view, the first through hole H1 and the second through hole H2 are rectangular, but the present invention is not limited thereto. In other embodiments, in the top view, the first through hole H1 and the second through hole H2 are circular, triangular, elliptical or other geometric shapes.

The insulating structure 500 is located on the bottom gate 224 and includes an isolation portion 520 and a gate dielectric portion 510 connected to the isolation portion 520. The gate dielectric portion 510 covers the sidewall of the bottom gate 224 (i.e., the second sidewall S2 of the second through hole H2 on the left side of the dotted line HL) and a portion of the first sidewall S1 of the first through hole H1 (i.e., the first sidewall S1 of the first through hole H1 on the left side of the dotted line HL), and does not cover the sidewall of the second electrode 222 (i.e., the second sidewall S2 of the second through hole H2 on the right side of the dotted line HL) and another portion of the first sidewall S1 of the first through hole H1 (i.e., the first sidewall S1 of the first through hole H1 on the right side of the dotted line HL). The isolation portion 520 covers the top surface 224t of the bottom gate 224 and does not cover the top surface 222t of the second electrode 222.

In some embodiments, the material of the insulating structure 500 includes silicon oxide, silicon oxynitride, silicon nitride, aluminum oxide, einsteinium oxide, zirconium oxide or other suitable materials or a combination of the foregoing materials. The insulating structure 500 and the first isolation structure 310 include the same or different materials.

The source/drain 610 is located on the isolation portion 520. In some embodiments, the material of the source/drain 610 includes, for example, metals such as chromium, gold, silver, copper, tin, lead, uranium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, nickel, the above alloys, the above metal oxides, the above metal nitrides, or the above combinations or other conductive materials. The source/drain 610 may have a single-layer structure or a multi-layer structure.

The semiconductor structure 300B extends continuously from the source/drain 610 along the insulating structure 500, the first electrode 210, the first isolation structure 310 to the second electrode 222.

The semiconductor structure 300B includes a first conductive region 311B contacting the first electrode 210, a first channel region 321B contacting the first sidewall S1 of the first isolation structure 310, a second conductive region 312B contacting the second electrode 222, a channel region 330B contacting the insulating structure 500, and a conductive region 340B contacting the source/drain 610. In this embodiment, the length L of the first channel region 321B is substantially equal to the thickness of the first isolation structure 310, and the length L1 of the channel region 330B is substantially equal to the thickness of the insulating structure 500.

The gate 402 and the top gate 404 are located on the gate dielectric layer 110 and are separated from each other. In some embodiments, the gate 402 and the top gate 404 belong to the same conductive layer. The gate dielectric layer 110, the channel region 330B of the semiconductor structure 300B, and the gate dielectric portion 510 of the insulating structure 500 are located between the bottom gate 224 and the top gate 404 in the first direction D1. In the present embodiment, at least one sidewall of the orthographic projection pattern of the semiconductor structure 300B on the substrate 100 (for example, corresponding to the left sidewall or the right sidewall of the semiconductor structure 300B in FIG. 3A ) is located between at least one sidewall of the orthographic projection pattern of the gate 402 on the substrate 100 (for example, corresponding to the left sidewall or the right sidewall of the gate 402 in FIG. 3A ) and the corresponding sidewall of the orthographic projection pattern of the second electrode 222 on the substrate 100, thereby reducing the parasitic capacitance between the gate 402 and the second electrode 222. Similarly, at least one sidewall of the orthographic projection pattern of the semiconductor structure 300B on the substrate 100 is located between at least one sidewall of the orthographic projection pattern of the top gate 404 on the substrate 100 (e.g., corresponding to the left sidewall or the right sidewall of the top gate 404 in FIG. 3A ) and the corresponding sidewall of the orthographic projection pattern of the source/drain 610 on the substrate 100, thereby reducing the parasitic capacitance between the top gate 404 and the source/drain 610.

Referring to FIG. 3B and FIG. 3C , part of the first electrode 210, part of the first isolation structure 310, the second electrode 222, part of the semiconductor structure 300B, part of the gate dielectric layer 110, and the gate 402 constitute the first thin film transistor 11. Another part of the first electrode 210, another part of the first isolation structure 310, the bottom gate 224, the insulating structure 500, another part of the semiconductor structure 300B, another part of the gate dielectric layer 110, and the top gate 404 constitute the second thin film transistor 12. In this embodiment, the first thin film transistor 11 has almost the same structure as the semiconductor device 10A of FIG. 1A .

In some embodiments, the semiconductor device 10C is applicable to a pixel circuit. For example, a pixel circuit for driving a light-emitting diode (such as an organic light-emitting diode). The top gate 404 is electrically connected to the drain of a switch element (not shown), wherein the gate of the switch element is electrically connected to a scanning line, and the source of the switch element is electrically connected to a data line. The switch element is used to control the opening and closing of the second thin film transistor 12. In some embodiments, the source/drain 610 of the second thin film transistor 12 is electrically connected to a first operating voltage (e.g., voltage VDD), the second electrode 222 of the first thin film transistor 11 is electrically connected to one of the electrodes of the light-emitting diode, and the other electrode of the light-emitting diode is electrically connected to a second operating voltage (e.g., voltage VSS).

In this embodiment, by setting up the semiconductor device 10C, the fluctuation caused by the noise of the data line signal provided to the top gate 404 through the aforementioned switching element can be reduced, thereby increasing the stability of the current output to the light-emitting diode.

4A to 4F are cross-sectional schematic diagrams of a method for manufacturing the semiconductor device 10C of FIG. 3B. Referring to FIG. 4A, a first electrode 210 is formed on a substrate 100. In some embodiments, a conductive layer is first formed on the substrate 100 over the entire surface, and then the conductive layer is patterned to form the first electrode 210. Then, a first isolation material layer 310' and a first conductive layer 220' are sequentially formed. The first isolation material layer 310' is formed on the first electrode 210. The first conductive layer 220' is formed on the first isolation material layer 310'.

Referring to FIG. 4B , the first conductive layer 220' is patterned to form a second electrode 222. In this embodiment, the first conductive layer 220' is patterned to form a second electrode 222 and a bottom gate 224 connected to each other.

In some embodiments, a patterned photoresist layer (not shown) is formed on the first conductive layer 220', and then the first conductive layer 220' is etched using the patterned photoresist layer as a mask to form the second electrode 222 and the bottom gate 224. The etching process is, for example, wet etching or dry etching.

Next, the first isolation material layer 310' is patterned to form a first isolation structure 310. The first isolation structure 310 and the second electrode 222 are sequentially stacked on the first electrode 210. Similarly, the first isolation structure 310 and the bottom gate 224 are sequentially stacked on the first electrode 210. In this embodiment, the first isolation material layer 310' is etched using the second electrode 222 and the bottom gate 224 as a mask to form the first isolation structure 310. The etching process is, for example, wet etching or dry etching.

In some embodiments, the patterned photoresist layer on the second electrode 222 and the bottom gate 224 is removed before or after patterning the first isolation material layer 310'. The method of removing the patterned photoresist layer includes, for example, an ashing process or other suitable processes.

Referring to FIG. 4C , an insulating material layer 500’ is formed on the second electrode 222 and the bottom gate 224, and the insulating material layer 500’ is filled into the first through hole H1 of the first isolation structure 310 and the second through hole H2 defined by the second electrode 222 and the bottom gate 224. An electrode material layer 600’ is formed on the insulating material layer 500’.

Referring to FIG. 4D , the electrode material layer 600' is patterned to form a source/drain 610. Next, the insulating material layer 500' is patterned to form an insulating structure 500. The insulating structure 500 includes an isolation portion 520 and a gate dielectric portion 510 connected to the isolation portion 520.

In some embodiments, a patterned photoresist layer PR is formed on the electrode material layer 600', and then the electrode material layer 600' is etched using the patterned photoresist layer PR as a mask to form a source/drain 610. The etching process is, for example, wet etching or dry etching.

In some embodiments, the insulating material layer 500' is etched using the source/drain 610 as a mask to form the insulating structure 500. The etching process is, for example, wet etching or dry etching.

In some embodiments, the patterned photoresist layer PR on the source/drain 610 is removed before or after the patterned insulating material layer 500'. The method of removing the patterned photoresist layer PR includes, for example, an ashing process or other suitable processes.

Referring to FIG. 4E , a semiconductor structure 300B is formed on the second electrode 222, the first isolation structure 310, the first electrode 210, the gate dielectric portion 510, the isolation portion 520, and the source/drain 610.

In some embodiments, after forming the semiconductor structure 300B, a first annealing process is performed to diffuse oxygen in the semiconductor structure 300B or the environment and store it in the first isolation structure 310 and/or the insulating structure 500.

Referring to FIG. 4F , a gate dielectric layer 110 is formed on the semiconductor structure 300B. The gate dielectric layer 110 has a first opening TH1 exposing the semiconductor structure 300B.

Finally, returning to FIG. 3A and FIG. 3B , a gate 402 and a top gate 404 are formed on the gate dielectric layer 110. The gate 402 is filled into the first opening TH1 to be electrically connected to the first electrode 210 through the first conductive region 311B. In some embodiments, a conductive layer (not shown) is first formed entirely on the gate dielectric layer 110, and then the conductive layer is patterned to form the gate 402 and the top gate 404.

FIG5A is a cross-sectional schematic diagram of a semiconductor device 10D according to an embodiment of the present invention. FIG5B is an equivalent circuit schematic diagram of the semiconductor device 10D of FIG5A. It must be noted that the embodiments of FIG5A and FIG5B follow the component numbers and partial contents of the embodiments of FIG1A and FIG1B, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical content is omitted. The description of the omitted part can be referred to the aforementioned embodiment, which will not be elaborated here.

Referring to FIG. 5A , in this embodiment, the semiconductor device 10D further includes a second isolation structure 320, a third electrode 232, a third isolation structure 330, a fourth electrode 242, a fourth isolation structure 340, and a fifth electrode 252.

The first isolation structure 310 is located on the first electrode 210. The second electrode 222 is located on the first isolation structure 310. The second isolation structure 320 is located on the second electrode 222. The third electrode 232 is located on the second isolation structure 320. The third isolation structure 330 is located on the third electrode 232. The fourth electrode 242 is located on the third isolation structure 330. The fourth isolation structure 340 is located on the fourth electrode 242. The fifth electrode 252 is located on the fourth isolation structure 340.

The first electrode 210, the first isolation structure 310, the second electrode 222, the second isolation structure 320, the third electrode 232, the third isolation structure 330, the fourth electrode 242, the fourth isolation structure 340 and the fifth electrode 252 are stacked in sequence above the substrate 100 along the normal direction ND of the top surface of the substrate 100. In this embodiment, the first electrode 210, the first isolation structure 310, the second electrode 222, the second isolation structure 320, the third electrode 232, the third isolation structure 330, the fourth electrode 242, the fourth isolation structure 340 and the fifth electrode 252 are stacked on the substrate 100 to effectively reduce the area required for setting up the semiconductor device 10D.

In some embodiments, the materials of the first electrode 210, the second electrode 222, the third electrode 232, the fourth electrode 242, and the fifth electrode 252 include, for example, metals such as chromium, gold, silver, copper, tin, lead, cobalt, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, nickel, their alloys, their metal oxides, their metal nitrides, or their combinations or other conductive materials. The materials of the first electrode 210, the second electrode 222, the third electrode 232, the fourth electrode 242, and the fifth electrode 252 are the same or different from each other. The first electrode 210, the second electrode 222, the third electrode 232, the fourth electrode 242, and the fifth electrode 252 may each have a single-layer structure or a multi-layer structure.

In some embodiments, the materials of the first isolation structure 310, the second isolation structure 320, the third isolation structure 330, and the fourth isolation structure 340 include, for example, silicon oxide, silicon oxynitride, silicon nitride, aluminum oxide, einsteinium oxide, zirconium oxide, or other suitable materials or combinations of the foregoing materials. In some embodiments, the materials of the first isolation structure 310, the second isolation structure 320, the third isolation structure 330, and the fourth isolation structure 340 include oxides (e.g., silicon oxide) and can be used as oxygen storage/oxygen replenishing layers, thereby adjusting the oxygen concentration in the semiconductor structure 300D during the manufacturing process. In some embodiments, the first isolation structure 310, the second isolation structure 320, the third isolation structure 330, and the fourth isolation structure 340 may each have a single-layer structure or a multi-layer structure. When the first isolation structure 310, the second isolation structure 320, the third isolation structure 330, and the fourth isolation structure 340 each have a multi-layer structure, an oxide layer (e.g., a silicon oxide layer) and a nitride layer (e.g., a silicon nitride layer) may be used in combination to optimize the performance of the semiconductor device 10D. For example, the oxide layer may be used as an oxygen storage/replenishing layer, and the nitride layer may be used as a hydrogen barrier layer or a metal ion barrier layer.

The semiconductor structure 300D extends continuously from the first electrode 210 to the fifth electrode 252. In this embodiment, the semiconductor structure 300D includes a first conductive region 311D contacting the first electrode 210, a first channel region 321D contacting the first isolation structure 310, a second conductive region 312D contacting the second electrode 222, a second channel region 322D contacting the sidewall of the second isolation structure 320, a third conductive region 313D contacting the sidewall of the third electrode 232, a third channel region 323D contacting the sidewall of the third isolation structure 330, a fourth conductive region 314D contacting the sidewall of the fourth electrode 242, a fourth channel region 324D contacting the sidewall of the fourth isolation structure 340, and a fifth conductive region 315D contacting the fifth electrode 252.

The first conductive region 311D, the first channel region 321D, the second conductive region 312D, the second channel region 322D, the third conductive region 313D, the third channel region 323D, the fourth conductive region 314D, the fourth channel region 324D and the fifth conductive region 315D are connected in sequence.

The first conductive region 311D, the first channel region 321D, the second conductive region 312D, the second channel region 322D, the third conductive region 313D, the third channel region 323D, the fourth conductive region 314D, the fourth channel region 324D, and the fifth conductive region 315D have the same or different resistivities. In some embodiments, the first isolation structure 310 to the fourth isolation structure 340 are used to provide oxygen elements to the first channel region 321D to the fourth channel region 324D of the semiconductor structure 300D to reduce oxygen vacancies in the first channel region 321D to the fourth channel region 324D, thereby making the resistivity of the first channel region 321D to the fourth channel region 324D higher than the resistivity of the first conductive region 311D to the fifth conductive region 315D. However, the present invention is not limited thereto. In other embodiments, the first channel region 321D to the fourth channel region 324D and the first conductive region 311D to the fifth conductive region 315D have the same resistivity.

In this embodiment, the equivalent circuit diagram of the semiconductor device 10D is shown in FIG5B. The semiconductor device 10D is substantially equivalent to a plurality of thin film transistors connected in series, wherein the thin film transistors share a gate 402, and the gate 402 is electrically connected to the drain or source (i.e., the first electrode 210) of the first thin film transistor.

In this embodiment, the semiconductor device 10D includes the third electrode 232 to the fifth electrode 252 and the second isolation structure 320 to the fourth isolation structure 340, but the present invention is not limited thereto. The number of electrodes and isolation structures stacked on the second electrode 222 can be adjusted according to demand. For example, in other embodiments, the third isolation structure 330, the fourth electrode 242, the fourth isolation structure 340 and the fifth electrode 252 can be omitted. In other embodiments, the fourth isolation structure 340 and the fifth electrode 252 can be omitted. In other embodiments, more electrodes and isolation structures can be included on the fifth electrode 252.

FIG6 is a schematic top view of a semiconductor device 10E according to an embodiment of the present invention. It must be noted that the embodiment of FIG6 uses the component numbers and partial contents of the embodiments of FIG5A and FIG5B, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, which will not be elaborated here.

Referring to FIG. 6 , in the semiconductor device 10E, the through hole of the first isolation structure 310, the through hole of the second electrode 222, the through hole of the second isolation structure 320, the through hole of the third electrode 232, the through hole of the third isolation structure 330, the through hole of the fourth electrode 242, the through hole of the fourth isolation structure 340, and the through hole of the fifth electrode 252 overlap, and the semiconductor structure 300D is filled in the aforementioned through holes.

FIG. 7A is a cross-sectional schematic diagram of a semiconductor device 10F according to an embodiment of the present invention. FIG. 7B is an equivalent circuit schematic diagram of the semiconductor device 10F of FIG. 7A. In this embodiment, the semiconductor device 10F is substantially equivalent to a thin film transistor series 11A and a second thin film transistor 12A connected together. The structure of the thin film transistor series 11A is similar to the semiconductor device 10D of FIG. 5A, so the structure of the thin film transistor series 11A can refer to FIG. 5A and related descriptions. The structure of the second thin film transistor 12A is similar to the second thin film transistor 12 of FIG. 3B, so the structure of the second thin film transistor 12A can refer to FIG. 3B and related descriptions.

Please refer to FIG. 7A. In this embodiment, although the bottom gate 224F and the second electrode 222F belong to the same conductive layer, the bottom gate 224F and the second electrode 222F are separated from each other. Instead, the transfer structure 406 electrically connects the bottom gate 224F to the fifth electrode 252. The transfer structure 406 extends continuously from above the bottom gate 224F to above the fifth electrode 252. In other words, the transfer structure 406 on the leftmost side of FIG. 7A is actually connected to the transfer structure 406 on the rightmost side, and FIG. 7A omits the connection path between the two.

In some embodiments, the transfer structure 406, the top gate 404, and the gate 402 belong to the same conductive layer and are separated from each other. The transfer structure 406 is connected to the fifth electrode 252 through the second opening TH2 in the gate dielectric layer 110, and is connected to the bottom gate 224F through the third opening TH3 in the gate dielectric layer 110, wherein the third opening TH3 extends through the gate dielectric layer 110.

In this embodiment, the semiconductor structure 300F extends continuously from the source/drain 610 along the insulating structure 500, the first electrode 210, the first isolation structure 310, the second electrode 222F, the second isolation structure 320, the third electrode 232, the third isolation structure 330, the fourth electrode 242, and the fourth isolation structure 340 to the fifth electrode 252.

The semiconductor structure 300F includes a first conductive region 311F contacting the first electrode 210, a first channel region 321F contacting the first isolation structure 310, a second conductive region 312F contacting the second electrode 222F, a second channel region 322F contacting the second isolation structure 320, a third conductive region 313F contacting the third electrode 232, and a third conductive region 314F contacting the third isolation structure 320. The third channel region 323F of the three isolation structures 330, the fourth conductive region 314F contacting the fourth electrode 242, the fourth channel region 324F contacting the fourth isolation structure 340, the fifth conductive region 315F contacting the fifth electrode 252, the channel region 330F contacting the insulating structure 500, and the conductive region 340F contacting the source/drain 610.

8A to 8E are cross-sectional schematic diagrams of the manufacturing method of the semiconductor device 10F of FIG. 7A. Referring to FIG. 8A, a first isolation material layer 310', a first conductive layer 220', a second isolation material layer 320', a second conductive layer 230', a third isolation material layer 330', a third conductive layer 240', a fourth isolation material layer 340', a fourth conductive layer 250' and a patterned photoresist pattern PR are sequentially formed above the first electrode 210.

In this embodiment, the patterned photoresist pattern PR includes a first portion PR1 and a second portion PR2 having different thicknesses. The first portion PR1 is separated from the second portion PR2. In this embodiment, the thickness of the first portion PR1 is greater than the thickness of the second portion PR2.

Referring to FIG. 8B , the patterned photoresist pattern PR is used as a mask to perform one or more etching processes on the fourth conductive layer 250’, the fourth isolation material layer 340’, the third conductive layer 240’, the third isolation material layer 330’, the second conductive layer 230’, the second isolation material layer 320’, the first conductive layer 220’ and the first isolation material layer 310’ to form the first isolation structure 310, the second electrode 222F, the second isolation structure 320, the third electrode 232, the third isolation structure 330, the fourth electrode 242, the fourth isolation structure 340 and the fifth electrode 252 stacked in sequence.

In this embodiment, the first conductive layer 220' forms a second electrode 222F and a bottom gate 224F separated from each other after an etching process.

During the etching process, the fourth conductive layer 250', the fourth isolation material layer 340', the third conductive layer 240', the third isolation material layer 330', the second conductive layer 230', the second isolation material layer 320', the first conductive layer 220' and the first isolation material layer 310' that are not shielded by the first portion PR1 and the second portion PR2 are all removed, and the first electrode 210 is exposed.

In the etching process, the fourth conductive layer 250', the fourth isolation material layer 340', the third conductive layer 240', the third isolation material layer 330', the second conductive layer 230', the second isolation material layer 320', the first conductive layer 220' and the area of the first isolation material layer 310' shielded by the second portion PR2 are etched to the first conductive layer 220', and the stacked structure of the first isolation structure 310 and the bottom gate 224F is left.

During the etching process, the fourth conductive layer 250', the fourth isolation material layer 340', the third conductive layer 240', the third isolation material layer 330', the second conductive layer 230', the second isolation material layer 320', the first conductive layer 220' and the area of the first isolation material layer 310' shielded by the first part PR1 are not etched, and the stacked structure of the first isolation structure 310, the second electrode 222F, the second isolation structure 320, the third electrode 232, the third isolation structure 330, the fourth electrode 242, the fourth isolation structure 340 and the fifth electrode 252 is left.

Please refer to FIG. 8C , an insulating structure 500 and a source/drain 610 are formed on the bottom gate 224F. The method of forming the insulating structure 500 and the source/drain 610 can refer to the process steps described in FIG. 4C and FIG. 4D , which will not be described in detail here.

Please refer to FIG. 8D to form a semiconductor structure 300F.

In some embodiments, after forming the semiconductor structure 300F, a first annealing process is performed to diffuse oxygen in the semiconductor structure 300F or the environment and store it in the first isolation structure 310, the second isolation structure 320, the third isolation structure 330, the fourth isolation structure 340 and/or the insulating structure 500.

Referring to FIG. 8E , a gate dielectric layer 110 is formed on the semiconductor structure 300F. In some embodiments, a dielectric material layer is deposited on the semiconductor structure 300F, the insulating structure 500, and the fifth electrode 252, and then an etching process is performed on the dielectric material layer to form a gate dielectric layer 110 including a first opening TH1, a second opening TH2, and a third opening TH3. The first opening TH1 exposes the semiconductor structure 300F. The second opening TH2 exposes the fifth electrode 252. The third opening TH3 exposes the bottom electrode 224F.

Finally, returning to FIG. 7A and FIG. 7B , a gate 402, a top gate 404, and a transfer structure 406 are formed on the gate dielectric layer 110. The gate 402 is filled into the first opening TH1 to be electrically connected to the first electrode 210 through the first conductive region 311E. The transfer structure 406 is filled into the second opening TH2 and the third opening TH3 to be electrically connected to the fifth electrode 252 and the bottom gate 224F. In some embodiments, a conductive layer (not shown) is first formed on the gate dielectric layer 110 in its entirety, and then the conductive layer is patterned to form the gate 402, the top gate 404, and the transfer structure 406.

In summary, the present invention can reduce the footprint of semiconductor devices through the stacking design of isolation structures and electrodes, so more semiconductor devices can be arranged on a substrate of the same area.

10A: Semiconductor devices

100: Substrate

110: Gate dielectric layer

210: First electrode

210t: Top

222: Second electrode

300A:Semiconductor structure

310: First isolation structure

311A: First conductive area

312A: Second conductive area

321A: First channel area

402: Gate

D1: First direction

L: Length

ND: Normal direction

S1: First side wall

t1: thickness

TH1: First opening

Claims (9)

A semiconductor device includes: a first electrode located on a substrate; a first isolation structure located on the top surface of the first electrode, wherein the first isolation structure includes a first through hole exposing a first side wall, wherein the first through hole overlaps the first electrode; a second electrode located on the first isolation structure; a semiconductor structure filled in the first through hole and including a first conductive region contacting the top surface of the first electrode , a first channel region contacting the first sidewall and a second conductive region contacting the second electrode; a gate dielectric layer located on the semiconductor structure and having an opening; and a gate electrode located on the gate dielectric layer and filled in the opening to be electrically connected to the first electrode through the first conductive region, and the first channel region, the gate dielectric layer and the gate electrode are stacked in sequence on the first sidewall of the first isolation structure parallel to a first direction. The semiconductor device as described in claim 1 further comprises: a bottom gate located on the first isolation structure and connected to the second electrode; an insulating structure located on the bottom gate and comprising an isolation portion and a gate dielectric portion connected to the isolation portion, wherein the gate dielectric portion covers the sidewalls of the bottom gate and the isolation portion covers the top surface of the bottom gate; a source/drain , located on the isolation portion, wherein the semiconductor structure extends continuously from the source/drain along the insulating structure, the first electrode and the first isolation structure to the second electrode; and a top gate, located on the gate dielectric layer, and the gate dielectric layer, the semiconductor structure and the gate dielectric portion are located between the bottom gate and the top gate in the first direction. A semiconductor device as described in claim 2, wherein the insulating structure covers a portion of the first through hole. The semiconductor device as described in claim 1 further comprises: a second isolation structure located on the second electrode; a third electrode located on the second isolation structure; a third isolation structure located on the third electrode; a fourth electrode located on the third isolation structure; a fourth isolation structure located on the fourth electrode; and a fifth electrode located on the fourth isolation structure, wherein the semiconductor structure comprises a second channel region contacting the sidewall of the second isolation structure, a second channel region contacting the sidewall of the second isolation structure, and a third channel region contacting the sidewall of the second isolation structure. A third conductive region of the third electrode, a third channel region contacting the sidewall of the third isolation structure, a fourth conductive region contacting the fourth electrode, a fourth channel region contacting the sidewall of the fourth isolation structure, and a fifth conductive region contacting the fifth electrode, wherein the first conductive region, the first channel region, the second conductive region, the second channel region, the third conductive region, the third channel region, the fourth conductive region, the fourth channel region, and the fifth conductive region are sequentially connected. The semiconductor device as described in claim 4 further includes: a bottom gate located on the first isolation structure; an insulating structure located on the bottom gate and including an isolation portion and a gate dielectric portion connected to the isolation portion, wherein the gate dielectric portion covers the sidewalls of the bottom gate and the isolation portion covers the top surface of the bottom gate; a source/drain located on the isolation portion, wherein the semiconductor structure extends from the source/drain along the insulating structure, the first electrode, the first isolation structure, the The second electrode, the second isolation structure, the third electrode, the third isolation structure, the fourth electrode and the fourth isolation structure extend continuously to the fifth electrode; a top gate located on the gate dielectric layer, and the gate dielectric layer, the semiconductor structure and the gate dielectric portion are located between the bottom gate and the top gate in the first direction; and a transfer structure electrically connecting the bottom gate to the fifth electrode, wherein the transfer structure, the top gate and the gate belong to the same conductive layer. A method for manufacturing a semiconductor device includes: forming a first electrode on a substrate; forming a first isolation structure and a second electrode, wherein the first isolation structure and the second electrode are sequentially stacked on the first electrode, wherein the first isolation structure includes a first through hole exposing a first side wall, wherein the first through hole overlaps the first electrode; forming a semiconductor structure on the second electrode, wherein the semiconductor structure is filled in the first through hole, and the semiconductor structure includes a contact with the first side wall; A first conductive region on the top surface of an electrode, a first channel region contacting the first sidewall, and a second conductive region contacting the second electrode; A gate dielectric layer is formed on the semiconductor structure, and the gate dielectric layer has an opening; a gate is formed on the gate dielectric layer, wherein the gate is filled in the opening to be electrically connected to the first electrode through the first conductive region, and the first channel region, the gate dielectric layer and the gate are stacked in sequence on the first sidewall of the first isolation structure parallel to a first direction. The manufacturing method as described in claim 6, wherein the method of forming the first isolation structure and the second electrode includes: forming a first isolation material layer on the first electrode; forming a conductive layer on the first isolation material layer; patterning the conductive layer to form the second electrode; patterning the first isolation material layer to form the first isolation structure. The manufacturing method as described in claim 7 further includes: patterning the conductive layer to form the second electrode and a bottom gate connected to each other; using the second electrode and the bottom gate as a mask, patterning the first isolation material layer to form the first isolation structure; forming an insulating material layer on the second electrode and the bottom gate, and filling the insulating material layer into the first through hole; forming an electrode material layer on the insulating material layer; patterning the electrode material layer to form a source/drain; patterning the insulating material layer to form An insulating structure, wherein the insulating structure includes an isolation portion and a gate dielectric portion connected to the isolation portion, wherein the gate dielectric portion covers the sidewall of the bottom gate, and the isolation portion covers the top surface of the bottom gate; the semiconductor structure is formed on the second electrode, the first isolation structure, the first electrode, the gate dielectric portion, and the source/drain; and a top gate is formed on the gate dielectric layer, and the gate dielectric layer, the semiconductor structure, and the gate dielectric portion are located between the bottom gate and the top gate in the first direction. The manufacturing method as described in claim 6, wherein the method of forming the first isolation structure and the second electrode comprises: sequentially forming a first isolation material layer, a first conductive layer, a second isolation material layer, a second conductive layer, a third isolation material layer, a third conductive layer, a fourth isolation material layer, a fourth conductive layer and a patterned photoresist pattern on the first electrode, wherein the patterned photoresist pattern comprises a first portion and a second portion having different thicknesses, wherein the first portion is separated from the first electrode. The second part; and using the patterned photoresist pattern as a mask, performing one or more etching processes on the fourth conductive layer, the fourth isolation material layer, the third conductive layer, the third isolation material layer, the second conductive layer, the second isolation material layer, the first conductive layer and the first isolation material layer to form the first isolation structure, the second electrode, a second isolation structure, a third electrode, a third isolation structure, a fourth electrode, a fourth isolation structure and a fifth electrode stacked in sequence.

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