TWI874057B - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

A semiconductor device includes a first source/drain electrode, an isolation structure, a second source/drain electrode, a semiconductor structure, a gate dielectric layer and a gate electrode. The first source/drain electrode has a groove recessed from the top surface. The isolation structure is located on the first source/drain electrode, partially fills the groove, and covers the sidewalls of the groove. The isolation structure includes a filling portion and an isolation portion. The filling portion is located in the groove and has a first through hole. The isolation portion is located on the filling portion and on the top surface of the first source/drain electrode outside the groove. The second source/drain electrode is located on the isolation portion. The semiconductor structure extends from the second source/drain electrode into the first through hole and the groove to electrically connect the second source/drain electrode and the first source/drain electrode.

Description

Semiconductor device and method for manufacturing the same

The present invention relates to a semiconductor device and a method for manufacturing the same.

At present, common thin film transistors usually use amorphous silicon semiconductors as channel materials. Amorphous silicon semiconductors are widely used in various thin film transistors because of their simple process and low cost. With the continuous advancement of display technology, the resolution of display panels is also increasing year by year. In order to reduce the size of thin film transistors in pixel circuits, many manufacturers are committed to developing new high carrier mobility semiconductor materials, such as metal oxide semiconductor materials.

The present invention provides a semiconductor device and a manufacturing method thereof. In addition to having the advantage of low footprint, the semiconductor device can also improve the problem of drain induced barrier lowering (DIBL).

At least one embodiment of the present invention provides a semiconductor device, which includes a first source/drain, an isolation structure, a second source/drain, a semiconductor structure, a gate dielectric layer, and a gate. The first source/drain is located on a substrate and has a groove. The groove is recessed from the top surface of the first source/drain. The isolation structure is located on the first source/drain and partially fills the groove and covers the sidewalls of the groove. The isolation structure includes a filling portion and an isolation portion. The filling portion is in the groove and has a first through hole. The isolation portion is on the filling portion and on the top surface of the first source/drain outside the groove. The second source/drain is located on the isolation portion. The semiconductor structure extends from the second source/drain into the first through hole and the groove to electrically connect the second source/drain and the first source/drain. The gate dielectric layer is located on the semiconductor structure. The gate is located on the gate dielectric layer.

At least one embodiment of the present invention provides a method for manufacturing a thin film transistor, comprising the following steps. A first source/drain having a groove is formed. The groove is recessed from the top surface of the first source/drain. An isolation material layer is formed on the first source/drain and covers the groove. A conductive layer is formed on the isolation material layer. The conductive layer is patterned to form a second source/drain. The isolation material layer is patterned to form an isolation structure. The isolation structure partially fills the groove and covers the sidewalls of the groove. The isolation structure includes a filling portion and an isolation portion. The filling portion is in the groove and has a first through hole. The isolation portion is on the filling portion and on the top surface of the first source/drain outside the groove. A semiconductor structure is formed, extending from the second source/drain into the first through hole and the groove to electrically connect the second source/drain and the first source/drain. A gate dielectric layer is formed on the semiconductor structure. A gate is formed on the gate dielectric layer.

10A, 10B, 10C, 10D, 10E, 10F, 10G, 10H, 101, 10J, 10K, 10L: semiconductor devices

100: Substrate

110: Buffer layer

210: First source/drain

210’: Electrode material layer

210”: Intermediate electrode structure

211: First electrode structure

211A, 211B, 211C, 211D: first electrode layer

211H: Opening

211A,,211B’,211C’: first electrode material layer

211D’, 211E’: electrode material layer

211E”: Intermediate electrode layer

211F: Third electrode layer

212: Groove

212a,314a,S1,S2: Side wall

212b: Outer side wall

212c: Top

212d: Bottom surface

213,211E: Second electrode layer

213’: Second electrode material layer

220: Second source/drain

220’: Conductive layer

310: Isolation structure

310’: Isolation material layer

312: Filling section

312c,314c: Upper surface

314: Isolation Department

320: Gate dielectric layer

400:Semiconductor structure

500: Gate

D1: First direction

D2: Second direction

DT1, DT2: Depth

H1: First through hole

H2: Second through hole

HD1, HD2, X1, X2: thickness

P1, P1’: thick part

P2: Thin part

PR1,PR2,PR3,PR4: patterned photoresist layer

Y: horizontal distance

FIG1A is a schematic top view of a semiconductor device according to an embodiment of the present invention.

FIG1B is a schematic cross-sectional view along line A-A’ of FIG1A .

FIG1C is a schematic diagram of an equivalent circuit of the semiconductor device of FIG1B .

Figures 2A to 2H are cross-sectional schematic diagrams of a method for manufacturing the semiconductor device of Figure 1B.

FIG3 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

Figures 4A to 4E are simulation diagrams of semiconductor devices according to some embodiments of the present invention.

FIG. 5A and FIG. 5B are Id-Vg characteristic curves of semiconductor devices according to some embodiments of the present invention.

FIG. 6A and FIG. 6B are Id-Vd characteristic curves of semiconductor devices according to some embodiments of the present invention.

FIG7 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

Figures 8A to 8D are cross-sectional schematic diagrams of a method for manufacturing the first source/drain of the semiconductor device of Figure 7.

FIG9 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

FIG10 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

Figures 11A to 11D are cross-sectional schematic diagrams of a method for manufacturing the first source/drain of the semiconductor device of Figure 10.

FIG12 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

FIG13 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

FIG1A is a schematic top view of a semiconductor device 10A according to an embodiment of the present invention. FIG1B is a schematic cross-sectional view along line A-A' of FIG1A. Referring to FIG1A and FIG1B, the semiconductor device 10A includes a first source/drain 210, an isolation structure 310, a second source/drain 220, a semiconductor structure 400, a gate dielectric layer 320, and a gate 500.

The substrate 100 is, for example, a rigid substrate, and its material may be glass, quartz, organic polymer or opaque/reflective material (e.g., conductive material, metal, wafer, ceramic or other applicable material) or other applicable materials. However, the present invention is not limited thereto. In other embodiments, the substrate 100 may also be a flexible substrate or a stretchable substrate. For example, the materials of the flexible substrate and the stretchable substrate include polyimide (PI), polydimethylsiloxane (PDMS), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyester (PES), polymethylmethacrylate (PMMA), polycarbonate (PC), polyurethane PU or other suitable materials.

In this embodiment, the first source/drain 210, the isolation structure 310, the second source/drain 220 and the semiconductor structure 400 are stacked in sequence in the first direction D1. The first direction D1 is, for example, the normal direction of the top surface of the substrate 100.

The first source/drain 210 is located on the substrate 100. In the present embodiment, the first source/drain 210 directly contacts the top surface of the substrate 100, but the present invention is not limited thereto. In other embodiments, a buffer layer (not shown) may be additionally included between the first source/drain 210 and the substrate 100. The buffer layer may include, for example, silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride or other suitable materials or a combination of the foregoing materials or a stack of the foregoing materials. In some embodiments, the buffer layer is used, for example, as a hydrogen barrier layer and/or a metal ion barrier layer.

The first source/drain 210 has a groove 212. The groove 212 is recessed from the top surface 212c of the first source/drain 210. In this embodiment, the sidewall 212a and the bottom surface 212d of the groove 212 are both the first source/drain 210. The groove 212 does not penetrate the first source/drain 210.

In some embodiments, the thickness X1 of the first source/drain 210 below the corresponding groove 212 is 0.01 micron to 0.2 micron, and the thickness X2 of the first source/drain 210 around the corresponding groove 212 is 0.21 micron to 1 micron. In some embodiments, the depth DT1 of the groove 212 (i.e., the difference between the thickness X2 and the thickness X1) is 0.2 micron to 0.8 micron.

In this embodiment, the groove 212 is circular in the top view, but the present invention is not limited to this. In other embodiments, the groove 212 is rectangular, elliptical, triangular or other suitable shapes in the top view.

In some embodiments, the material of the first source/drain 210 includes, for example, metals such as chromium, gold, silver, copper, tin, lead, uranium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, nickel, alloys of the above metals, oxides of the above metals, nitrides of the above metals, or combinations thereof or other conductive materials. The first source/drain 210 may have a single-layer structure or a multi-layer structure. For example, in this embodiment, the first source/drain 210 is a single-layer copper metal.

The isolation structure 310 is located on the first source/drain 210. The isolation structure 310 partially fills the groove 212 and covers the sidewall 212a of the groove 212. The isolation structure 310 includes a filling portion 312 and an isolation portion 314. The filling portion 312 is located in the groove 212 and has a first through hole H1. The filling portion 312 covers the sidewall 212a and a portion of the bottom surface 212d of the groove 212. The isolation portion 314 is located on the filling portion 312 and on the top surface 212c of the first source/drain 210 outside the groove 212. In some embodiments, part of the outer sidewall 212b of the first source/drain 210 is covered by the isolation portion 314 of the isolation structure 310, but the present invention is not limited thereto. In other embodiments, the isolation structure 310 does not contact the outer sidewall 212b of the first source/drain 210.

In some embodiments, the upper surface 314c of the isolation portion 314 and the upper surface 312c of the filling portion 312 are located at different levels. The filling portion 312 extends beyond the side wall 314a of the isolation portion 314, so that a portion of the upper surface 312c protrudes from the side wall 314a.

In some embodiments, the material of the isolation structure 310 includes, for example, silicon oxide, silicon oxynitride, silicon nitride, aluminum oxide, einsteinium oxide, zirconium oxide or other suitable materials or a combination of the foregoing materials. In some embodiments, the material of the isolation structure 310 includes an oxide (e.g., silicon oxide) and can be used as an oxygen storage/oxygen replenishing layer, thereby adjusting the oxygen concentration in the semiconductor structure 400 during the manufacturing process. In some embodiments, the isolation structure 310 can have a single-layer structure or a multi-layer structure. When the isolation structure 310 has a multi-layer structure, an oxide layer (e.g., a silicon oxide layer) and a nitride layer (e.g., a silicon nitride layer) can be used in combination to optimize the performance of the semiconductor device 10A. For example, an oxide layer can be used as an oxygen storage/replenishing layer, while a nitride layer can be used as a hydrogen barrier layer or a metal ion barrier layer.

The second source/drain 220 is located on the isolation portion 314 of the isolation structure 310, and extends from the upper surface 314c of the isolation portion 314 along the sidewall 314a of the isolation portion 314 to the upper surface 312c of the filling portion 312. In the present embodiment, the upper surface 312c of the filling portion 312 is lower than the top surface 212c of the first source/drain 210, and the second source/drain 220 extends into the recess 212. For example, the depth DT2 of the second source/drain 220 extending into the recess 212 is 0 micrometers to 0.3 micrometers. In other embodiments, the upper surface 312c of the filling portion 312 is higher than or parallel to the top surface 212c of the first source/drain 210, and the second source/drain 220 does not extend into the groove 212.

The second source/drain 220 has a second through hole H2, and the side wall S2 of the second through hole H2 is aligned with the side wall S1 of the first through hole H1. In this embodiment, the first through hole H1 and the second through hole H2 are circular in the top view, but the present invention is not limited to this. In other embodiments, the first through hole H1 and the second through hole H2 are rectangular, elliptical, triangular or other suitable shapes in the top view.

In some embodiments, the material of the second source/drain 220 includes, for example, metals such as chromium, gold, silver, copper, tin, lead, cobalt, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, nickel, alloys of the above metals, oxides of the above metals, nitrides of the above metals, or combinations thereof or other conductive materials. The second source/drain 220 may have a single-layer structure or a multi-layer structure. For example, in this embodiment, the second source/drain 220 is a single-layer copper metal, but the present invention is not limited thereto. In other embodiments, the second source/drain 220 is a stacked layer of copper and titanium, a stacked layer of aluminum and titanium, a stacked layer of copper and tungsten nickel alloy, a stacked layer of molybdenum and aluminum, or other suitable structures.

The semiconductor structure 400 extends from the top surface of the second source/drain 220 to the second through hole H2, the first through hole H1 and the groove 212 to electrically connect the second source/drain 220 and the first source/drain 210. The semiconductor structure 400 is separated from the sidewall 212a of the groove 212 by the filling portion 312. In some embodiments, the horizontal distance Y between the sidewall 212a of the groove 212 and the semiconductor structure 400 is 0.1 micrometer to 0.5 micrometer.

In some embodiments, the material of the semiconductor structure 400 includes an oxide containing three or more of gallium (Ga), zinc (Zn), indium (In), tin (Sn), aluminum (Al), and tungsten (W) (e.g., metal oxides such as indium gallium zinc tin oxide (IGZTO), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), aluminum zinc tin oxide (AZTO), and indium tungsten zinc oxide (IWZO)), indium gallium oxide (InGO), indium tungsten oxide (InWO), or tungsten-based rare earth doped metal oxides (e.g., Ln-IZO), or other suitable metal oxides or a combination of the above materials. The semiconductor structure 400 has a single-layer structure or a multi-layer structure.

In this embodiment, the semiconductor structure 400 is rectangular in the top view, but the present invention is not limited thereto. In other embodiments, the semiconductor structure 400 is circular, elliptical, triangular or other suitable shapes in the top view.

The gate dielectric layer 320 is located on the semiconductor structure 400. In some embodiments, the material of the gate dielectric layer 320 includes silicon oxide, silicon oxynitride, silicon nitride, aluminum oxide, vanadium oxide, zirconium oxide or other suitable materials or a combination of the foregoing materials.

The gate 500 is located on the gate dielectric layer 320. In some embodiments, the semiconductor structure 400 is located between the sidewall 212a of the groove 212 and the gate 500 in the second direction D2. The second direction D2 is perpendicular to the first direction D1.

In some embodiments, the material of the gate 500 includes, for example, metals such as chromium, gold, silver, copper, tin, lead, uranium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, nickel, alloys of the above metals, oxides of the above metals, nitrides of the above metals, or combinations thereof or other conductive materials. The gate 500 may have a single-layer structure or a multi-layer structure.

In some embodiments, the first source/drain 210 is used as a source, and the second source/drain 220 is used as a drain. The design of the groove 212 of the first source/drain 210 can reduce the problem of the semiconductor structure 400 causing the potential barrier to drop near the drain. For example, as shown in FIG1C, the semiconductor device 10A is substantially equivalent to a dual-gate thin film transistor, in which the source and the bottom gate are connected together. Combining FIG1B and FIG1C, it is explained that the first source/drain 210 can be used as a bottom gate in addition to being used as a source.

2A to 2H are schematic cross-sectional views of a method for manufacturing the semiconductor device 10A of FIG. 1B. Referring to FIG. 2A to 2D, a first source/drain 210 having a groove 212 is formed. First, an electrode material layer 210' is formed on the substrate 100, as shown in FIG. 2A. In this embodiment, a single electrode material layer 210' is formed, but the present invention is not limited thereto. In other embodiments, multiple electrode material layers 210' are formed on the substrate 100, and the aforementioned multiple electrode material layers 210' include, for example, the same or different materials.

Next, a patterned photoresist layer PR1 is formed on the electrode material layer 210'. The patterned photoresist layer PR1 includes a thick portion P1 and a thin portion P2 connected to the thick portion P1. In some embodiments, the method of forming the patterned photoresist layer PR1 includes a half-tone mask process or a grayscale mask process. The thin portion P2 corresponds to the portion where the groove 212 (see Figures 1A and 1B) is to be formed later, and the thick portion P1 corresponds to the portion of the first source/drain 210 outside the groove 212.

Please refer to FIG. 2B , the electrode material layer 210' is etched using the patterned photoresist layer PR1 as a mask to form an intermediate electrode structure 210". In some embodiments, the electrode material layer 210' is etched using a wet etching process or a dry etching process.

Referring to FIG. 2C , a thinning process is performed on the patterned photoresist layer PR1 to remove the thin portion P2 and thin the thick portion P1. For example, the patterned photoresist layer PR1 is thinned by an ashing process or other suitable process. Since the thickness of the thick portion P1 is thicker than the thin portion P2, after the thin portion P2 is completely removed, the thinned thick portion P1' still remains on the intermediate electrode structure 210".

Referring to FIG. 2D , the intermediate electrode structure 210" is etched using the thinned thick portion P1' as a mask to form a first source/drain 210 having a groove 212. The groove 212 is recessed from the top surface 212c of the first source/drain 210. In some embodiments, the intermediate electrode structure 210" is etched using a wet etching process or a dry etching process.

In some embodiments, the thinned thick portion P1' is removed by an ashing process or other suitable process.

Referring to FIG. 2E , an isolation material layer 310’ is formed on the first source/drain 210 and covers the groove 212. A conductive layer 220’ is formed on the isolation material layer 310’. A patterned photoresist layer PR2 is formed on the conductive layer 220’.

Referring to FIG. 2F , the conductive layer 220' is patterned using the patterned photoresist layer PR2 as a mask to form a second source/drain 220 having a second through hole H2. In some embodiments, the conductive layer 220' is etched using a wet etching process or a dry etching process.

Referring to FIG. 2G , the isolation material layer 310' is patterned with the second source/drain 220 as a mask to form an isolation structure 310 including a filling portion 312 and an isolation portion 314. In some embodiments, the isolation material layer 310' is etched using a wet etching process or a dry etching process. In this embodiment, before the isolation material layer 310' is patterned, the patterned photoresist layer PR2 is removed using an ashing process or other suitable process, but the present invention is not limited thereto. In other embodiments, the patterned photoresist layer PR2 is removed after the isolation material layer 310' is patterned.

In this embodiment, the width of the second source/drain 220 is greater than the width of the first source/drain 210, and the isolation structure 310 covers the outer sidewall 212b of the first source/drain 210. However, the present invention is not limited thereto. In other embodiments, the width of the second source/drain 220 is less than or equal to the width of the first source/drain 210, and the isolation structure 310 does not cover the outer sidewall 212b of the first source/drain 210.

Please refer to FIG. 2H to form a semiconductor structure 400. The semiconductor structure 400 extends from the top surface of the second source/drain 220 to the second through hole H2, the first through hole H1 and the groove 212 to electrically connect the second source/drain 220 and the first source/drain 210.

In some embodiments, after forming the semiconductor structure 400, a first annealing process is performed to diffuse oxygen in the semiconductor structure 400 or the environment and store it in the insulating structure 310.

Finally, please return to FIG. 1B to form a gate dielectric layer 320 on the semiconductor structure 400. A gate 500 is formed on the gate dielectric layer 320.

In some embodiments, after forming the gate dielectric layer 320, a second annealing process is performed to diffuse the oxygen stored in the insulating structure 310 into the semiconductor structure 400, thereby reducing the oxygen vacancies in the portion of the semiconductor structure 400 that contacts the insulating structure 310 (i.e., the portion that serves as the semiconductor channel region) and increasing its resistivity, thereby reducing the leakage current problem.

FIG3 is a cross-sectional schematic diagram of a semiconductor device 10B according to an embodiment of the present invention. It must be noted that the embodiment of FIG3 uses the component numbers and partial contents of the embodiments of FIG1A to FIG1C, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, which will not be elaborated here.

The main difference between the semiconductor device 10B of FIG. 3 and the semiconductor device 10A of FIG. 1B is that the second source/drain 220 of the semiconductor device 10B does not extend into the groove 212 of the first source/drain 210.

FIG. 4A to FIG. 4E are simulation diagrams of semiconductor devices according to some embodiments of the present invention. The semiconductor devices 10C to 10G of FIG. 4A to FIG. 4E have similar structures, except that the first source/drain 210 of the semiconductor device 10C does not have a groove 212, while the semiconductor devices 10D to 10G have different depths DT1 of the groove 212. The depths DT1 of the groove 212 of the first source/drain 210 of the semiconductor devices 10D to 10G are 0.2 microns, 0.4 microns, 0.6 microns, and 0.8 microns, respectively. The depths DT2 of the second source/drain 220 of the semiconductor devices 10E to 10G extending into the groove 212 are 0.1 microns, 0.2 microns, and 0.3 microns, respectively.

In the semiconductor devices 10C-10G, the substrate 100 is glass, the first source/drain 210, the second source/drain 220 and the gate 500 are copper, the isolation structure 310 and the gate dielectric layer 320 are silicon oxide, and the semiconductor structure 400 is indium gallium zinc oxide (IGZO).

The relationship among the depth DT1 of the recess 212 , the depth DT2 of the second source/drain 220 extending into the recess 212 , and the Drain Induced Potential Barrier (DIBL) lowering is analyzed, and the results are shown in Table 1. Taking the first source/drain 210 as the source and the second source/drain 220 as the drain, and taking the DIBL of the semiconductor device 10C without the groove 212 (i.e., the depth DT1 is 0) as the basis, the reduction of the critical voltage (Vth) when the source-drain voltage difference (Vds) is 0.1V and the critical voltage (Vth) when the source-drain voltage difference (Vds) is 1V (i.e., the DIBL) is simulated and calculated using computer-aided design (TCAD) technology.

Table 1

In Table 1, a negative value of the depth DT2 indicates that the second source/drain 220 does not extend into the groove 212, and the aforementioned negative value is equal to the vertical distance between the end point of the second source/drain 220 and the top surface of the groove 212. It can be seen from Table 1 that the DIBL of the semiconductor device can be significantly reduced by setting the groove 212.

5A and 5B are Id-Vg characteristic curves of semiconductor devices according to some embodiments of the present invention. The depth DT1 of the semiconductor device corresponding to FIG5A is 0.6 micrometers, the thickness HD1 (thickness in the horizontal direction) of the isolation structure 310 between the sidewall S1 of the first through hole H1 and the semiconductor structure 400 is 0.1 micrometers, and the thickness HD2 of the gate dielectric layer 320 in the horizontal direction is also 0.1 micrometers (similar to the structure of the semiconductor device 10F in FIG4D, but the thickness HD1 and the thickness HD2 are both adjusted to 0.1 micrometers). The depth DT1 of the semiconductor device corresponding to FIG5B is 0, and the thickness HD2 of the gate dielectric layer 320 in the isolation structure 310 in the horizontal direction is 0.1 micron (similar to the structure of the semiconductor device 10C in FIG4A, but the thickness HD2 is adjusted to 0.1 micron). The first source/drain 210 is used as the source, and the second source/drain 220 is used as the drain, Vd is the voltage difference between the second source/drain 220 and the first source/drain 210, Vg is the voltage of the gate 500, and Id is the current output by the second source/drain 220. By comparing FIG5A with FIG5B, it can be seen that the negative effects caused by DIBL can be improved by setting the groove 212.

FIG. 6A and FIG. 6B are Id-Vd characteristic curves of semiconductor devices according to some embodiments of the present invention. FIG. 6A corresponds to the same semiconductor device as FIG. 5A, and FIG. 6B corresponds to the same semiconductor device as FIG. 5B. In the semiconductor device corresponding to FIG. 6A, under the condition of fixed Vg, the influence of Vd on Id is small, which is also due to the fact that the first source/drain groove improves the problem of DIBL.

FIG. 7 is a cross-sectional schematic diagram of a semiconductor device 10H according to an embodiment of the present invention. It must be noted that the embodiment of FIG. 7 uses the component numbers and partial contents of the embodiments of FIG. 1A to FIG. 1C, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.

The main difference between the semiconductor device 10H of FIG. 7 and the semiconductor device 10A of FIG. 1B is that the first source/drain 210 of the semiconductor device 10H has a multi-layer structure.

Referring to FIG. 7 , the buffer layer 110 is located on the substrate 100 . The first source/drain 210 is located on the buffer layer 110 . The first source/drain 210 of the semiconductor device 10H includes a first electrode layer 211A, 211B, 211C and a second electrode layer 213 . The first electrode layers 211A, 211B, 211C are stacked together to form a first electrode structure 211 .

The first electrode layer 211B is sandwiched between the first electrode layer 211A and the first electrode layer 211C. In some embodiments, the material of the first electrode layer 211B is different from the material of the first electrode layer 211A and the first electrode layer 211C. For example, the material of the first electrode layer 211B includes copper, and the material of the first electrode layer 211A and the first electrode layer 211C includes a tungsten-nickel alloy. In some embodiments, the thickness of the first electrode layer 211B is 100 nanometers to 600 nanometers, and the thickness of the first electrode layer 211A and the first electrode layer 211C is 10 nanometers to 30 nanometers.

The first electrode structure 211 has an opening 211H. The opening 211H corresponds to the groove 212 of the first source/drain 210. In this embodiment, the groove 212 has the same width as the opening 211H, and the sidewall 212a of the groove 212 is aligned with the sidewall of the opening 211H. In other embodiments, the width of the groove 212 is smaller than the width of the opening 211H, such as the semiconductor device 101 of FIG. 9.

The second electrode layer 213 is located on the top surface of the first electrode structure 211 and fills the opening 211H of the first electrode structure 211. In this embodiment, the portion of the second electrode layer 213 filling the opening 211H is separated from the portion located on the top surface of the first electrode structure 211, but the present invention is not limited thereto. In other embodiments, the second electrode layer 213 extends continuously from the top surface of the first electrode structure 211 to the opening 211H, as shown in the semiconductor device 10I of FIG. 9. In some embodiments, the material of the second electrode layer 213 includes copper or other metal materials. In some embodiments, the thickness of the second electrode layer 213 is 10 nanometers to 200 nanometers.

8A to 8D are cross-sectional schematic diagrams of a method for manufacturing the first source/drain 210 of the semiconductor device 10H of FIG. 7. Referring to FIG. 8A, first electrode material layers 211A', 211B', and 211C' are sequentially formed on the substrate 100. In this embodiment, the first electrode material layers 211A', 211B', and 211C' are formed on the buffer layer 110. A patterned photoresist layer PR3 is formed on the first electrode material layers 211A', 211B', and 211C'.

Referring to FIG. 8B , the first electrode material layer 211A’, 211B’, 211C’ is etched with the patterned photoresist layer PR3 as a mask to form a first electrode structure 211. The first electrode structure 211 has an opening 211H. In some embodiments, the first electrode material layer 211A’, 211C’ includes a tungsten-nickel alloy, and the first electrode material layer 211B’ includes copper. Tungsten-nickel alloy and copper have different etching rates. In some embodiments, the provision of the first electrode material layer 211C’ helps to form an opening 211H with a relatively vertical sidewall after the etching process.

In some embodiments, the patterned photoresist layer PR3 is removed using an ashing process or other suitable process.

Referring to FIG. 8C , one or more second electrode material layers 213' are formed on the first electrode structure 211 and filled into the opening 211H. In this embodiment, the method for depositing the second electrode material layer 213' includes a physical vapor deposition process or other suitable processes. The deposition process can be isotropic (i.e., the film thickness grows laterally) or anisotropic (i.e., the film thickness does not grow laterally).

A patterned photoresist layer PR4 is formed on the second electrode material layer 213'. The patterned photoresist layer PR4 covers the first electrode structure 211 and the opening 211H.

Please refer to FIG. 8D , the second electrode material layer 213' is etched using the patterned photoresist layer PR4 as a mask to form the first source/drain 210. In some embodiments, the patterned photoresist layer PR4 is removed by an ashing process or other suitable process.

Finally, a process similar to that of FIGS. 2E to 2H is performed on the first source/drain 210 formed in FIG. 8D to obtain the semiconductor device 10H.

FIG10 is a cross-sectional schematic diagram of a semiconductor device 10J according to an embodiment of the present invention. It must be noted that the embodiment of FIG10 uses the component numbers and partial contents of the embodiments of FIG1A to FIG1C, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, which will not be elaborated here.

The main difference between the semiconductor device 10J of FIG. 10 and the semiconductor device 10A of FIG. 1B is that the first source/drain 210 of the semiconductor device 10J has a multi-layer structure.

Referring to FIG. 10 , the first source/drain 210 of the semiconductor device 10J includes a first electrode layer 211D and a second electrode layer 211E.

The second electrode layer 211E is located on the top surface of the first electrode layer 211D. The bottom surface 212d of the groove 212 is the first electrode layer 211D, and the sidewall 212a of the groove 212 is the second electrode layer 211E. In some embodiments, the material of the first electrode layer 211D is different from the material of the second electrode layer 211E. For example, the material of the first electrode layer 211D includes titanium, and the material of the second electrode layer 211E includes copper.

In some embodiments, the thickness of the first electrode layer 211D is 10 nm to 50 nm, and the thickness of the second electrode layer 211E is 100 nm to 600 nm.

11A to 11D are cross-sectional schematic diagrams of a method for manufacturing the first source/drain 210 of the semiconductor device 10J of FIG. 10. Referring to FIG. 11A, electrode material layers 211D' and 211E' are sequentially formed on the substrate 100. In this embodiment, the electrode material layers 211D' and 211E' include different materials. For example, the electrode material layer 211D' includes titanium, and the electrode material layer 211E' includes copper.

Next, a patterned photoresist layer PR1 is formed on the electrode material layer 211D', 211E'. The patterned photoresist layer PR1 includes a thick portion P1 and a thin portion P2 connected to the thick portion P1. In some embodiments, the method of forming the patterned photoresist layer PR1 includes a half-tone mask process or a grayscale mask process. The thin portion P2 corresponds to the portion where the groove 212 (see FIG. 10 ) is to be formed later, and the thick portion P1 corresponds to the portion of the first source/drain 210 outside the groove 212.

Please refer to Figure 11B, the electrode material layer 210' is etched using the patterned photoresist layer PR1 as a mask to form an intermediate electrode structure 210". In some embodiments, a wet etching process and/or a dry etching process is used to etch the electrode material layers 211D', 211E'. In some embodiments, a wet etching process is used to etch the electrode material layer 211E' to obtain the intermediate electrode layer 211E". Then, a dry etching process is used to etch the electrode material layer 211D' to obtain the first electrode layer 211D. In this embodiment, the intermediate electrode structure 210" includes a first electrode layer 211D and an intermediate electrode layer 211E". In some embodiments, when the electrode material layer 211D' includes a molybdenum-titanium alloy, the electrode material layer 211D' can be etched using a wet etching process or a dry etching process; when the electrode material layer 211D' includes titanium metal, the electrode material layer 211D' can be etched using a dry etching process.

Referring to FIG. 11C , a thinning process is performed on the patterned photoresist layer PR1 to remove the thin portion P2 and thin the thick portion P1. For example, the patterned photoresist layer PR1 is thinned by an ashing process or other suitable process. Since the thickness of the thick portion P1 is thicker than the thin portion P2, after the thin portion P2 is completely removed, the thinned thick portion P1' still remains on the intermediate electrode structure 210".

Please refer to FIG. 11D , the intermediate electrode structure 210″ is etched with the thinned thick portion P1′ as a mask to form a first source/drain 210 having a groove 212. The groove 212 is recessed from the top surface 212c of the first source/drain 210. In some embodiments, a wet etching process is used to etch the intermediate electrode layer 211E″. Since the first electrode layer 211D and the intermediate electrode layer 211E″ have different etching selectivities, the aforementioned etching process can easily stop on the first electrode layer 211D. In some embodiments, the thinned thick portion P1′ is removed by an ashing process or other suitable process.

Finally, a process similar to that of FIGS. 2E to 2H is performed on the first source/drain 210 formed in FIG. 11D to obtain the semiconductor device 10J.

FIG12 is a cross-sectional schematic diagram of a semiconductor device 10K according to an embodiment of the present invention. It must be noted that the embodiment of FIG12 uses the component numbers and some contents of the embodiment of FIG10, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, which will not be elaborated here.

The main difference between the semiconductor device 10K of FIG. 12 and the semiconductor device 10J of FIG. 10 is that the first electrode layer 211D of the first source/drain 210 of the semiconductor device 10K extends beyond the sidewall of the second electrode layer 211E.

In FIG. 11B , if the intermediate electrode layer 211E″ and the first electrode layer 211D are both formed by a wet etching process, the outer sidewalls of the intermediate electrode layer 211E″ and the outer sidewalls of the first electrode layer 211D can be retracted together in the patterned photoresist layer PR1 during the wet etching process, so that the outer sidewalls of the first electrode layer 211D can be aligned with the outer sidewalls of the intermediate electrode layer 211E″. However, in the embodiment of FIG. 12 , since the intermediate electrode layer 211E″ is formed by a wet etching process, the outer sidewalls of the first electrode layer 211D can be aligned with the outer sidewalls of the intermediate electrode layer 211E″. The intermediate electrode layer 211E" is formed by dry etching process to form the first electrode layer 211D. Therefore, when dry etching is performed to form the first electrode layer 211D, the outer sidewall of the intermediate electrode layer 211E" located thereon has been retracted into the patterned photoresist layer PR1, resulting in the outer sidewall of the first electrode layer 211D formed by dry etching with the patterned photoresist layer PR1 as a mask exceeding the outer sidewall of the second electrode layer 211E retracted into the patterned photoresist layer PR1.

FIG13 is a cross-sectional schematic diagram of a semiconductor device 10L according to an embodiment of the present invention. It must be noted that the embodiment of FIG13 uses the component numbers and some contents of the embodiment of FIG10, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, which will not be elaborated here.

The main difference between the semiconductor device 10L of FIG. 13 and the semiconductor device 10J of FIG. 10 is that the first source/drain 210 of the semiconductor device 10L further includes a third electrode layer 211F.

The first source/drain 210 of the semiconductor device 10L can be formed by a process similar to FIG. 11A to FIG. 11D. Specifically, in the step of FIG. 11A, another electrode material layer is additionally formed on the electrode material layer 211E', and the aforementioned another electrode material layer is etched through the steps of FIG. 11B to FIG. 11D to form a third electrode layer 211F.

In some embodiments, the materials of the first electrode layer 211D, the second electrode layer 211E, and the third electrode layer 211F include titanium, copper, and tungsten-nickel alloy, respectively. The third electrode layer 211F is provided to help form a relatively vertical sidewall 212a after the etching process.

In summary, the stacking arrangement of the first source/drain, the isolation structure and the second source/drain can reduce the footprint of the semiconductor device. In addition, the problem of the potential barrier drop caused by the drain can be improved by the groove of the first source/drain.

10A: Semiconductor devices

100: Substrate

210: First source/drain

212: Groove

212a,314a,S1,S2: Side wall

212b: Outer side wall

212c: Top

212d: Bottom surface

220: Second source/drain

310: Isolation structure

312: Filling section

312c,314c: Upper surface

314: Isolation Department

320: Gate dielectric layer

400:Semiconductor structure

500: Gate

D1: First direction

D2: Second direction

DT1, DT2: Depth

H1: First through hole

H2: Second through hole

X1, X2: thickness

Y: horizontal distance

Claims (10)

A semiconductor device, comprising: A first source/drain, located on a substrate and having a groove, wherein the groove is recessed from the top surface of the first source/drain; An isolation structure, located on the first source/drain and partially filled in the groove and covering the sidewall of the groove, wherein the isolation structure comprises a filling portion and an isolation portion, wherein the filling portion is in the groove and has a first through hole, and the isolation portion is on the filling portion and on the top surface of the first source/drain outside the groove; A second source/drain, located on the isolation portion; A semiconductor structure extending from the second source/drain into the first through hole and the groove to electrically connect the second source/drain and the first source/drain; A gate dielectric layer located on the semiconductor structure; and A gate located on the gate dielectric layer. A semiconductor device as described in claim 1, wherein the upper surface of the isolation portion and the upper surface of the filling portion are located at different horizontal heights, and the second source/drain extends from the upper surface of the isolation portion along the side wall of the isolation portion to the upper surface of the filling portion. A semiconductor device as described in claim 1, wherein the second source/drain has a second through hole, and the sidewalls of the second through hole are aligned with the sidewalls of the first through hole. A semiconductor device as described in claim 1, wherein the thickness of the first source/drain below the groove is 0.01 micron to 0.2 micron, and the thickness of the first source/drain around the groove is 0.21 micron to 1 micron. A semiconductor device as described in claim 1, wherein the first source/drain, the isolation structure, the second source/drain and the semiconductor structure are stacked sequentially in a first direction, and the semiconductor structure is located between the side wall of the groove and the gate in a second direction perpendicular to the first direction. A semiconductor device as described in claim 1, wherein the first source/drain comprises: Three first electrode layers stacked together to form a first electrode structure, wherein the material of one of the three first electrode layers sandwiched in the middle is different from the materials of the other two; and A second electrode layer located on the top surface of the first electrode structure and filled in an opening of the first electrode structure. A semiconductor device as described in claim 1, wherein the first source/drain comprises: a first electrode layer; and a second electrode layer located on the top surface of the first electrode layer, wherein the bottom surface of the groove is the first electrode layer, and the sidewall of the groove is the second electrode layer, wherein the material of the first electrode layer is different from the material of the second electrode layer. A method for manufacturing a thin film transistor, comprising: forming a first source/drain having a groove, wherein the groove is recessed from the top surface of the first source/drain; forming an isolation material layer on the first source/drain and covering the groove; forming a conductive layer on the isolation material layer; patterning the conductive layer to form a second source/drain; Patterning the isolation material layer to form an isolation structure, wherein the isolation structure partially fills the groove and covers the sidewalls of the groove, wherein the isolation structure includes a filling portion and an isolation portion, wherein the filling portion is in the groove and has a first through hole, and the isolation portion is on the filling portion and on the top surface of the first source/drain outside the groove; Forming a semiconductor structure extending from the second source/drain to the first through hole and the groove to electrically connect the second source/drain and the first source/drain; Forming a gate dielectric layer on the semiconductor structure; and Forming a gate on the gate dielectric layer. The manufacturing method as described in claim 8, wherein the method for forming the first source/drain having the groove comprises: Forming at least one electrode material layer on a substrate; Forming a patterned photoresist layer on the at least one electrode material layer, wherein the patterned photoresist layer comprises a thick portion and a thin portion connected to the thick portion; Etching the at least one electrode material layer using the patterned photoresist layer as a mask to form an intermediate electrode structure; Performing a thinning process on the patterned photoresist layer to remove the thin portion and thin the thick portion; Etching the intermediate electrode structure using the thinned thick portion as a mask to form the first source/drain. A manufacturing method as described in claim 8, wherein the method for forming the first source/drain having the groove comprises: forming at least one first electrode material layer on a substrate; forming a first patterned photoresist layer on the at least one first electrode material layer; etching the at least one first electrode material layer using the first patterned photoresist layer as a mask to form a first electrode structure, wherein the first electrode structure has an opening; forming at least one second electrode material layer on the first electrode structure and filling the opening; forming a second patterned photoresist layer on the at least one second electrode material layer; and etching the at least one second electrode material layer using the second patterned photoresist layer as a mask to form the first source/drain.