TWI875464B - Thin film transistor and manufacturing method thereof - Google Patents

Abstract

A thin film transistor includes a first source/drain, an isolation structure, a second source/drain, a semiconductor structure, a gate dielectric layer, a protrusion structure and a gate. The first source/drain is located on the substrate. The isolation structure is located on the first source/drain and has a first through hole overlapping the first source/drain. The second source/drain is disposed on the isolation structure. The semiconductor structure extends from the second source/drain to the first source/drain along the sidewall of the first through hole. The gate dielectric layer is located on the semiconductor structure. The protruding structure is located on the second source/drain and has a second through hole overlapping the first through hole. The gate is located on the gate dielectric layer and extends from above the protrusion structure into the second through hole and into the first through hole. The first source/drain, isolation structure, second source/drain, protrusion structure and gate are stacked in sequence in the first direction.

Description

Thin film transistor and method for manufacturing the same

The present invention relates to a thin film transistor and a method for manufacturing the same.

Currently, thin film transistors are widely used in various electronic products, such as mobile phones, televisions, tablet computers, smart windows, etc. Generally speaking, a thin film transistor includes a gate, a semiconductor channel layer, a source, and a drain, wherein the current flows from the source through the semiconductor channel layer to the drain, and the gate is used to provide an electric field to the semiconductor channel layer to determine whether the semiconductor channel layer is turned on or not. With the advancement of technology, the size of thin film transistors has been reduced year by year. In order to reduce the size of thin film transistors, many manufacturers are committed to developing new semiconductor materials and new thin film transistor structures.

The present invention provides a thin film transistor and a manufacturing method thereof, which can reduce the problems caused by parasitic capacitance.

At least one embodiment of the present invention provides a thin film transistor, which includes a first source/drain, an isolation structure, a second source/drain, a semiconductor structure, a gate dielectric layer, a protrusion structure and a gate. The first source/drain is located on a substrate. The isolation structure is located on the first source/drain and has a first through hole overlapping the first source/drain. The second source/drain is arranged on the isolation structure. The semiconductor structure extends from the second source/drain along the side wall of the first through hole to the first source/drain. The gate dielectric layer is located on the semiconductor structure. The protrusion structure is located on the second source/drain and has a second through hole overlapping the first through hole. The gate is located on the gate dielectric layer and extends from above the protrusion structure into the second through hole and the first through hole. The first source/drain, the isolation structure, the second source/drain, the protrusion structure and the gate are stacked in sequence in the first direction.

At least one embodiment of the present invention provides a method for manufacturing a thin film transistor, comprising the following steps. A first source/drain is formed on a substrate. An isolation structure is formed on the first source/drain, wherein the isolation structure has a first through hole overlapping the first source/drain. A second source/drain is formed on the first source/drain. A semiconductor structure is formed on the second source/drain, and the semiconductor structure extends from the second source/drain along the side wall of the first through hole to the first source/drain. A gate dielectric layer is formed on the semiconductor structure. A protrusion structure is formed on the first source/drain, and the protrusion structure has a second through hole. A gate is formed on the gate dielectric layer, wherein the first through hole overlaps the second through hole, and the gate extends from above the protrusion structure into the second through hole and the first through hole, wherein the first source/drain, the isolation structure, the second source/drain, the protrusion structure and the gate are stacked in sequence in the first direction.

10,20,30,40: Thin film transistors

100: Substrate

110,110A: Isolation structure

110A’: Isolation material layer

112: First through hole

120,120A,120B,120C: protrusion structure

120’, 120A’, 120B’: Photoresist material layer

121: First level

123: Second level

122: Second through hole

130: Gate dielectric layer

210: First source/drain

220: Second source/drain

220’: Conductive material layer

222: Open mouth

230: Gate

232: First electrode

234: Second electrode

300:Semiconductor structure

D1: First direction

L: Light

MK: Mask

T1, T2, T3: thickness

Figures 1A, 2A, 3A, 4A, 5A, 6A, 7A and 8A are top views of a method for manufacturing a thin film transistor according to an embodiment of the present invention.

Figures 1B, 2B, 3B, 4B, 5B, 6B, 7B and 8B are schematic cross-sectional views along lines A-A’ in Figures 1A, 2A, 3A, 4A, 5A, 6A, 7A and 8A, respectively.

FIG9 is a schematic cross-sectional view of a thin film transistor according to an embodiment of the present invention.

Figures 10A to 10D are cross-sectional schematic diagrams of the manufacturing method of the thin film transistor of Figure 9.

Figure 11 is a schematic cross-sectional view of a thin film transistor according to an embodiment of the present invention.

Figures 12A to 12E are cross-sectional schematic diagrams of the manufacturing method of the thin film transistor of Figure 11.

FIG13 is a schematic cross-sectional view of a thin film transistor according to an embodiment of the present invention.

FIG. 14 is a graph showing the transmittance of the semiconductor structure and the first source/drain for light of different wavelengths according to some embodiments of the present invention.

1A, 2A, 3A, 4A, 5A, 6A, 7A and 8A are top views of a method for manufacturing a thin film transistor 10 according to an embodiment of the present invention. 1B, 2B, 3B, 4B, 5B, 6B, 7B and 8B are cross-sectional views along lines A-A' in 1A, 2A, 3A, 4A, 5A, 6A, 7A and 8A, respectively. Referring to FIG. 1A and FIG. 1B , a substrate 100 is provided. In some embodiments, the substrate 100 is, for example, a rigid substrate, and its material may be glass, quartz, an organic polymer or an opaque/reflective material (e.g., a conductive material, metal, a wafer, ceramic or other applicable material) or other applicable materials. However, the present invention is not limited thereto, and in other embodiments, the substrate 100 may also be a flexible substrate or a stretchable substrate. For example, the materials of the flexible substrate and the stretchable substrate include polyimide (PI), polydimethylsiloxane (PDMS), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyester (PES), polymethylmethacrylate (PMMA), polycarbonate (PC), polyurethane (PU) or other suitable materials.

A first source/drain 210 is formed on the substrate 100. In some embodiments, a blanket conductive material layer is first formed on the substrate 100. Then, a patterned photoresist layer is formed on the conductive material layer. Then, the conductive material layer is etched using the patterned photoresist layer as a mask to form the first source/drain 210. Finally, the patterned photoresist layer is removed.

In some embodiments, the material of the first source/drain 210 includes metal (e.g., chromium, gold, silver, copper, tin, lead, uranium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, nickel, indium, tin, alloys of the above metals, stacked layers of the above metals, or other suitable metal materials), conductive oxide (e.g., indium tin oxide (ITO), zinc oxide (ZnO), or other suitable conductive oxides), conductive nitride, or other suitable conductive materials. In this embodiment, the first source/drain 210 is a transparent conductive layer, and its transmittance for light with a wavelength of 350nm to 1000nm is 70% to 95%, but the present invention is not limited thereto. In other embodiments, the first source/drain 210 is an opaque conductive layer (or light shielding layer).

In this embodiment, the first source/drain 210 directly contacts the top surface of the substrate 100, but the present invention is not limited thereto. In other embodiments, a buffer layer (not shown) may be additionally included between the first source/drain 210 and the substrate 100. The buffer layer may include, for example, silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride or other suitable materials or a combination of the foregoing materials or a stack of the foregoing materials. In some embodiments, the buffer layer is used, for example, as a hydrogen barrier layer and/or a metal ion barrier layer.

Referring to FIG. 2A and FIG. 2B , an isolation structure 110 is formed on the first source/drain 210. The isolation structure has a first through hole 112 overlapping the first source/drain 210. In some embodiments, a blanket isolation material layer is first formed on the substrate 100 and the first source/drain 210. Then, a patterned photoresist layer is formed on the isolation material layer. Then, the isolation material layer is etched using the patterned photoresist layer as a mask to form an isolation structure 110 having the first through hole 112. Finally, the patterned photoresist layer is removed.

In some embodiments, the material of the isolation structure 110 includes, for example, an organic insulating material, silicon oxide, silicon oxynitride, silicon nitride, aluminum oxide, uranium oxide, zirconium oxide or other suitable materials or a combination of the foregoing materials. In some embodiments, the material of the isolation structure 110 includes an oxide (e.g., silicon oxide) and can be used as an oxygen storage/oxygen replenishing layer, thereby adjusting the oxygen concentration of the semiconductor structure subsequently formed during the manufacturing process. In some embodiments, the isolation structure 110 can have a single-layer structure or a multi-layer structure. When the isolation structure 110 has a multi-layer structure, an oxide layer (e.g., a silicon oxide layer) and a nitride layer (e.g., a silicon nitride layer) can be used in combination to optimize the performance of the thin film transistor. For example, an oxide layer can be used as an oxygen storage/replenishing layer, while a nitride layer can be used as a hydrogen barrier layer or a metal ion barrier layer.

In some embodiments, the thickness T1 of the isolation structure 110 is less than or equal to 0.5 microns.

Referring to FIG. 3A and FIG. 3B , a second source/drain 220 is formed on the first source/drain 210. The second source/drain 220 has an opening 222 overlapping the first through hole 112. In the present embodiment, the second source/drain 220 is formed on the isolation structure 110. In some embodiments, a blanket conductive material layer is first formed on the isolation structure 110. Then, a patterned photoresist layer is formed on the conductive material layer. Then, the conductive material layer is etched using the patterned photoresist layer as a mask to form a second source/drain 220 having an opening 222. Finally, the patterned photoresist layer is removed.

In some embodiments, the material of the second source/drain 220 includes metal (e.g., chromium, gold, silver, copper, tin, lead, uranium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, nickel, indium, tin, alloys of the above metals, stacked layers of the above metals, or other suitable metal materials), conductive oxide (e.g., indium tin oxide, zinc oxide, or other suitable conductive oxides), conductive nitride, or other suitable conductive materials. In this embodiment, the second source/drain 220 is an opaque conductive layer (or light shielding layer), and its transmittance for light with a wavelength of 350nm to 1000nm is less than 0.5%, but the present invention is not limited thereto. In other embodiments, the second source/drain 220 is a transparent conductive layer.

In the present embodiment, the patterning process of the second source/drain 220 and the patterning process of the isolation structure 110 are performed using different masks. Therefore, the shape of the vertical projection of the second source/drain 220 on the substrate 100 is different from the shape of the vertical projection of the isolation structure 110 on the substrate 100. In other embodiments, the patterning process of the second source/drain 220 and the patterning process of the isolation structure 110 can be performed using the same mask. For example, a blanket isolation material layer and a blanket conductive material layer are continuously deposited on the substrate 100 and the first source/drain 210. Then, a patterned photoresist layer is formed on the blanket conductive material layer using a mask. Then, the conductive material layer and the isolation material layer located thereunder are etched once or multiple times using the patterned photoresist layer to form the second source/drain 220 and the isolation structure 110. In this case, the shape of the vertical projection of the second source/drain 220 on the substrate 100 is substantially equal to the shape of the vertical projection of the isolation structure 110 on the substrate 100.

Please refer to FIG. 4A and FIG. 4B to form a photoresist material layer 120' on the second source/drain 220. In this embodiment, the photoresist material layer 120' is filled into the first through hole 112 and the opening 222.

Light L is irradiated from the side of the substrate 100 facing away from the first source/drain 210. In this embodiment, the first source/drain 210 is a transparent conductive layer, and part of the light L passes through the substrate 100, the first source/drain 210 and the isolation structure 110, and irradiates the photoresist layer 120'. Since the second source/drain 220 is an opaque conductive layer (or a light shielding layer), the second source/drain 220 will shield part of the light L, and the light L irradiates the part of the photoresist layer 120' that is not shielded by the second source/drain 220.

Referring to FIG. 5A and FIG. 5B , the portion of the photoresist layer 120' not shielded by the second source/drain 220 (i.e., the portion irradiated by light) is removed to form a protruding structure 120. For example, the portion of the photoresist layer 120' irradiated by light is removed by a developing process. In this embodiment, the protruding structure 120 is formed on the first source/drain 210 by an exposure process and a developing process, and the protruding structure 120 has a second through hole 122 exposing the first source/drain 210. The second through hole 122 overlaps the first through hole 112 and the opening 222.

In some embodiments, the thickness T2 of the protrusion structure 120 is 1 micron to 1.5 microns. In some embodiments, the thickness T2 of the protrusion structure 120 is greater than the thickness T1 of the isolation structure 110.

In this embodiment, the second source/drain 220 is used as a mask to perform an exposure process and a development process to form the protrusion structure 120, thereby saving the cost of the mask. In addition, using the second source/drain 220 as a mask can improve the alignment accuracy between the second source/drain 220 and the protrusion structure 120, so that the second source/drain 220 is substantially aligned with the protrusion structure 120.

6A and 6B, a semiconductor structure 300 is formed on the second source/drain 220, and the semiconductor structure 300 extends from the second source/drain 220 along the sidewall of the first through hole 112 to the first source/drain 210. In this embodiment, the semiconductor structure 300 extends from the top surface of the protrusion structure 120 into the second through hole 122, and extends along the sidewall of the second through hole 122 to the second source/drain 220. Then, the semiconductor structure 300 extends from the second source/drain 220 into the first through hole 112, and extends along the sidewall of the first through hole 112 to the first source/drain 210. In this embodiment, the semiconductor structure 300 contacts the top surface of the protrusion structure 120, the sidewall of the second through hole 122, the sidewall of the opening 222, and the sidewall of the first through hole 112.

In some embodiments, the material of the semiconductor structure 300 includes an oxide containing two or more of gallium (Ga), zinc (Zn), indium (In), tin (Sn), aluminum (Al), and tungsten (W) (e.g., metal oxides such as indium gallium zinc tin oxide (IGZTO), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), aluminum zinc tin oxide (AZTO), and indium tungsten zinc oxide (IWZO)), indium gallium oxide (IGO), indium tungsten oxide (IWO), indium zinc oxide (IZO), or lanthanum-doped rare earth metal oxides (e.g., Ln-IZO), or other suitable metal oxides or combinations of the above materials. In some embodiments, the semiconductor structure 300 has a single-layer or multi-layer structure. In some embodiments, the semiconductor structure 300 includes a transparent semiconductor layer or an opaque semiconductor layer. In some embodiments, the semiconductor structure 300 includes an amorphous metal oxide.

In some embodiments, both the first source/drain 210 and the semiconductor structure 300 include metal oxide. However, the resistivity of the first source/drain 210 is lower than the resistivity of the semiconductor structure 300, which can be achieved by adjusting the composition of the metal element in the metal oxide, or by performing an additional doping process (such as a hydrogen doping process) on the first source/drain 210. In some embodiments, both the first source/drain 210 and the semiconductor structure 300 include metal oxide, wherein the resistivity of the first source/drain 210 is 1.59μ ohm cm to 120μ ohm cm, and the resistivity of the semiconductor structure 300 is ^10-3 ohm cm to ¹⁰³ ohm cm.

Referring to FIG. 7A and FIG. 7B , a gate dielectric layer 130 is formed on the semiconductor structure 300. In some embodiments, the gate dielectric layer 130 extends from the semiconductor structure 300 to the protrusion structure 120 and the isolation structure 110.

In some embodiments, the gate dielectric layer 130 includes, for example, silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, einsteinium oxide, or other suitable materials. In some embodiments, the thickness T3 of the gate dielectric layer 130 is 5nm to 1000nm.

In some examples, after forming the gate dielectric layer 130, the gate dielectric layer 130, the protrusion structure 120, and the isolation structure 110 are etched to expose the first source/drain 210 and the second source/drain 220. For example, a patterned photoresist layer is formed on the gate dielectric layer 130. Then, the gate dielectric layer 130, the protrusion structure 120, and the isolation structure 110 located thereunder are etched using the patterned photoresist layer to form a first opening TH1 exposing the first source/drain 210 and a second opening TH2 exposing the second source/drain 220. In some embodiments, the first opening TH1 passes through the gate dielectric layer 130 and the isolation structure 110, and the second opening TH2 passes through the gate dielectric layer 130 and the protrusion structure 120.

Finally, referring to FIG. 8A and FIG. 8B , a gate 230 is formed on the gate dielectric layer 130. At this point, the thin film transistor 10 is substantially completed. In this embodiment, while forming the gate 230, a first electrode 232 and a second electrode 234 are formed on the gate dielectric layer 130. In some embodiments, a blanket conductive material layer is first formed on the gate dielectric layer 130. Then, a patterned photoresist layer is formed on the conductive material layer. Then, the conductive material layer is etched using the patterned photoresist layer as a mask to form a gate 230, a first electrode 232, and a second electrode 234 separated from each other. Finally, the patterned photoresist layer is removed.

The gate 230 extends from above the protrusion structure 120 into the second through hole 122 and the first through hole 112. The first source/drain 210, the isolation structure 110, the second source/drain 220, the protrusion structure 120 and the gate 230 are stacked in sequence in the first direction D1. The first direction D1 is, for example, perpendicular to the top surface of the substrate 100.

The first electrode 232 is filled into the first opening TH1 and connected to the first source/drain 210. The second electrode 234 is filled into the second opening TH2 and connected to the second source/drain 220.

In some embodiments, the materials of the gate 230, the first electrode 232, and the second electrode 234 include metals (e.g., chromium, gold, silver, copper, tin, lead, uranium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, nickel, indium, tin, alloys of the above metals, stacked layers of the above metals, or other suitable metal materials), conductive oxides (e.g., indium tin oxide, zinc oxide, indium gallium zinc oxide, or other suitable conductive oxides), conductive nitrides, or other suitable conductive materials.

In this embodiment, the protrusion structure 120 is used to increase the distance between the gate 230 and the second source/drain 220 in the first direction D1, thereby reducing the parasitic capacitance between the gate 230 and the second source/drain 220, thereby improving the reliability of the thin film transistor 10.

FIG9 is a cross-sectional schematic diagram of a thin film transistor 20 according to an embodiment of the present invention. It must be noted that the embodiment of FIG9 uses the component numbers and partial contents of the embodiments of FIG1A to FIG8B, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, which will not be elaborated here.

The main difference between the thin film transistor 20 of FIG. 9 and the thin film transistor 10 of FIG. 8B is that in the thin film transistor 10 of FIG. 8B, the shape of the second source/drain 220 and the shape of the isolation structure 110 are defined using different masks. However, in the thin film transistor 20 of FIG. 9, the shape of the second source/drain 220 and the shape of the isolation structure 110A are defined using the same mask. In addition, in the thin film transistor 10 of FIG. 8B, the shape of the protrusion structure 120 is defined using the second source/drain 220 as a mask. However, in the thin film transistor 20 of FIG. 9, the shape of the second source/drain 220 is defined using the protrusion structure 120A as a mask.

Figures 10A to 10D are cross-sectional schematic diagrams of the manufacturing method of the thin film transistor 20 of Figure 9. Referring to Figure 10A, a first source/drain 210 is formed on the substrate 100. An isolation material layer 110A' is formed on the first source/drain 210 and the substrate 100. A conductive material layer 220' is formed on the isolation material layer 110A'. A photoresist material layer 120A' is formed on the conductive material layer 220'. The photoresist material layer 120A' is irradiated with light L using the mask MK as a mask. Part of the light L passes through the mask MK and irradiates the photoresist material layer 120A'. In this embodiment, the photoresist material layer 120A' includes positive photoresist or negative photoresist.

Please refer to FIG. 10B , the exposed photoresist material layer 120A' is subjected to a development process to form a protruding structure 120A on the conductive material layer 220'. The protruding structure 120A has a second through hole 122 overlapping the first source/drain 210.

Referring to FIG. 10C , the conductive material layer 220′ is etched using the protrusion structure 120A as a mask to form a second source/drain 220 having an opening 222. The opening 222 of the second source/drain 220 overlaps the second through hole 122. In some embodiments, the etching of the conductive material layer 220′ includes dry etching, wet etching, or a combination thereof. In this embodiment, the etching process is performed using the protrusion structure 120A as a mask to form the second source/drain 220, thereby saving the cost of the mask. In addition, using the protrusion structure 120A as a mask can improve the alignment accuracy between the second source/drain 220 and the protrusion structure 120A, so that the second source/drain 220 is substantially aligned with the protrusion structure 120A.

Referring to FIG. 10D , the isolation material layer 110A′ is etched using the protrusion structure 120A and the second source/drain 220 as a mask to form the isolation structure 110A. The isolation structure 110A has a first through hole 112 overlapping the second through hole 122. In some embodiments, the etching of the isolation material layer 110A′ includes dry etching, wet etching, or a combination thereof. In this embodiment, the second source/drain 220 is used as a mask to perform an etching process to form the isolation structure 110A, thereby saving the cost of the mask. In addition, using the second source/drain 220 as a mask can improve the alignment accuracy between the second source/drain 220 and the isolation structure 110A, so that the second source/drain 220 is substantially aligned with the isolation structure 110A.

Finally, returning to FIG. 9 , the semiconductor structure 300, the gate dielectric layer 130 and the gate 230 are formed. At this point, the thin film transistor 20 is substantially completed.

FIG11 is a cross-sectional schematic diagram of a thin film transistor 30 according to an embodiment of the present invention. It must be noted that the embodiment of FIG11 uses the component numbers and partial contents of the embodiments of FIG1A to FIG8B, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, which will not be elaborated here.

The main difference between the thin film transistor 30 of FIG. 11 and the thin film transistor 10 of FIG. 8B is that in the thin film transistor 10 of FIG. 8B , the protrusion structure 120 is formed first, and then the semiconductor structure 300, the gate dielectric layer 130 and the gate 230 are formed. However, in the thin film transistor 30 of FIG. 11 , the semiconductor structure 300 and the gate dielectric layer 130 are formed first, and then the protrusion structure 120B and the gate 230 are formed.

12A to 12E are cross-sectional schematic diagrams of the manufacturing method of the thin film transistor 30 of FIG. 11 . Referring to FIG. 12A , a first source/drain 210 is formed on a substrate 100. Then, an isolation structure 110A and a second source/drain 220 are formed on the first source/drain 210. In this embodiment, the patterning process of the second source/drain 220 and the patterning process of the isolation structure 110A can be performed using the same photomask. For example, a blanket isolation material layer and a blanket conductive material layer are continuously deposited on the substrate 100 and the first source/drain 210. Then, a patterned photoresist layer is formed on the blanket conductive material layer using a photomask. Then, the conductive material layer and the isolation material layer located thereunder are etched once or multiple times using the patterned photoresist layer to form the second source/drain 220 and the isolation structure 110A. Finally, the patterned photoresist layer is removed. In this case, the shape of the vertical projection of the second source/drain 220 on the substrate 100 is substantially equal to the shape of the vertical projection of the isolation structure 110A on the substrate 100.

In other embodiments, the patterning process of the second source/drain 220 and the patterning process of the isolation structure 110A may be performed using different masks, such as the process of FIG. 2A to FIG. 3B .

Referring to FIG. 12B , a semiconductor structure 300 is formed on the second source/drain 220. The semiconductor structure 220 extends from the opening 222 of the second source/drain 220 along the sidewall of the first through hole 112 to the first source/drain 210. In this embodiment, the semiconductor structure 300 is formed on the top surface of the second source/drain 220 and contacts the top surface of the second source/drain 220, thereby providing a larger contact area between the semiconductor structure 300 and the second source/drain 220.

Please refer to FIG. 12C , a gate dielectric layer 130 is formed on the semiconductor structure 300.

Please refer to FIG. 12D , a photoresist material layer 120B' is formed on the second source/drain 220. In this embodiment, the photoresist material layer 120B' is formed on the gate dielectric layer 130.

Light L is irradiated from the side of the substrate 100 facing away from the first source/drain 210, and the light L irradiates the portion of the photoresist layer 120B' that is not shielded by the second source/drain 220. In this embodiment, part of the light L sequentially passes through the first source/drain 210, the semiconductor structure 300, and the gate dielectric layer 130, and irradiates the photoresist layer 120B' in the first through hole 112.

In this embodiment, the second source/drain 220 is used as a mask to perform an exposure process on the photoresist material layer 120B', and the light L is irradiated from the back side of the substrate 100 to the photoresist material layer 120B', but the present invention is not limited thereto. In other embodiments, other masks are additionally provided above the photoresist material layer 120B', and the aforementioned masks are used to perform an exposure process on the photoresist material layer 120B'.

Referring to FIG. 12E , the portion of the photoresist layer 120B' not shielded by the second source/drain 220 (i.e., the portion irradiated by light) is removed to form a protrusion structure 120B. In this embodiment, the protrusion structure 120B is separated from the second source/drain 220 and the semiconductor structure 300.

Finally, returning to FIG. 11 , a gate 230 is formed on the protrusion structure 120B. At this point, the thin film transistor 30 is substantially completed. In this embodiment, the gate 230 extends from the top surface of the protrusion structure 120B into the second through hole 122 and the first through hole 112. The gate 230 contacts the top surface of the protrusion structure 120B and the sidewall of the second through hole 122. In this embodiment, the gate dielectric layer 130 extends from between the protrusion structure 120B and the second source/drain 220 into the first through hole 112.

FIG13 is a cross-sectional schematic diagram of a thin film transistor 40 according to an embodiment of the present invention. It must be noted that the embodiment of FIG13 uses the component numbers and some contents of the embodiment of FIG11, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, which will not be elaborated here.

The main difference between the thin film transistor 40 of FIG. 13 and the thin film transistor 30 of FIG. 11 is that in the thin film transistor 30 of FIG. 11 , the material of the protrusion structure 120B includes cured photoresist, and the protrusion structure 120B has a single-layer structure. However, in the thin film transistor 40 of FIG. 13 , the material of the protrusion structure 120C includes other organic materials or inorganic materials other than the photoresist, and the protrusion structure 120C has a multi-layer structure.

Referring to FIG. 13 , the protrusion structure 120C includes a structure formed by stacking the first layers 121 and 123 together. In some embodiments, the method for forming the protrusion structure 120C includes the following steps: forming a blanket multi-layer insulating material on the gate dielectric layer 130. Then, forming a patterned photoresist layer on the aforementioned multi-layer insulating material. Then, performing an etching process on the aforementioned multi-layer insulating material using the patterned photoresist layer as a mask to form the protrusion structure 120C. Finally, removing the patterned photoresist layer.

In FIG. 13 , the protrusion structure 120C has a double-layer structure, but the present invention is not limited thereto. The protrusion structure 120C may also have a single-layer structure or a structure having three or more layers.

FIG. 14 is a graph showing the transmittance (T%) of the semiconductor structure and the first source/drain for light of different wavelengths (λ) according to some embodiments of the present invention. In some embodiments, when the light L is irradiated from the back side of the substrate 100 to the photoresist layer, the light needs to pass through the semiconductor structure 300 and the first source/drain 210, as shown in FIG. 4B and FIG. 12D. FIG. 14 shows the transmittance (T%) of indium tin oxide (ITO) with a thickness of 200 nm, indium gallium zinc oxide (IGZO) with a thickness of 200 nm, and a stacked layer of the former two for light of different wavelengths (λ). As shown in Figure 14, if the semiconductor structure and the first source/drain include IGZO and ITO respectively, the wavelength of the light is preferably 350nm to 1000nm to pass through the semiconductor structure and the first source/drain.

In summary, the present invention utilizes a protrusion structure to increase the distance between the gate and the second source/drain in a thin film transistor, thereby reducing the parasitic capacitance between the gate and the second source/drain, thereby increasing the reliability of the thin film transistor.

10: Thin Film Transistor

100: Substrate

110: Isolation structure

112: First through hole

120: Protrusion structure

122: Second through hole

130: Gate dielectric layer

210: First source/drain

220: Second source/drain

222: Open mouth

230: Gate

232: First electrode

234: Second electrode

300:Semiconductor structure

D1: First direction

Claims (10)

A thin film transistor comprises: a first source/drain located on a substrate; an isolation structure located on the first source/drain and having a first through hole overlapping the first source/drain; a second source/drain disposed on the isolation structure; a semiconductor structure extending from the second source/drain along the sidewall of the first through hole to the first source/drain; a gate dielectric layer located on the semiconductor structure; a protrusion structure located on the second source/drain and having a second through hole overlapping the first through hole; and A gate is located on the gate dielectric layer and extends from above the protrusion structure into the second through hole and the first through hole, wherein the first source/drain, the isolation structure, the second source/drain, the protrusion structure and the gate are stacked in sequence in a first direction. A thin film transistor as described in claim 1, wherein the thickness of the protrusion structure is 1 micron to 1.5 microns, and the thickness of the isolation structure is less than or equal to 0.5 microns. A thin film transistor as described in claim 1, wherein the semiconductor structure extends from the top surface of the protrusion structure into the second through hole and the first through hole, and the semiconductor structure contacts the top surface of the protrusion structure and the side wall of the second through hole. A thin film transistor as described in claim 1, wherein the gate extends from the top surface of the protrusion structure into the second through hole and the first through hole, and the gate contacts the top surface of the protrusion structure and the side wall of the second through hole. A thin film transistor as described in claim 1, wherein the gate dielectric layer extends from between the protrusion structure and the second source/drain into the first through hole. A method for manufacturing a thin film transistor, comprising: forming a first source/drain on a substrate; forming an isolation structure on the first source/drain, wherein the isolation structure has a first through hole overlapping the first source/drain; forming a second source/drain on the first source/drain; forming a semiconductor structure on the second source/drain, and the semiconductor structure extends from the second source/drain along the sidewall of the first through hole to the first source/drain; forming a gate dielectric layer on the semiconductor structure; forming a protrusion structure on the first source/drain, and the protrusion structure has a second through hole; and A gate is formed on the gate dielectric layer, wherein the first through hole overlaps the second through hole, and the gate extends from above the protrusion structure into the second through hole and the first through hole, wherein the first source/drain, the isolation structure, the second source/drain, the protrusion structure and the gate are stacked in sequence in a first direction. The manufacturing method as described in claim 6, wherein the method for forming the isolation structure on the first source/drain comprises: forming an isolation material layer on the first source/drain; forming a conductive material layer on the isolation material layer; forming the protrusion structure on the conductive material layer; etching the conductive material layer using the protrusion structure as a mask to form the second source/drain; and etching the isolation material layer using the protrusion structure and the second source/drain as masks to form the isolation structure. The manufacturing method as described in claim 6, wherein the method for forming the protrusion structure includes: forming a photoresist material layer on the second source/drain; irradiating light from the side of the substrate facing away from the first source/drain, wherein the light irradiates the portion of the photoresist material layer that is not shielded by the second source/drain, and part of the light is shielded by the second source/drain; and performing a developing process on the photoresist material layer to form the protrusion structure. A manufacturing method as described in claim 8, wherein the first source/drain comprises a transparent conductive layer, and a portion of the light passes through the first source/drain. The manufacturing method as described in claim 8, wherein the photoresist material layer is formed on the gate dielectric layer, and a portion of the light passes through the first source/drain, the semiconductor structure and the gate dielectric layer in sequence.

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