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TW201933543A - 形成半導體裝置結構之方法及相關的半導體裝置結構 - Google Patents

形成半導體裝置結構之方法及相關的半導體裝置結構 Download PDF

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TW201933543A
TW201933543A TW107130478A TW107130478A TW201933543A TW 201933543 A TW201933543 A TW 201933543A TW 107130478 A TW107130478 A TW 107130478A TW 107130478 A TW107130478 A TW 107130478A TW 201933543 A TW201933543 A TW 201933543A
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metal
nitride film
work function
gate dielectric
semiconductor device
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琦 謝
朱馳宇
基蘭 什雷斯塔
寶琳 卡爾卡
歐瑞斯特 馬蒂亞
珍 威廉 馬耶斯
麥可 尤金 吉凡斯
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荷蘭商Ａｓｍ智慧財產控股公司
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Abstract

本發明揭示一種形成半導體裝置結構之方法。該方法可包括於半導體基板上方沉積NMOS閘極介電質及PMOS閘極介電質，於該NMOS閘極介電質上方及該PMOS閘極介電質上方沉積第一功函數金屬，移除於該PMOS閘極介電質上方之該第一功函數金屬，且於該NMOS閘極介電質上方及該PMOS閘極介電質上方沉積第二功函數金屬。亦揭示包括藉由本揭示之方法所沉積之期望金屬閘極電極的半導體裝置結構。

Description

形成半導體裝置結構之方法及相關的半導體裝置結構
本揭示大致係關於形成半導體裝置結構之方法及相關的半導體裝置結構；特定言之，本揭示係關於形成用於NMOS及PMOS裝置結構兩者之閘極電極之方法。
習知互補金屬氧化物半導體(CMOS)技術係利用n-型及p-型多晶矽作為閘極電極材料。然而，經摻雜的多晶矽可能不是用於先進技術節點應用的理想閘極電極材料。舉例來說，儘管經摻雜的多晶矽係傳導性，其仍可能有在偏壓下會耗乏載流子之表面區域。此耗乏區域可呈現為額外的閘極絕緣體厚度，一般稱為閘極耗乏，且可增加等效氧化物厚度。雖然閘極耗乏區域可能係薄的，在數埃左右，但當閘極氧化物厚度在先進技術節點應用中減小時，其可能變得顯著。作為再一實例，對於NMOS及PMOS裝置兩者，多晶矽不呈現理想的有效功函數(eWF)。為克服經摻雜多晶矽的非理想有效功函數，可利用臨限電壓調整植入。然而，隨著裝置幾何形體於先進技術節點應用中減小，臨限電壓調整植入過程會變得愈來愈複雜。
為克服經摻雜多晶矽閘極電極的相關問題，可用替代材料來取代非理想的經摻雜多晶矽閘極材料，其諸如，比方說，金屬、金屬氮化物及金 屬碳化物。舉例來說，可利用金屬、金屬氮化物、或金屬碳化物之性質來提供用於NMOS及PMOS裝置兩者之更理想的有效功函數，其中閘極電極之有效功函數，即擷取電子所需之能量，可與半導體材料之能障高度相容。舉例來說，在PMOS裝置之情況中，有效功函數大約為5.0-5.2eV，而在NMOS裝置之情況中，有效功函數大約為4.1-4.3eV。因此，需要對於NMOS及PMOS裝置兩者形成具有較佳有效功函數之閘極電極的方法。
提供本內容概要以簡化形式來引介一些概念。此等概念更詳細地說明於以下揭示之實例具體例的詳細說明中。本概要不欲指出所主張標的物之關鍵特徵或基本特徵，亦不欲用來限制所主張標的物之範疇。
在一些具體例中，提供用來形成半導體裝置結構之方法。該方法可包括於半導體基板上方沉積NMOS閘極介電質及PMOS閘極介電質，於NMOS閘極介電質上方及PMOS閘極介電質上方沉積第一功函數金屬，移除於PMOS閘極介電質上方之第一功函數金屬，且於NMOS閘極介電質上方及PMOS閘極介電質上方沉積第二功函數金屬。
在其他具體例中，可提供半導體裝置結構。該半導體裝置結構可包括：設置於PMOS閘極介電質上方之PMOS閘極電極，其中該PMOS閘極電極包括直接設置於PMOS閘極介電質上方之金屬氮化物膜及直接設置於金屬氮化物膜上方之鉬膜。
在其他具體例中，可提供半導體裝置結構。該半導體裝置結構可包括：設置於NMOS閘極介電質上方之NMOS閘極電極，其中該NMOS閘極電極包括直接設置於NMOS閘極介電質上方之金屬氮化物膜、直接設置於金屬氮化物膜上方之第一功函數金屬、設置於第一功函數金屬上方之額外金屬氮化 物膜及設置於該額外金屬氮化物膜上方之鉬膜。
在又其他具體例中，可提供互補金屬氧化物半導體裝置結構。該CMOS裝置結構可包括：設置於PMOS閘極介電質上方之PMOS閘極電極，其中該PMOS閘極電極包括直接設置於PMOS閘極介電質上方之第一氮化鈦膜及直接設置於第一氮化鈦膜上方之鉬膜。該CMOS裝置結構亦可包括：設置於NMOS閘極介電質上方之NMOS閘極電極，其中該NMOS閘極電極包括直接設置於NMOS閘極介電質上方之第二氮化鈦膜、直接設置於第二氮化鈦膜上方之第一功函數金屬、設置於第一功函數金屬上方之第三氮化鈦膜及設置於第三氮化鈦膜上方之鉬膜。
為概述本發明之目的及相較於先前技術所達成之優點，本發明之某些目的及優點已於此描述於上文中。當然，應明瞭無須所有該等目的或優點皆可根據本發明之任何特定具體例來達成。因此，舉例而言，熟悉本技藝者當認知本發明可依達成或最佳化本文所教示或提出之一個優點或一組優點而無須達成本文中可能教示或提出之其他目的或優點的方式來具體化或實施。
此等具體例全部意欲在本文所揭示之本發明範疇內。此等及其他具體例將自以下參考附圖的某些具體例之詳細描述而對熟悉本技藝者變得顯而易見，但本發明並不受限於所揭示之任何特定具體例。
儘管本說明書以具體指出且明確主張被視為本發明之具體例的申請專利範圍作結，但在結合隨附圖式閱讀時可更容易自本揭示之具體例之某些實例的描述來確定本揭示之具體例的優勢，在隨附圖式中：圖1-11係根據本揭示之具體例所形成之包括閘極電極之半導體裝置結構的簡化橫截面圖。
儘管在下文中揭示特定具體例及實施例，但彼等熟悉本技藝者應理解，本發明延伸超出本發明所具體揭示之具體例及/或用途及其明顯修改及等效物。因此，期望所揭示之本發明範疇不應受限於下文所描述之特別揭示的具體例。
本文中呈現的繪示不意欲為任何特定材料、結構、或裝置的實際視圖，而僅係用來描述所揭示之具體例的理想化呈現。
如本文所使用，術語「循環沉積」可指將前驅體(反應物)連續引入至反應腔室中以在基板上方沉積一膜且包括諸如原子層沉積及循環化學氣相沉積之沉積技術。
如本文所使用，術語「循環化學氣相沉積」可指當中基板依序暴露於兩種或更多種揮發性前驅體之任何製程，該等前驅體在基板上反應及/或分解以產生所需沉積物。
如本文所使用，術語「基板」可指任何底層材料，其可被使用或在其上可形成裝置、電路或膜。
如本文所使用，術語「原子層沉積(ALD)」可指在處理腔室中實施沉積循環(較佳地複數個連續沉積循環)的氣相沉積製程。通常地，在各循環期間，前驅體化學吸附至沉積表面(例如基板表面或先前所沉積之底層表面，諸如來自先前ALD循環之材料)，從而形成不容易與其他前驅體反應(亦即自我限制反應)的單層或亞單層。之後，必要時可接著將反應物(例如另一前驅體或反應氣體)引入至處理腔室中以用於將經化學吸附之前驅體轉化為沉積表面上的所需材料。通常地，此反應物能夠進一步與前驅體反應。此外，亦可在各循環期間利用沖洗步驟自處理腔室移除過量前驅體及/或在轉化經化學吸附之前驅體 之後自處理腔室移除過量反應物及/或反應副產物。此外，如本文中所使用之術語「原子層沉積」在用前驅體組合物、反應氣體及沖洗(例如惰性載劑)氣體之交替脈衝執行時還意欲包括由相關術語指示之製程，諸如「化學氣相原子層沉積」、「原子層磊晶法(ALE)」、分子束磊晶法(MBE)、氣體源MBE或有機金屬MBE及化學束磊晶法。
如本文中所使用，術語「膜」及「薄膜」可指藉由本文中所揭示方法而沉積之任何連續或不連續結構及材料。舉例而言，「膜」及「薄膜」可包括2D材料、奈米棒、奈米管或奈米粒子，或甚至部分或完全分子層或部分或完全原子層或原子及/或分子之群集。「膜」及「薄膜」可包含具有針孔，但仍為至少部分連續之材料或層。
如本文中所使用，術語「功函數金屬」可指當形成於半導體裝置之閘極介電質之中、上或上方時所產生適當有效功函數的任何傳導性含金屬材料。
本揭示包括可用來形成包含一或多種功函數金屬之閘極電極的方法及半導體裝置結構，其中該等功函數金屬可利用諸如，比方說，原子層沉積製程的循環沉積製程來形成。可利用於閘極電極之ALD形成之現有的功函數金屬可能因其等不適當的有效功函數值而存在限制。舉例來說，已知材料的有效功函數可隨其厚度而改變。因此，隨著在先進技術節點應用中裝置幾何形體的減小，對應裝置膜(諸如閘極電極的功函數金屬)之厚度亦可減小並伴隨有效功函數值的改變。此一閘極電極之有效功函數的改變可導致針對NMOS及PMOS裝置結構兩者之非理想的有效功函數。因此需要提供更理想之閘極電極的方法及結構。該等方法及結構的實例更詳細地揭示於本文中。
以下揭示之非限制性實例具體例可使用非限制性實例的CMOS製程流程來說明，其在技藝中一般稱為「後閘極(gate last)」，其中閘極電極可 於源極/汲極區域形成及相關的高溫活化製程後形成。然而應明瞭，本文中說明的「後閘極」具體例係可利用於實例CMOS裝置結構(包括NMOS及PMOS裝置結構)之形成中之製程的非限制性實例具體例。本文中描述所揭示之具體例的方法及半導體裝置結構亦可包括在技藝中一般稱為「先閘極(gate first)」的CMOS製程流程，其中閘極電極可於源極/汲極形成及相關的高溫活化製程之前形成。常用的CMOS製程流程描述於發證給Machkaoutsan等人的美國專利第9,136,180號中並以引用方式併入本文。
應注意本文所描述之方法及半導體裝置結構的各種具體例包括半導體裝置結構之設計及組成中之各種熟知的步驟，因此為簡明起見，許多習知的步驟及結構在本文中僅簡單地提及或完全省略。另外，在整個當前揭示之具體例中給出多個實例材料，應注意針對各實例材料給出之化學式不應被認作限制性且所給出之非限制性實例材料不應受給定實例化學計量所限制。
在一些具體例中，本揭示之方法可包括將NMOS閘極介電質及PMOS閘極介電質沉積於半導體基板上方，將第一功函數金屬沉積於NMOS閘極介電質上方及PMOS閘極介電質上方，移除PMOS閘極介電質上方之第一功函數金屬，且將第二功函數金屬沉積於NMOS閘極介電質上方及PMOS閘極介電質上方。
詳言之，且參照圖1，半導體裝置結構100可包括半導體基板102及形成於半導體基板102之表面106上方的犧牲閘極結構104。半導體基板102可進一步包括PMOS區域108及NMOS區域110，其中可於隨後形成該等PMOS及NMOS源極/汲極及通道區域。為簡單描述揭示之具體例起見，圖1中僅繪示單個PMOS區域108及單個NMOS區域110；然而，應明瞭本文中揭示之方法及結構亦適用於包括大量PMOS區域及NMOS區域的半導體裝置結構。半導體基板102亦可包括淺溝槽隔離(STI)112，其中STI 112分離並刻劃PMOS區域108與 NMOS區域110。
半導體基板102可包括，例如，塊狀矽基板或絕緣體上矽(SOI)基板，其中該SOI基板進一步包括支撐基板及中間埋置氧化物層(未顯示)。在一些具體例中，半導體基板102可包括矽、鍺、矽鍺、碳化矽、或III-V族材料中之至少一者。在一些具體例中，半導體基板102可呈用於FinFET類型裝置中之鰭片結構的形式，而在圖1中，半導體基板102包含實質上平坦的表面106。
如圖1中所繪示，可將犧牲閘極結構104形成於半導體基板102之表面106上方。在一些具體例中，犧牲閘極結構104可包含犧牲閘極114及犧牲帽蓋116，其中該犧牲帽蓋116可直接形成於犧牲閘極114上方。犧牲閘極結構104可使用習知之製程步驟(諸如沉積、光微影、及蝕刻)來形成。犧牲閘極114可包含多晶矽材料及犧牲帽蓋116可包含氧化矽或氮化矽。
於犧牲閘極結構形成後，可將間隔件形成於犧牲閘極結構之任一側上，如圖2所繪示。詳言之，圖2繪示包括間隔件120的半導體裝置結構118。間隔件120可鄰近於犧牲閘極結構104之側面且於其上形成。在揭示之一些具體例中，間隔件120可包含氮化矽材料且可藉由ALD製程形成。
在間隔件形成後，可實施用於在半導體基板102中形成源極/汲極區域之製程，其包括，但不限於，蝕刻、磊晶沉積、應力技術、及使用犧牲閘極結構作為離子植入遮罩的離子植入。在半導體基板102中形成源極/汲極區域之製程可導致在半導體基板102中形成PMOS區域108及NMOS區域110(為簡單起見未顯示源極/汲極及通道區域之細節)。
揭示之具體例可繼續形成包含圍繞間隔件之介電質材料的層間介電質(ILD)。圖3繪示包含介電質材料124的半導體裝置結構122。介電質材料124可利用諸如化學氣相沉積(CVD)、低壓化學氣相沉積(LPCVD)、或電漿增強化學氣相沉積(PECVD)之沉積技術形成。可沉積介電質材料124，使得其填充 間隔件120之間的區域並覆蓋間隔件120及犧牲帽蓋116。隨後可將介電質材料124平面化，例如，利用化學機械拋光製程來提供平坦表面，犧牲帽蓋116則充作拋光停止指標。
在沉積ILD後，揭示之具體例可繼續移除犧牲閘極結構。舉例來說，圖4繪示半導體裝置結構126，其顯示於移除犧牲閘極結構，然而實質上完整地留下間隔件120之後的圖3之半導體裝置結構122。移除犧牲閘極結構可暴露間隔件120間之區域中的表面106。移除犧牲閘極結構包括形成閘極溝槽128，該等閘極溝槽以間隔件120及表面106為界。犧牲閘極結構係藉由蝕刻製程移除，蝕刻化學係經選擇使得間隔件120及介電質材料124未經蝕刻，或未經顯著地蝕刻。犧牲閘極結構可藉由乾式蝕刻製程、濕式蝕刻製程、或其組合移除。
揭示之具體例可繼續在閘極溝槽中形成界面層。如圖5所繪示，半導體裝置結構130可包括界面層132，其可形成在設置於閘極溝槽128中之半導體基板102之表面106上。在一些具體例中，界面層132可包含氧化矽且可利用化學氧化製程來氧化半導體基板102之表面106而選擇性地形成於表面106上。在一些具體例中，方法可包括形成設置於NMOS區域之通道區域上方及PMOS區域108之通道區域上方的界面層132。
揭示之具體例可進一步包括形成閘極介電質。作為一非限制性實例具體例，可將高k介電質材料之仿形層形成於圖5之半導體裝置結構130上方，從而產生如圖6所繪示之半導體裝置結構134。舉例來說，可將設置於NMOS區域110上方之高k介電質材料136指示為NMOS介電質136A及可將設置於PMOS區域108上方之高k介電質材料136指示為PMOS介電質136B。因此，在揭示之一些具體例中，形成NMOS閘極介電質136A及PMOS閘極介電質136B可包括直接於界面層132上方沉積高k介電質材料136。
在一些具體例中，高k介電質材料136可包含下列至少一者：氧化鉿(HfO2)、氧化鉭(Ta2O5)、氧化鋯(ZrO2)、氧化鈦(TiO2)、矽酸鉿(HfSiOx)、氧化鋁(Al2O3)或氧化鑭(La2O3)或其混合物/層合物。在一些具體例中，高k介電質材料136可包含下列至少一者：介電金屬氧化物，諸如過渡金屬氧化物或氧化鋁；金屬矽酸鹽；介電金屬氧氮化物或其混合物。在揭示之一些具體例中，高k介電質材料136可使用原子層沉積製程仿形地沉積。在一些具體例中，方法可包括將高k介電質材料136形成為具有大約小於2奈米之厚度。
揭示之具體例可進一步包括將第一功函數金屬沉積於NMOS閘極介電質上方及PMOS閘極介電質上方。詳言之且參照圖7，NMOS閘極電極140之一部分可沉積於NMOS閘極介電質及PMOS閘極介電質兩者上方。在揭示之一些具體例中，NMOS閘極電極140之該部分可包含第一襯層140A、第一功函數金屬140B及第二襯層140C。在一些具體例中，第一襯層140A及第二襯層140C可包含金屬氮化物，諸如過渡金屬氮化物，例如氮化鈦(TiN)、氮化鉭(TaN)、或氮化鈮(NbN)中之至少一者。在揭示之一些具體例中，第一襯層140A及第二襯層140C可皆包含氮化鈦，即分別為第一氮化鈦膜及第二氮化鈦膜。在揭示之一些具體例中，第一襯層140A及第二襯層140C皆包含經摻雜的氮化鈦(TiN)，其中該氮化鈦膜可摻雜碳(C)、矽(Si)、或硼(B)中之至少一者。
在揭示之一些具體例中，第一功函數金屬可包含金屬碳化物，諸如過渡金屬碳化物，例如碳化鈦(TiCx)、碳化鉭(TaC)、碳化鈦鋁(TiAlCx)或碳化鈮鋁或其混合物/層合物中之至少一者。在揭示之一些具體例中，第一功函數金屬可包含過渡金屬，諸如Ti、Ta、或Nb及另一金屬諸如Al及碳。在揭示之一些具體例中，該部分之NMOS閘極電極140可藉由循環沉積方法，諸如，比方說，原子層沉積製程或循環CVD製程來沉積。
詳言之，ALD製程典型上係基於自我限制反應，由此使用反應 物之依序且交替的脈衝來於每個沉積循環沉積約一個原子(或分子)單層的材料。沉積條件及前驅體通常經選擇以提供自飽和反應，使得一種反應物之吸收層留下不與同一反應物之氣相反應物反應的表面終端。接著使基板與不同反應物接觸，該不同反應物與先前終端反應以實現持續沉積。因此，交替脈衝之各循環通常留下不超過約單層的所需材料。然而，如上文所提及，熟習此項技術者將認知到在一或多個ALD循環中可沉積超過一個單層的材料，例如在不管製程之交替性質如何發生一些氣相反應時。
在用於沉積包含金屬氮化物及金屬碳化物之NMOS閘極電極140之一部分的ALD型製程中，一個沉積循環包含使基板暴露於第一反應物，自反應空間移除任何未反應之第一反應物及反應副產物，使基板暴露於第二反應物，繼而為第二移除步驟。第一氣相反應物可包含金屬前驅體，諸如鈦前驅體、鉭前驅體、或鈮前驅體。第二前驅體可包含氮前驅體、鋁前驅體、或碳前驅體。在一些具體例中，第二前驅體可包含鋁前驅體及碳前驅體兩者。
作為揭示之一非限制性實例具體例，第一襯層140A可包含第一氮化鈦膜(TiN)且可藉由原子層沉積製程直接沉積於高k介電質材料136之表面上方。舉例來說，氮化鈦之原子層沉積可包括沉積循環之第一「金屬階段」，其包括使基板與可包括鹵化鈦之第一氣相反應物接觸，使得經吸附單層經鹵素配位體封端。在一些具體例中，鹵化鈦可包括四氯化鈦(TiCl4)。在揭示之一些具體例中，鹵化鈦(例如，四氯化鈦)可於少於20秒、或少於10秒、或甚至少於5秒之時段內脈衝至反應空間中。
過量金屬前驅體(例如，鈦前驅體)及反應副產物(若存在)可例如藉由用惰性氣體沖洗而自基板表面移除。過量金屬前驅體及任何反應副產物可藉助於由抽汲系統產生之真空來移除。
在沉積循環之第二階段(「氮階段」)中，使基板與含氮前驅體 (諸如氨(NH3)或肼(N2H2))接觸。在揭示之一些具體例中，含氮前驅體可包含烷基肼前驅體，包括，但不限於，第三丁基肼(C4H9N2H3)、甲基肼(CH3NHNH2)、二甲基肼((CH3)2N2H2))。在揭示之一些具體例中，含氮前驅體可包含氮自由基、原子、或電漿。在揭示之一些具體例中，氮前驅體(例如，氨)可經脈衝至反應空間中持續少於20秒、或少於10秒、或甚至少於5秒之時段。氮反應物可與留在基板表面上之含鈦分子反應。較佳地，在第二階段中，氮藉由氮反應物與由金屬前驅體留下之單層的交互作用而納入至膜中。在一些具體例中，氮反應物與經化學吸附之金屬物種之間的反應於基板上方產生氮化鈦薄膜。
過量的第二源化學物質及反應副產物(若存在)係例如藉由沖洗氣體脈衝及/或由抽汲系統產生之真空而自基板表面移除。沖洗氣體較佳為任何惰性氣體，諸如，但不限於，氬氣(Ar)、氮氣(N2)、或氦氣(He)。若插入沖洗(亦即沖洗脈衝)或其他反應物移除步驟，則通常將一階段視為緊接在另一階段之後。
可將包括使基板與鈦前驅體接觸、沖洗反應空間、使基板與氮前驅體接觸及沖洗反應空間的沉積循環重複兩次或更多次，直至得到期望厚度的第一襯層140A(例如，第一氮化鈦膜)為止。在揭示之一些具體例中，第一襯層140A包含氮化鈦(TiN)且係經沉積至小於5埃、或小於15埃、或甚至小於30埃奈米之厚度。
在揭示之一些具體例中，基板可於原子層沉積製程期間經加熱至期望沉積溫度，因此，用於沉積第一襯層140A之ALD製程可於低於大約550℃、或低於大約350℃、或甚至低於大約150℃之基板溫度下進行。在揭示之其他具體例中，於其中發生第一襯層140A之原子層沉積的反應空間可利用流體連接至反應空間之抽汲系統而處於真空下。因此，在揭示之一些具體例中，用來沉積第一襯層之ALD製程可在低於10托(Torr)、或甚至低於5托、或甚至低 於1托之反應空間壓力下進行。
沉積該部分之NMOS閘極電極140的製程可藉由直接於第一襯層140A之表面上方，例如，直接於第一氮化鈦膜上方原子層沉積第一功函數金屬140B來進行。在揭示之一些具體例中，第一功函數金屬可包含碳化鈦(TiC)、碳化鉭、碳化鈦鋁(TiAlC)、或碳化鈮鋁(NbAlC)中之至少一者。
第一功函數金屬140B之原子層沉積可包含一沉積循環，其包括使基板與包含金屬前驅體之第一氣相反應物接觸、沖洗反應空間、使基板與包含碳前驅體及在一些具體例中之額外金屬前驅體之第二氣相反應物接觸、及沖洗反應空間。
在揭示之一些具體例中，第一功函數金屬之沉積可包含一沉積循環，其包括第一「金屬階段」，其中該第一金屬階段包括使基板與含鈦前驅體、含鉭前驅體、或含鈮前驅體接觸。在揭示之一些具體例中，ALD製程之第一金屬階段包括使基板與諸如，比方說，四氯化鈦(TiCl4)之鹵化鈦接觸。在揭示之一些具體例中，ALD製程之第一金屬階段包括使基板與諸如，比方說，五氯化鉭(TaCl5)之鹵化鉭接觸。在揭示之一些具體例中，ALD製程之第一金屬階段包括使基板與諸如，比方說，五氯化鈮(NbCl5)或五氟化鈮(NbF5)之鹵化鈮接觸。舉例來說，如第一功函數金屬包含碳化鈦或碳化鈦鋁，則ALD沉積循環之第一金屬階段可包括使基板與四氯化鈦(TiCl4)接觸，然而如第一功函數金屬包含碳化鈮鋁，則ALD沉積循環之第一金屬階段可包括使基板與五氯化鈮(NbCl5)接觸。在揭示之一些具體例中，基板可與第一金屬前驅體(例如，四氯化鈦)接觸達少於20秒、或少於10秒、或甚至少於1秒的時段。
過量金屬前驅體(例如，鈦前驅體)及反應副產物(若存在)可例如藉由用惰性氣體沖洗而自基板表面移除。過量金屬前驅體及任何反應副產物可藉助於由抽汲系統產生之真空來移除。
在利用來沉積第一功函數金屬140B之沉積循環的第二階段中，基板可與包含碳及額外含金屬前驅體中之至少一者的第二氣相反應物接觸。在揭示之一些具體例中，第一功函數金屬140B可包含碳化鈦及第二氣相反應物可包括含碳前驅體，包括，但不限於，硼源化合物、矽源化合物、磷源化合物、或烴。詳言之，硼源化合物可包含具有至少一個硼-碳鍵之硼化合物且可選自下列：具有式C2BnHn+x之碳硼烷，其中n係1至10之整數，及x係偶整數，較佳2、4或6。碳硼烷的實例可包含閉式-碳硼烷(C2BnHn+2)、巢式-碳硼烷(C2BnHn+4)、及蛛式-碳硼烷(C2BnHn+6)。
具有式R3NBX3之胺-硼烷加成物，其中R係直鏈或分支鏈C1至C10，較佳C1至C4烷基或H，及X係直鏈或分支鏈C1至C10，較佳C1至C4烷基、H或鹵素。
胺基硼烷，其中B上之一或多個取代基係根據式R2N之胺基，其中R係直鏈或分支鏈C1至C10，較佳C1至C4烷基或經取代或未經取代之芳基。適合之胺基硼烷的一實例為(CH3)2NB(CH3)2。
烷基硼或烷基硼烷，其中烷基通常為直鏈或分支鏈C1至C10烷基，較佳為C2至C4烷基。舉例來說，烷基硼可包含三乙基硼(CH3CH2)3B。
在揭示之一些具體例中，含碳前驅體可包含烷基矽化合物、或烷基磷化合物。在一些具體例中，含碳前驅體可包含烴，諸如，比方說，具有高氫/碳比的烴。在一些具體例中，含碳前驅體可包含金屬有機化合物，諸如，比方說，三甲基鋁(TMA)。過渡金屬碳化物之原子層沉積描述於發證給Elers等人的美國專利第6,800,552號中，並以引用方式併入本文。
在揭示之一些具體例中，第一功函數金屬140B可包含碳化鈦鋁或碳化鈮鋁及第二氣相反應物可包含含碳及鋁的前驅體，包括，但不限於，選 自由以下組成之群之一或多者的鋁烴化合物：三甲基鋁(TMA)、三乙基鋁(TEA)、氫化二甲基鋁(DMAH)、二甲基乙基胺鋁烷(DMEAA)、三甲基胺鋁烷(TEAA)、N-甲基吡咯啶鋁烷(MPA)、三異丁基鋁(TIBA)、及三-第三丁基鋁(TTBA)。在一些具體例中，鋁烴化合物包含鍵結至鋁之第三丁基配位體。在一些具體例中，鋁烴化合物包含至少一個或多個Al-C鍵。在一些具體例中，鋁烴化合物包含兩個或更少的Al-H鍵。在一些具體例中，鋁烴不包含Al-Al鍵。在一些具體例中，鋁烴化合物不包含氧及/或鹵化物。在一些具體例中，鋁烴化合物僅包含鋁、氫及碳而無其他元素。在揭示之一些具體例中，基板可與第二氣相反應物(例如，三甲基鋁)接觸達少於20秒、或少於10秒、或甚至少於1秒的時段。
可將包括使基板與第一含金屬前驅體接觸、沖洗反應空間、使基板與包含碳及額外金屬中之至少一者的第二氣相反應物接觸、及沖洗反應空間之用來沉積第一功函數金屬140B的沉積循環重複兩次或更多次，直至沉積得到期望厚度的第一功函數金屬為止。在揭示之一些具體例中，第一功函數金屬140B係經沉積至小於5奈米、或小於4奈米、或甚至小於3奈米之厚度。
在揭示之一些具體例中，基板可於第一功函數金屬140B之原子層沉積製程期間經加熱至期望沉積溫度，因此，用於沉積第一功函數金屬104B之ALD製程可於低於大約550℃、或低於大約400℃、或甚至低於大約300℃之基板溫度下進行。在揭示之其他具體例中，於其中發生第一功函數金屬140B之原子層沉積的反應空間可利用流體連接至反應空間之抽汲系統而處於真空下。因此，在揭示之一些具體例中，用來沉積第一功函數金屬層之ALD製程可在低於10托、或甚至低於5托、或甚至低於1托之反應空間壓力下進行。
過量第二氣相反應物(例如，TMA)及反應副產物(若存在)可例如藉由用惰性氣體沖洗而自基板表面移除。過量第二氣相反應物及任何反應副產 物可藉助於由抽汲系統產生之真空來移除。
NMOS閘極電極140之一部分的沉積可藉由沉積第二襯層140C來進行。在揭示之一些具體例中，第二襯層140C可直接沉積於第一功函數金屬140B之表面上方。在揭示之一些具體例中，第二襯層140C可包含氮化鈦、氮化鉭、或氮化鈮中之至少一者。在一些具體例中，第二襯層140C可包含氮化鈦，即第二鉭化鈦膜，且可藉由如本文中針對第一襯層140A所描述之相同或實質上相似的原子層沉積製程來沉積。在揭示之一些具體例中，第二襯層140C包含氮化鈦(TiN)且係經沉積至小於4奈米、或小於3奈米、或甚至小於2奈米之厚度。
在揭示之一些具體例中，藉由循環沉積製程(諸如，比方說，原子層沉積)形成於半導體基板上方之該部分的NMOS閘極電極140可如圖7所繪示沉積於三維結構上方，其中該部分之NMOS閘極電極140係沉積於半導體裝置結構138之閘極溝槽的上方及其中。因此，在一些具體例中，在具有縱橫比(高度/寬度)大於約2、大於5、大於約10、大於約25、大於約50、或甚至大於約100之結構中，NMOS閘極電極140之一部分的階梯覆蓋率可等於或大於約50%、或大於約80%、或大於約90%、或大於約95%、或大於約98%、或大於約99%、或甚至約100%。
在一些具體例中，NMOS閘極電極140之該部分的生長速率可低於約5Å/循環、或低於約2Å/循環、或甚至低於約1Å/循環。
揭示之具體例可繼續形成在第一功函數金屬之所選部分上方的遮罩層，其中該遮罩層界定在後續移除製程之後殘留之第一功函數金屬的區域。舉例來說，圖8繪示半導體裝置結構142，其包括可設置於第一功函數金屬140B之所選部分上方的遮罩層144。遮罩層144可使用諸如旋塗、沉積、光微影、顯影及蝕刻之常用半導體製程來形成並圖案化。在一些具體例中，揭示之方法可包括選擇遮罩層144以包含氧化矽、氮化矽、氧氮化矽、或聚合物材料 (例如，光阻劑)中之至少一者。遮罩層144可設置於可在後續移除製程之後殘留之第一功函數金屬140B的部分上方，即遮罩層可設置於NMOS閘極介電質136A上方。
揭示之具體例可進一步包括移除PMOS閘極介電質上方的第一功函數金屬。詳言之，圖9繪示半導體裝置結構146，其包含除了移除遮罩層外，於移除一部分之第一功函數金屬140之後的第一功函數金屬。移除PMOS閘極介電質上方之第一功函數金屬可包括選擇性地蝕刻設置於PMOS閘極介電質136B上方的第二襯層140C(例如，第二氮化鈦膜)，及選擇性地蝕刻設置於PMOS閘極介電質136B上方的第一功函數金屬140B。術語「選擇性地蝕刻」可係指其中以顯著高於第二材料之蝕刻速率蝕刻第一材料的蝕刻製程。舉例來說，第一材料(例如，第一功函數金屬)與第二材料(例如，下層第一襯層140A)間之蝕刻速率的比可包括大於3：1、5：1、或甚至10：1或甚至更大的蝕刻比。在揭示之一些具體例中，可能很難得到相對於下層第一襯層140C對第一功函數金屬140B具選擇性的選擇性蝕刻製程。因此，在揭示之一些具體例中，移除PMOS介電質136B上方之第一功函數金屬140B進一步包括移除至少一部分的第一襯層140A，例如，第一氮化鈦膜。在一些具體例中，移除PMOS介電質136B上方之第一功函數金屬140B可包括完全移除設置於PMOS介電質136B上方之區域的第一襯層140A。
在揭示之一些具體例中，選擇性地蝕刻第一功函數金屬140B進一步包括使第一功函數金屬140B暴露至氟基蝕刻化學或氯基蝕刻化學之至少一者。作為一非限制性實例，選擇性蝕刻製程可包括使第二襯層140C(例如，第二氮化鈦膜)及第一功函數金屬140B兩者暴露至六氟化硫(SF6)、四氟化碳(CF4)、或三氟化氮(NF3)中之至少一者。在揭示之其他具體例中，蝕刻第二襯層140C及第一功函數金屬140B可包括拋光、研磨或化學機械拋光移除製程中之 一或多者。如圖9所繪示，移除製程產生設置於NMOS閘極介電質136A上方之第一功函數金屬140B。
揭示之具體例可進一步包括將第二功函數金屬沉積於NMOS閘極介電質上方及PMOS閘極介電質上方。如圖10所繪示，半導體裝置結構148可包括可仿形地形成於NMOS閘極介電質136A上方及PMOS閘極介電質136B上方之第二功函數金屬150。在一些具體例中，第二功函數金屬150可在設置於PMOS閘極介電質136B上方之區域中直接設置於第一襯層140A(例如，第一氮化鈦膜)上方。在一些具體例中，第二功函數金屬150可在設置於NMOS閘極介電質136A上方之區域中直接設置於第二襯層140C上方及第一功函數金屬104B上方。如圖10所繪示，第二功函數金屬150不僅包含第二功函數金屬而且亦填充閘極溝槽結構，使得閘極溝槽的剩餘部分完全經第二功函數金屬150填充，因此，第二功函數金屬包含閘極填充金屬。
在揭示之一些具體例中，第二功函數金屬150可包含鉬膜，且鉬膜可利用循環沉積製程(諸如，比方說，原子層沉積製程)沉積。因此，沉積第二功函數金屬150之方法可包括使半導體基板交替地及依序地與鉬前驅體及還原劑前驅體接觸。舉例來說，在揭示之一些具體例中，沉積第二功函數金屬150可包括藉由原子層沉積來沉積鉬膜，該ALD製程包括一沉積循環，其包括使半導體基板與包含含鉬前驅體之第一氣相反應物接觸、沖洗反應空間、使半導體結構與包含還原劑前驅體之第二氣相反應物接觸、及第二次沖洗反應空間。
在揭示之一些具體例中，用來沉積第二功函數金屬150(例如，鉬膜)之沉積循環包括第一金屬階段，其包括使基板與包含含鉬前驅體之第一氣相反應物接觸。在一些具體例中，鉬前驅體可包含鉬及鹵素，諸如，比方說，氯化物。在一些具體例中，鉬前驅體可包含鉬、鹵素及硫屬化物，其中該硫屬 化物可包含氧。在一些具體例中，鉬前驅體可包含五氯化鉬(MoCl5)或二氯化二氧化鉬(MoO2Cl2)中之至少一者。在一些具體例中，含鉬前驅體可經脈衝至反應空間中持續少於20秒、或少於10秒、或甚至少於1秒之時段。
過量的第一氣相反應物(例如，五氯化鉬)及反應副產物(若存在)可例如藉由用惰性氣體沖洗而自基板表面移除。過量的第二氣相反應物及任何反應副產物可藉助由抽汲系統所產生之真空來移除。
用來沉積鉬膜之沉積循環的第二階段可包括一還原階段，其中使基板暴露至一或多種還原劑前驅體，其與存在於半導體基板上之鉬配位體反應，藉此形成鉬膜。因此，在揭示之一些具體例中，循環沉積循環之第二階段包括使半導體基板與還原劑前驅體接觸，該還原劑前驅體包含下列至少一者：氫(H2)、矽烷(SiH4)、二矽烷(Si2H6)、三矽烷(Si3H8)、鍺烷(GeH4)、二鍺烷(Ge2H6)、或二硼烷(B2H6)。在揭示之一些具體例中，還原劑前驅體可包含氫(H2)或氫自由基、原子、或電漿(即利用氫電漿所產生之氫的受激發物種，例如，遠端或直接電漿)。在一些具體例中，還原劑前驅體可包含具有一般實驗式SixH(2x+2)之較高級矽烷。在一些具體例中，還原劑前驅體可包含具有一般實驗式GexH(2x+2)之較高級鍺烷。在一些具體例中，還原劑前驅體可經脈衝至反應空間中持續少於20秒、或少於10秒、或甚至少於1秒之時段。
在揭示之一些具體例中，第二功函數金屬150可經沉積至一厚度，使得閘極溝槽完全經第二功函數金屬填充，即利用第二功函數金屬作為閘極填充金屬。舉例來說，在揭示之一些具體例中，第二功函數金屬150可包含經沉積至介於大約50奈米與300奈米之間或介於大約5奈米與50奈米之間之厚度的鉬膜。
在揭示之一些具體例中，基板可於第二功函數金屬150之原子層沉積製程期間經加熱至期望沉積溫度，因此，用於沉積第二功函數金屬150之 ALD製程可在低於大約750℃、或低於大約650℃、或低於大約550℃、或低於大約450℃、或低於大約350℃、或低於大約250℃、或甚至低於大約150℃之基板溫度下進行。在揭示之一些具體例中，第二功函數金屬之沉積可在介於300℃與750℃之間、或介於400℃與700℃之間、或介於450℃與600℃之間之基板溫度下進行。
在揭示之其他具體例中，於其中發生第二功函數金屬150之原子層沉積的反應空間可利用流體連接至反應空間之抽汲系統而處於真空下。因此，在揭示之一些具體例中，用來沉積第二功函數金屬層之ALD製程可在低於10托、或甚至低於5托、或甚至低於1托之反應空間壓力下進行。
在揭示之一些具體例中，藉由諸如，比方說，原子層沉積之循環沉積製程形成於半導體基板上方的第二功函數金屬150可如圖10所繪示沉積於三維結構上方，其中該第二功函數金屬完全填充閘極溝槽及因此包含閘極填充金屬。因此，在一些具體例中，在具有縱橫比(高度/寬度)大於約2、大於5、大於約10、大於約25、大於約50、或甚至大於約100之結構中，第二功函數金屬150之階梯覆蓋率可等於或大於約50%、或大於約80%、或大於約90%、或大於約95%、或大於約98%、或大於約99%、或甚至約100%。在其他具體例中，Mo膜可包含少於約20原子%氧、少於約10原子%氧、少於約5原子%氧、或甚至少於約2原子%氧。在其他具體例中，Mo膜可包含少於約10原子%氫、或少於約5原子%氫、或少於約2原子%氫、或甚至少於約1原子%氫。在一些具體例中，Mo膜可包含少於約10原子%之鹵化物/Cl、或少於約5原子%之鹵化物/Cl、少於約1原子%之鹵化物/Cl、或甚至少於約0.5原子%之鹵化物/Cl。在又其他具體例中，Mo膜可包含少於約10原子%碳、或少於約5原子%碳、或少於約2原子%碳、或少於約1原子%碳、或甚至少於約0.5原子%碳。在本文中概述的具體例中，元素之原子濃度可利用拉塞福回向散射(RBS；Rutherford backscattering)來 測定。
在一些具體例中，第二功函數金屬150之生長速率可低於約5Å/循環、或低於約2Å/循環、或甚至低於約1Å/循環。
在揭示之一些具體例中，在沉積第二功函數金屬150之前，可將第三襯層(未顯示)沉積於PMOS閘極介電質136B及NMOS閘極介電質136A上方。在一些具體例中，第三襯層可包含氮化鈦、氮化鉭、或氮化鈮中之至少一者。在一些具體例中，第三襯層可包含利用本文中描述之原子層沉積製程沉積之第三氮化鈦膜。第三氮化鈦膜可利用於其中移除階段完全或部分地移除設置於PMOS介電質136B上方之第一襯層140A的具體例中。因此，在揭示之一些具體例中，第一襯層140A之厚度可在設置於PMOS區域108與NMOS區域110上方者之間不同。
在揭示之一些具體例中，圖10之半導體裝置結構148包含直接設置於PMOS閘極介電質136B上方之金屬氮化物膜，諸如，比方說，氮化鈦。在一些具體例中，直接設置於PMOS閘極介電質136B上方之金屬氮化物膜包含第一襯層140C、或第三襯層，其取決於在移除製程期間是否完全移除第一襯層140C以移除設置於PMOS介電質136B上方之第一功函數金屬140C。在揭示之一些具體例中，可改變直接設置於PMOS閘極介電質136B上方之金屬氮化物膜的厚度，以使得能夠調節設置於PMOS閘極介電質上方之金屬閘極電極的有效功函數。舉例來說，在揭示之一些具體例中，直接設置於PMOS閘極介電質上方之金屬氮化物膜的厚度在大約5埃與大約30埃之間變化。在揭示之一些具體例中，設置於PMOS介電質136上方之金屬閘極電極包含直接與PMOS介電質136接觸之金屬氮化物膜140A(諸如，比方說，氮化鈦)及直接設置於金屬氮化物膜140A上方之再一第二有效功函數金屬(例如，鉬膜)。作為揭示之一非限制性實例具體例，PMOS裝置之閘極電極包含氮化鈦膜及鉬膜，及PMOS裝置之閘極 電極的有效功函數藉由改變直接與PMOS介電質136接觸之氮化鈦膜140A之厚度而改變(即調節)至較佳值。舉例來說，在一些具體例中，直接設置於PMOS閘極介電質上方之氮化鈦膜的厚度在大約5埃與大約30埃之間變化，導致PMOS閘極電極之有效功函數介於大約5.2eV與大約4.8eV之間。
在揭示之具體例中之後續製程可選擇性地自圖10之半導體裝置結構148之表面移除過量材料。如圖11之半導體裝置結構152所繪示，其中可利用一或多個蝕刻及/或拋光製程來形成平面化半導體裝置結構152。在圖11之半導體裝置結構152形成後，可進行進一步製程來完成半導體裝置結構，例如，完成互補金屬氧化物半導體(CMOS)裝置結構。舉例來說，後段製程可形成與閘極電極結構及與源極/汲極區域之接點以及形成於半導體基板102上之裝置間的互連。
揭示之具體例亦可包含根據揭示之方法所形成之半導體裝置結構。舉例來說，圖11繪示半導體裝置結構152，其包含設置於PMOS閘極介電質上方之PMOS閘極電極，其中該PMOS閘極電極包含直接設置於PMOS閘極介電質136B上方之金屬氮化物膜140A(諸如，比方說，氮化鈦)及直接設置於金屬氮化物膜140A上方之鉬膜150。在揭示之一些具體例中，PMOS閘極電極具有大於大約4.9eV、或大於大約5.0eV、或甚至大於大約5.1eV之有效功函數。在一些具體例中，直接設置於PMOS閘極介電質上方之金屬氮化物膜具有小於30埃之厚度。在一些具體例中，直接設置於金屬氮化物膜上方之鉬膜具有小於10奈米之厚度。在一些具體例中，PMOS閘極介電質136B可包含下列至少一者：氧化鉿(HfO2)、氧化鋁(Al2O3)、氧化鉭(Ta2O5)、氧化鋯(ZrO2)、氧化鈦(TiO2)、矽酸鉿(HfSiOx)及氧化鑭(La2O3)。在一些具體例中，鉬膜同時作為功函數金屬及閘極填充金屬，閘極填充金屬係設置於閘極溝槽中並填充閘極溝槽。在揭示之一些具體例中，直接設置於PMOS閘極介電質136B上之金屬氮化物膜140A的厚 度可改變，藉此改變閘極電極的有效功函數。舉例來說，金屬氮化物膜140A可包含氮化鈦膜且可具有介於大約5埃與大約30埃間之厚度，從而針對金屬閘極堆疊產生介於大約5.2eV與大約4.8eV之間之有效功函數。
圖11之半導體裝置結構152亦可包含設置於NMOS閘極介電質上方之NMOS閘極電極，其中該NMOS閘極電極包含直接設置於NMOS閘極介電質136A上方之金屬氮化物膜140A、直接設置於金屬氮化物膜140A上方之第一功函數金屬140B、設置於第一功函數金屬140B上方之額外金屬氮化物膜140C及直接設置於額外金屬氮化物膜140B上方之鉬膜150。
在揭示之一些具體例中，NMOS閘極電極具有低於4.5eV、或低於4.3eV、或甚至低於4.2eV之有效功函數。在揭示之一些具體例中，NMOS閘極電極具有4.3eV之有效功函數。在一些具體例中，直接設置於NMOS閘極介電質上方之金屬氮化物膜具有小於4奈米之厚度。在揭示之一些具體例中，金屬氮化物膜可包含氮化鈦、氮化鉭、或氮化鈮中之至少一者。在一些具體例中，第一功函數金屬140B包含碳化鈦(TiC)、碳化鉭(TaC)、碳化鈦鋁(TiAlC)、或碳化鈮鋁(NbAlC)中之至少一者，其中該第一功函數金屬140B具有小於4奈米之厚度。在一些具體例中，直接設置於第一功函數金屬上方之額外金屬氮化物膜140C具有小於3奈米之厚度。在揭示之一些具體例中，額外金屬氮化物膜140C可包含氮化鈦、氮化鉭、或氮化鈮中之至少一者。在一些具體例中，直接設置於額外金屬氮化物膜140C上方之鉬膜150具有小於10奈米之厚度。在一些具體例中，鉬膜包含閘極填充金屬，閘極填充金屬係設置於閘極溝槽中並填充閘極溝槽。在揭示之一些具體例中，鉬膜150具有小於大約50μΩcm、或小於大約30μΩcm、或甚至小於大約20μΩcm的電阻率。
揭示之具體例亦可包含如圖11所繪示的互補金屬氧化物半導體(CMOS)裝置結構。CMOS裝置結構可包含設置於PMOS閘極介電質上方之 PMOS閘極電極，其中該PMOS閘極電極包括直接設置於PMOS閘極介電質136B上方之第一氮化鈦膜140A及直接設置於第一氮化鈦膜140A上方之鉬膜150。CMOS裝置結構可進一步包含設置於NMOS閘極介電質上方之NMOS閘極電極，其中該NMOS閘極電極包括直接設置於NMOS閘極介電質136A上方之第二氮化鈦膜140A、直接設置於第二氮化鈦膜140A上方之第一功函數金屬140B、直接設置於第一功函數金屬上方之第三氮化鈦膜140C及直接設置於第三氮化鈦膜140C上方之鉬膜150。
上文所描述本揭示之實例具體例並不限制本發明的範疇，此係由於此等具體例僅為本發明之具體例的實例，其由所附申請專利範圍及其法定等效物定義。任何等效具體例意欲處於本發明之範疇內。實際上，除本文中所示及所描述者之外，本揭示之各種修改(諸如所描述之元件的替代性適用組合)根據描述對熟習此項技術者而言將變得顯而易見。該等修改及具體例同樣意欲屬於所附申請專利範圍之範疇內。

Claims (54)

  1. 一種形成半導體裝置結構之方法，其包含：於半導體基板上方沉積NMOS閘極介電質及PMOS閘極介電質；於該NMOS閘極介電質上方及該PMOS閘極介電質上方沉積第一功函數金屬；移除於該PMOS閘極介電質上方之該第一功函數金屬；及於該NMOS閘極介電質上方及該PMOS閘極介電質上方沉積第二功函數金屬。
  2. 如請求項1之方法，其中該第一功函數金屬包含金屬碳化物。
  3. 如請求項2之方法，其中該金屬碳化物包含碳化鈦、碳化鉭、碳化鈦鋁、或碳化鈮鋁中之至少一者。
  4. 如請求項1之方法，其中沉積第一功函數金屬進一步包含直接於該NMOS閘極介電質上方及直接於該PMOS閘極介電質上方沉積第一金屬氮化物膜。
  5. 如請求項4之方法，其中該第一金屬氮化物膜包含第一氮化鈦膜、第一氮化鉭膜、或第一氮化鈮膜中之至少一者。
  6. 如請求項5之方法，其中沉積第一功函數金屬進一步包含直接於該第一金屬氮化物膜上方沉積該第一功函數金屬。
  7. 如請求項1之方法，其中沉積第一功函數金屬進一步包含直接於該第一功函數金屬上方沉積第二金屬氮化物膜。
  8. 如請求項7之方法，其中該第二金屬氮化物膜包含第二氮化鈦膜、第二氮化鉭膜、或第二氮化鈮膜中之至少一者。
  9. 如請求項8之方法，其中移除該第一功函數金屬進一步包含移除該第二金屬氮化物膜。
  10. 如請求項4之方法，其中移除該第一功函數金屬進一步包含移除該第一金屬氮化物膜之至少一部分。
  11. 如請求項1之方法，其進一步包含於該NMOS閘極介電質上方及該PMOS閘極介電質上方沉積第三金屬氮化物膜。
  12. 如請求項11之方法，其中該第三金屬氮化物膜包含第三氮化鈦膜、第三氮化鉭膜、或第三氮化鈮膜中之至少一者。
  13. 如請求項1之方法，其中該第二功函數金屬包含鉬膜。
  14. 如請求項13之方法，其中該鉬膜包含閘極填充金屬。
  15. 如請求項1之方法，其中該第二功函數金屬係藉由循環沉積製程沉積。
  16. 如請求項15之方法，其中該循環沉積製程包含原子層沉積。
  17. 如請求項16之方法，其中該原子層沉積包含使該半導體基板交替地及依序地與鉬前驅體及還原劑前驅體接觸。
  18. 如請求項17之方法，其中該鉬前驅體包含鉬及鹵素。
  19. 如請求項18之方法，其中該鹵素包含氯化物。
  20. 如請求項18之方法，其中該鉬前驅體進一步包含硫屬化物。
  21. 如請求項20之方法，其中該硫屬化物包含氧。
  22. 如請求項18之方法，其中該鉬前驅體包含五氯化鉬(MoCl5)或二氯化二氧化鉬(MoO2Cl2)中之至少一者。
  23. 如請求項17之方法，其中該還原劑前驅體包含氫(H2)。
  24. 如請求項1之方法，其中該閘極介電質包含下列至少一者：氧化鉿(HfO2)、氧化鉭(Ta2O5)、氧化鋁(Al2O3)、氧化鋯(ZrO2)、氧化鈦(TiO2)、矽酸鉿(HfSiOx)或氧化鑭(La2O3)。
  25. 如請求項4之方法，其中改變該第一金屬氮化物膜之厚度，使 得能夠調節該PMOS閘極介電質上方之金屬閘極電極的有效功函數。
  26. 如請求項25之方法，其中該第一金屬氮化物膜之厚度係在5埃與30埃之間改變。
  27. 如請求項25之方法，其中改變該第一金屬氮化物膜之厚度產生具有介於大約4.8eV與大約5.2eV之間之有效功函數的PMOS金屬閘極電極。
  28. 如請求項1之方法，其中設置於該PMOS閘極介電質上方之PMOS金屬閘極電極包含直接設置於該PMOS閘極介電質上方之金屬氮化物膜及直接設置於該金屬氮化物膜上方之鉬膜。
  29. 如請求項28之方法，其中該金屬氮化物膜包含氮化鈦、氮化鉭、或氮化鈮中之至少一者。
  30. 如請求項1之方法，其中設置於該NMOS閘極介電質上方之NMOS金屬閘極電極包含直接設置於該NMOS閘極介電質上方之金屬氮化物膜、直接設置於該金屬氮化物膜上方之包含金屬碳化物之第一功函數金屬、直接設置於該第一功函數金屬上方之額外金屬氮化物膜及直接設置於該額外金屬氮化物膜上方之鉬膜。
  31. 如請求項30之方法，其中該金屬碳化物包含碳化鈦、碳化鉭、碳化鈦鋁或碳化鈮鋁中之至少一者。
  32. 如請求項30之方法，其中該金屬氮化物膜包含氮化鈦、氮化鉭、或氮化鈮中之至少一者。
  33. 如請求項30之方法，其中該額外金屬氮化物膜包含氮化鈦、氮化鉭、或氮化鈮中之至少一者。
  34. 如請求項28之方法，其中該PMOS金屬閘極電極具有大於5eV之有效功函數。
  35. 一種半導體裝置結構，其包括： 設置於PMOS閘極介電質上方之PMOS閘極電極，其中該PMOS閘極電極包括直接設置於該PMOS閘極介電質上方之金屬氮化物膜及直接設置於該金屬氮化物膜上方之鉬膜。
  36. 如請求項35之半導體裝置結構，其中該金屬氮化物膜包含氮化鈦、氮化鉭、或氮化鈮中之至少一者。
  37. 如請求項35之半導體裝置結構，其中該PMOS閘極電極具有大於5eV之有效功函數。
  38. 如請求項35之半導體裝置結構，其中該金屬氮化物膜具有小於30埃之厚度。
  39. 如請求項35之半導體裝置結構，其中該鉬膜具有小於300奈米之厚度。
  40. 如請求項35之半導體裝置結構，其中該PMOS閘極介電質包含下列至少一者：氧化鉿(HfO2)、氧化鋁(Al2O3)、氧化鉭(Ta2O5)、氧化鋯(ZrO2)、氧化鈦(TiO2)、矽酸鉿(HfSiOx)及氧化鑭(La2O3)。
  41. 如請求項35之半導體裝置結構，其中該鉬膜包含閘極填充金屬，該閘極填充金屬係設置於閘極溝槽中並填充閘極溝槽。
  42. 如請求項35之半導體裝置結構，其中該金屬氮化物膜具有介於大約5埃與大約30埃之間的厚度。
  43. 一種半導體裝置結構，其包括：設置於NMOS閘極介電質上方之NMOS閘極電極，其中該NMOS閘極電極包括直接設置於該NMOS閘極介電質上方之金屬氮化物膜、直接設置於該金屬氮化物膜上方之第一功函數金屬、設置於該第一功函數金屬上方之額外金屬氮化物膜及設置於該額外金屬氮化物膜上方之鉬膜。
  44. 如請求項43之半導體裝置結構，其中該金屬氮化物膜包含氮化 鈦、氮化鉭、或氮化鈮中之至少一者。
  45. 如請求項43之半導體裝置結構，其中該額外金屬氮化物膜包含氮化鈦、氮化鉭、或氮化鈮中之至少一者。
  46. 如請求項43之半導體裝置結構，其中該NMOS閘極電極具有大於4.2eV之有效功函數。
  47. 如請求項43之半導體裝置結構，其中該金屬氮化物膜具有小於30埃之厚度。
  48. 如請求項43之半導體裝置結構，其中該第一功函數金屬包含金屬碳化物。
  49. 如請求項48之半導體裝置結構，其中該金屬碳化物包含碳化鈦、碳化鉭、碳化鈦鋁、或碳化鈮鋁中之至少一者。
  50. 如請求項43之半導體裝置結構，其中該第一功函數金屬具有小於3奈米之厚度。
  51. 如請求項43之半導體裝置結構，其中該額外金屬氮化物膜具有小於3奈米之厚度。
  52. 如請求項43之半導體裝置結構，其中該鉬膜具有小於300奈米之厚度。
  53. 如請求項43之半導體裝置結構，其中該鉬膜包含閘極填充金屬，該閘極填充金屬係設置於閘極溝槽中並填充閘極溝槽。
  54. 一種互補金屬氧化物半導體(CMOS)裝置結構，其包括：設置於PMOS閘極介電質上方之PMOS閘極電極，其中該PMOS閘極電極包括直接設置於該PMOS閘極介電質上方之第一氮化鈦膜及直接設置於該第一氮化鈦膜上方之鉬膜；及設置於NMOS閘極介電質上方之NMOS閘極電極，其中該NMOS閘極電極 包括直接設置於該NMOS閘極介電質上方之第二氮化鈦膜、直接設置於該第二氮化鈦膜上方之第一功函數金屬、設置於該第一功函數金屬上方之第三氮化鈦膜及設置於該第三氮化鈦膜上方之鉬膜。
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TWI913951B (zh) 2024-08-17 2026-02-01 台灣積體電路製造股份有限公司 半導體裝置結構及其形成的方法

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KR20190032213A (ko) 2019-03-27
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US20200227325A1 (en) 2020-07-16
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