DE4035098A1 - Digital division circuit with combined decimal point and shift register control - has control circuit for operation of shift register stages via AND=circuit - Google Patents

Abstract

An electronic digital circuit is for use in the division of coded numbers. The main circuit consists of a number of subtractor modules in parallel, with shift register stages at the input and output (3,4). The registers are controlled by a module (60) that provides control of the comma position. The control circuit is based around flip-flops (5, 1, 52, 53). Outputs from the flip-flops are combined by logic gates (54-58) to generate register shift pulse control signals. ADVANTAGE - Simplified control of division circuit.

Description

The invention relates to an improvement of the combi nated comma and shift register additional control unit with the divider circuit according to P 40 32 814.7.

This divider circuit is in the present patent registration not shown completely, but only partially, because only this combined comma and shift register Control unit was improved. The missing details are thus the patent application P 40 32 814.7 remove.

The main circuit is shown in FIG . A tetrad subtraction circuit 5 is shown in FIG . In Fig. 3 the numeric input circuit 10 is illustrated. In FIG. 4, the control unit 20 with the result shift register 15 is shown. In FIG. 5, the decimal point and the shift register controller 60 is shown.

This dividing circuit consists of the main circuit 1 and the additional shift register 3 b and the digit input circuit 10 and the main control unit 20 , which is shown as part of the main control unit 20 , and the comma and shift register control unit 60 . The main circuit 1 is shown shortened by 2 or 3 or 4 sub-circuits and thus has 8 or 9 or 10 tetrad subtracting circuits 5 , the shift registers 3 and 4 are accordingly longer. The additional shift register 3 b is the right-hand extension of the shift register 3 . Shift register 3 is the dividend shift register and has parallel input and left shift by 4 bits per cycle. Shift register 4 is the divisor shift register and only has a left shift of 4 bits per cycle.

As the tetrad subtractor circuits 5 , real tetrad subtractor circuits can be used, or fake tetrad subtractor circuits, which form the difference digit by adding the nine's complement digit, like the fake tetrad subtractor circuit shown in FIG. 2. This spurious tetrad subtraction circuit shown in FIG. 2 consists of 16 AND circuits 11 with 2 inputs each and 10 OR circuits 12 with 2 inputs each and 2 OR circuits 13 with 3 inputs each and 8 negation circuits 14 and 2 dual Full adders 15 and 16 and the associated lines. Inputs A and B and outputs C are identified with the associated numerical values (numbers 5, 2, 1, 1 ). The carry input has the designation x. The carry output has the designation y.

The number input circuit 10 ( FIG. 3) consists of the keyboard N with keys for the numbers 0 and 1 to 9 and the key P for the decimal point and the OR circuit 21 with 9 inputs and the OR circuit 22 with 2 inputs and the OR circuit 23 with 5 inputs and 2 OR circuits 24 with 4 inputs each and the OR circuit 25 with 8 inputs and 2 gate circuits 26 and 27 , consisting of 4 AND circuits 28 each 2 inputs and the negation circuit 29 and the associated lines. The N keys are marked with the associated digits.

The main control unit 20 ( Fig. 4) consists of the pulse circuit 11 and the start circuit 12 and the pulse counter 13 and the circuit 14 and the quotient shift register 15 and the potential memory flip-flops 31 to 33 and the AND circuits 34 to 41 with 2 inputs each and the OR circuits 44 and 45 with 2 inputs each and the negation circuits 46 to 49 and the associated lines.

The combined comma and shift register control unit 60 ( FIG. 5) consists of 3 potential memory flip-flops 51 to 53 and the AND circuits 54 to 59 with 2 inputs each and the OR circuit 61 with 2 inputs and 2 Diodes 62 and the associated lines. The comma shift register consists of parts 7 a and 7 b.

The operation of this comma and shift register control unit results as follows: When the dividend is typed in, the flip-flops 51 and 52 are in their right position and the flip-flop 53 in its left position and thus become the same for each digit Shift registers 3 and 3 b and also the comma shift register 7 a are driven with one clock to the left and thus one digit after the other is stored in the dividend shift register (additional dividend shift register 3 b). Here, the AND circuit 54 is thus pre-activated and the AND circuit 59 is not pre-activated. The input of the comma of this dividend is triggered by tapping the P key, the output K of the circuit 10 driving the input k of the circuit 60 with an H pulse. Here, the AND circuit 56 is pre-activated and the comma index is thus set in the comma shift register 7 a via the OR circuit 61 . For the remaining digits after the decimal point, only shift registers 3 and 3 b and 7 a are driven with one cycle, the comma index in shift register 7 a thus being clocked to the left with the content of shift register 3 b. If this dividend does not have a comma, the following tap on the key D (division) not only flips the flip-flop 51 into its left position, but also the required closing comma (comma index) in the AND circuit 58 Comma shift register 7 a set. The AND circuit 55 is thus precontrolled and the divisor is typed into the shift register 4 , the comma also being typed in at the corresponding point using the P key. With respect to this divisor comma, the AND circuit 57 is pre-controlled, so that when this comma is typed in, only the flip-flop 52 is tilted into its left position. In the Divisorziffern after the decimal point, the shift register 7 a with a clock to the right each time is thus controlled, and thus processes the decimal point positions of the divisor in this way. If the dividend has 2 decimal places and the divisor also has 2 decimal places, the comma index is again at the entry position s. At the end of the division, the dividend in shift registers 3 and 3 b and the comma index in shift register 7 a are clocked to the left as soon as the output E of the circuit has 1 H potential. Thus, the dividend is initially clocked to the left until the output E of the main circuit has 1 L potential. Here, too, the comma shift register 7a is clock-driven and thus shifts the dividend to the corresponding point in the index stroke step to the left. At the end of the division, the result number (quotient) is stored in the shift register 15 and the comma index is in the corresponding bit of the comma shift register 7 b. The final processing of the result number (quotient) takes place in a result number shift circuit according to P 40 31 603.3 and in a zero input circuit according to P 40 31 897.4. The result number appears formally correct in the display field of the advertisement.

The input x of the circuit 5 a is constantly at H potential in the operating state.

Output A controls the parallel input into shift register 3 with H pulses.

Output B controls input b.

The output K controls the input k.

Output C controls input c.

Output F controls input f.

The output E controls the input e.

By pressing the D button the Input of the divisor pre-activated.

By pressing the G button the Division process triggered.

By pressing the R key, the entire dividing circuit reset.

The input T is at the clock frequency controlled.

The input h is in the operating state constantly at H potential.  

In FIG. 6, the decimal point and shift register control unit shown Normal 60.

The output shift register 15 is clock-driven to the right from output 1 .

From the output 2 , the comma shift register 7 b is clock-driven to the right.

From output 3 , divisor shift register 4 is clocked to the left.

From output 4 , the quotient shift register 15 is clock-driven to the left.

From the output 5 , the shift registers 3 and 3 b are clock-driven to the left.

From the output 6 , the comma shift register 7 a is clock-driven to the left.

From the output 7 , the comma shift register 7 b is clock-driven to the left.

From the output 8 , the comma shift register 7 a is clock-driven to the right.

From the output 9 , the comma index is set in the comma shift register 7 a.

Claims (5)

1. Electronic dividing circuit according to P 40 25 468.2, which is provided with a combined comma and shift register control unit ( 60 ), characterized in that the shift registers ( 15 ) and ( 7 b) are not from the output of the AND circuit ( 54 ) Clock-controlled. 2. Electronic divider circuit according to claim 1, characterized marked that for the first input number (Dividend) automatically a final comma is set, if this first input number (dividend) is not a comma having. 3. Electronic dividing circuit according to claim 1 or according to claim 1 and 2, characterized in that this comma and shift register control unit ( 60 ) from guide B has a result shift register ( 15 ) with 2 shift directions. 4. Electronic divider circuit according to claim 1 or according to claims 1 and 2 or according to claims 1 to 3, characterized in that the special versions with a result number shift circuit after P 40 31 603.3 are provided. 5. Electronic divider circuit according to claim 1 or according to claim 1 and 2 or according to claim 1 to 3 or according to claim 1 to 4 or according to claim 1 and 2 and 4, characterized in that the special version also with a zero input circuit after P 40 31 897.4 is provided.