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WO2012071878A1 - 一种晶体管的制造方法 - Google Patents

一种晶体管的制造方法 Download PDF

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Publication number
WO2012071878A1
WO2012071878A1 PCT/CN2011/075635 CN2011075635W WO2012071878A1 WO 2012071878 A1 WO2012071878 A1 WO 2012071878A1 CN 2011075635 W CN2011075635 W CN 2011075635W WO 2012071878 A1 WO2012071878 A1 WO 2012071878A1
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Prior art keywords
gate electrode
active region
gate dielectric
bottom gate
top gate
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English (en)
French (fr)
Inventor
张盛东
贺鑫
王龙彦
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Peking University Shenzhen Graduate School
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Peking University Shenzhen Graduate School
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Priority to US13/376,834 priority Critical patent/US9129992B2/en
Publication of WO2012071878A1 publication Critical patent/WO2012071878A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733—Multi-gate TFTs
    • H10D30/6734—Multi-gate TFTs having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass

Definitions

  • the present invention relates to the fabrication of transistors, and more particularly to a method of fabricating a dual gate thin film transistor.
  • the thin film transistor is one of the core devices in the flat panel display technology, and its performance directly affects the effect of the flat panel display.
  • the thin film transistor of the prior art includes a single gate structure and a double gate structure. Compared with single-gate thin film transistors, the double-gate structure has advantages of stronger driving capability, steeper subthreshold slope, and significantly reduced circuit footprint. Moreover, a reasonable and ingenious combination of dual gates enables new functional devices and circuits.
  • the biggest problem with double-gate structure thin film transistors, especially planar double gates is that their fabrication process is complicated, especially the self-alignment of structures is difficult to achieve. The methods proposed so far are all non-self-aligned.
  • Non-self-aligned processes can result in large dispersion of device characteristics and large parasitic components (such as parasitic capacitance) that are unacceptable for flat panel display applications. Therefore, how to obtain a self-aligned dual gate fabrication method has been a problem in the semiconductor transistor process.
  • the main technical problem to be solved by the present invention is to provide a method of fabricating a transistor, which can achieve precise alignment of the top gate electrode and the bottom gate electrode of the dual gate thin film transistor.
  • the present invention provides a method of manufacturing a transistor, including:
  • the conductive film is etched to form a top gate electrode by using a photoresist pattern formed by photolithography as a mask.
  • the bottom gate electrode is made of an opaque material.
  • a bottom gate dielectric layer is further formed between the bottom gate electrode and the active region, and a top gate dielectric is formed between the active region and the conductive film, after lithographic exposure And simultaneously etching the conductive film and the top gate dielectric to form a top gate electrode and a top gate dielectric layer respectively by using a photoresist pattern formed by photolithography; the substrate, the bottom gate dielectric layer, and the active layer
  • the region, the top gate dielectric and the conductive film are transparent materials.
  • sequentially forming the bottom gate electrode, the active region, and the conductive film on the front side of the substrate includes:
  • a metal oxide semiconductor layer for forming an active region is grown on the bottom gate dielectric layer, followed by growing an active region protective layer film, and then simultaneously photolithography and etching the metal oxide semiconductor layer and
  • the source region protective layer film forms an active region and an active region protective layer.
  • a region facing the bottom gate electrode and the top gate electrode is a channel region, and the two sides of the channel are respectively For the source and drain regions;
  • top gate dielectric on the protective layer, so that the top gate dielectric covers the active region and the protective layer and extends onto the bottom gate dielectric layer;
  • a conductive film for forming a top gate electrode is grown on the top gate dielectric.
  • the top gate electrode After forming the top gate electrode, it also includes bombarding the source and drain regions with plasma.
  • the plasma is argon, hydrogen or ammonia.
  • the energy when bombarded with argon plasma is 100-200 W and the gas pressure is 0.1-1 Torr.
  • the bottom gate electrode is made of chromium, molybdenum, titanium or aluminum, the bottom gate electrode has a thickness of 100-300 nm, and the top gate electrode is made of indium tin oxide or zinc aluminum oxide.
  • the thickness of the active region is zinc oxide or indium oxide, and the active region has a thickness of 50 to 200 nm.
  • the bottom gate dielectric layer and the top gate dielectric layer are made of silicon nitride or silicon oxide, and have a thickness of 100-400 nm, which is formed by chemical vapor deposition PECVD or magnetron sputtering.
  • the bottom gate dielectric layer and the top gate dielectric layer are alumina, yttria or yttria, having a thickness of 100 to 400 nm, and are grown by magnetron sputtering.
  • Figure 1 is a structural view showing the formation of a bottom gate electrode on a substrate
  • FIG. 2 is a schematic view showing the structure after forming a bottom gate dielectric layer, an active region, and an active region protective layer;
  • Figure 3 shows a structural view after forming a top gate dielectric layer
  • Figure 4 is a schematic view showing the structure at the time of exposure
  • FIG. 5 is a schematic structural view showing etching to form a top gate dielectric and a top gate electrode and plasma processing the source and drain;
  • Figure 6 shows the structure of Figure 5 after removing the photoresist
  • Figure 7 is a structural view showing a contact hole forming each electrode of a transistor
  • Fig. 8 shows a structural view after forming a metal electrode.
  • the manufacturing process of the double gate structure thin film transistor determines that the top gate electrode and the bottom gate electrode cannot be precisely aligned, which results in a large parasitic capacitance of the transistor, which limits its performance.
  • the invention adopts a self-aligned process to fabricate a thin film transistor having a double gate structure by an opaque design.
  • an opaque design is used in fabricating the bottom gate electrode, for example, opaque light can be used.
  • the material makes the bottom gate electrode opaque.
  • a design having a light transmitting property is employed, for example, a light transmitting material or a thickness design is used to have a light transmitting property;
  • the bottom gate electrode functions as a natural reticle by exposing upward from the back surface of the substrate, thereby improving alignment precision of the finally formed top gate electrode and bottom gate electrode.
  • Fig. 1 shows a structural view after forming a bottom gate electrode on a substrate.
  • the substrate 1 is made of a glass substrate or other substrate having light transmitting properties, and an opaque film having a thickness of 100 to 300 nm is grown on the substrate 1 by magnetron sputtering or thermal evaporation.
  • the material of the film may be Chromium, molybdenum, titanium or aluminum, etc.; the bottom gate electrode 2 is formed by photolithography or etching of the film.
  • the bottom gate electrode 2 may also adopt other materials having opaque characteristics, or may form an opaque film on the substrate 1 by using other film forming processes according to the requirements of the material, and the opaque film may be formed.
  • the thickness of the film may also vary depending on the properties of the material, as long as the parameters of the thin film transistor of the double gate structure are met and the requirements for opacity are achieved.
  • Figure 2 shows a schematic view of the structure after forming the bottom gate dielectric layer, the active region and the active region protective layer.
  • the bottom gate dielectric layer 3 may be an insulating dielectric film or a metal oxide film.
  • a thin film of insulating dielectric is grown on the substrate 1 and the bottom gate electrode 2 to cover the bottom gate electrode 2 and extend onto the substrate 1, for example, plasma enhanced chemical vapor deposition (PECVD) can be used.
  • PECVD plasma enhanced chemical vapor deposition
  • the method comprises: growing a 100-400 nm thick insulating dielectric film, wherein the insulating dielectric film is a silicon nitride film or a silicon oxide film, and the insulating dielectric film is used as the bottom gate dielectric layer 3.
  • a metal oxide film having a thickness of 100 to 400 nm may be grown by magnetron sputtering, and the material may be aluminum oxide, hafnium oxide or tantalum oxide, etc., and the metal oxide film is used as a bottom gate.
  • Dielectric layer 3 after the bottom gate dielectric layer 3 is grown, a 50-200 nm thick amorphous or polycrystalline metal oxide film and a 20-80 nm thick metal oxide film are sequentially deposited on the bottom gate dielectric layer 3.
  • an insulating dielectric film can be realized by a method of RF magnetron sputtering, and the active region 4 and the active region protective layer 5 are separately formed by photolithography and etching.
  • the material of the amorphous or polycrystalline metal oxide thin film for forming the active region may be zinc oxide based or indium oxide or the like, and when indium oxide is grown by sputtering the indium oxide metal oxide semiconductor thin film The purity of the ceramic target is equal to or better than 99.99%.
  • Fig. 3 shows a structural view after forming an active region and an active region protective layer.
  • a dielectric film of 100-400 nm thick is grown on the surface of the active region protective layer 5, and the dielectric film extends and covers the bottom gate dielectric layer 3.
  • the growth may be performed by magnetron sputtering to grow a layer of 100-400 nm.
  • a thick metal oxide film the material of which may be alumina, yttria or yttria; or a method of magnetron sputtering to grow a 100-400 nm thick insulating dielectric film, the material of which may be silicon nitride Or silicon oxide; plasma-enhanced chemical vapor deposition (PECVD) may also be used to grow a 100-400 nm thick insulating dielectric film, which may be made of silicon nitride or silicon oxide.
  • PECVD plasma-enhanced chemical vapor deposition
  • the metal oxide film or the insulating dielectric film and the active region protective layer 5 together form the top gate dielectric layer 6.
  • the material of the active region protective layer 5 may be the same as or different from the material of the top gate dielectric layer 3.
  • the active region protective layer 5 of FIG. 2 is made of silicon oxide
  • the insulating dielectric film of FIG. 3 is also made of silicon oxide.
  • the active region is formed by photolithography and etching, and no simultaneous formation is formed.
  • the source region protective layer 5, in this step, a metal oxide film or an insulating dielectric film for forming the top gate dielectric layer 6 is directly grown on the surface of the active region and extends to cover the surface of the bottom gate dielectric layer 3.
  • the active region protective layer 5 is formed in FIG. 2, and the upper surface of the active region can be protected from contamination and damage during the subsequent process by the blocking action of the active region protective layer 5, especially in photolithography and engraving.
  • the etching forms the active region 4 and the process of manufacturing the top gate dielectric layer 6 from contamination and damage.
  • the main pollution and damage are derived from the dry stripping or growth of the gate dielectric layer 6 after photolithography and etching of the active region 4.
  • the surface of the active region is defective, it is also possible to contaminate the active region 4 when the substrate is transferred between different processes, resulting in deterioration of the characteristics of the device.
  • a protective dielectric layer is immediately grown thereon, and the protective dielectric layer and the metal oxide semiconductor layer are separately formed into a protective layer by photolithography and etching. Active area protected by it.
  • the protective layer is finally used as a part of the top gate dielectric, the portion of the top gate dielectric that closely contacts the upper surface of the active region is grown together with the active region during fabrication, so that the combined effect of the active region and the top gate dielectric is more It is good to prevent contamination and damage to the upper surface of the active region during photolithography and etching of the active region and the fabrication of the top gate dielectric layer, so that the performance of the device is more stable.
  • Fig. 4 shows a schematic structural view at the time of exposure.
  • a transparent conductive film 70 of 100-300 nm thick is deposited by RF magnetron sputtering for forming the material of the top gate electrode 7.
  • the material of the conductive film 70 may be indium oxide. Tin or aluminum oxide zinc.
  • a positive resist is applied to the surface of the transparent conductive film 70, and when exposed, it is exposed from the back surface of the substrate 1, and the direction indicated by the arrow in the drawing is the exposure direction, and then development is performed.
  • the formed photoresist pattern is 8 in the figure, and the shape and size of the photoresist pattern 8 and the shape of the surface of the bottom gate electrode are the same as the mask of the bottom gate electrode in the photolithography. Same size as the two, and the two are right.
  • the coated photoresist can also be a negative photoresist.
  • the negative photoresist is formed by photolithography and the pattern formed by the positive photoresist is opposite to the pattern formed by the positive photoresist.
  • the aligned structure requires a lift-off technique.
  • the photoresist in the process of photolithographically forming the top gate electrode pattern, when the glue is applied, the photoresist is coated on the front surface of the transparent conductive film for forming the top gate electrode; when exposed, the exposure is performed from the back surface of the glass substrate; Since the glass substrate, the active region, and the conductive film have light transmitting characteristics, the bottom gate electrode has a light blocking property. Therefore, at the time of exposure, the bottom gate electrode functions as a natural reticle.
  • the cost of separately manufacturing the reticle is omitted, and on the other hand, since the bottom gate electrode is used as a reticle, the top gate electrode formed by etching the conductive film forms precise alignment with the bottom gate electrode, thereby reducing parasitic The generation of components improves the uniformity of device performance.
  • Fig. 5 shows a structure in which a top gate dielectric layer and a top gate electrode are formed.
  • the top gate dielectric 6 and the conductive film 70 covered with the photoresist pattern 8 are etched in FIG. 4 to form a top gate dielectric layer 61 and a top gate electrode 7, respectively.
  • a region facing the bottom gate electrode 2 and the top gate electrode 7 is a channel region, and regions on both sides of the channel region are a source region and a drain region, respectively.
  • the photoresist pattern 8 can be removed after the top gate dielectric layer 61 and the top gate electrode 7 are formed.
  • the source region and the drain region are plasma-treated first, so that on the one hand, the parasitic resistance of the source region and the drain region itself can be reduced, and on the other hand, during bombardment Since the photoresist pattern 8 has a protective effect on the top gate electrode 7, there is no need to worry about the plasma treatment affecting the top gate electrode.
  • the direction indicated by the arrow is the direction of bombardment of the plasma.
  • the surface of the source and drain regions is bombarded with a gas such as argon, hydrogen or ammonia to increase the carrier concentration, thereby reducing the parasitic resistance. value.
  • the argon plasma used has an energy of 100 to 200 W and a gas pressure of 0.1 to 1 Torr.
  • Figure 6 shows the structure of Figure 5 after removal of the photoresist.
  • the photoresist 8 on the top gate electrode 7 is removed, and it can be removed by acetone ultrasonic method or dry gel removal.
  • Fig. 7 is a view showing the structure of a contact hole for forming electrodes of the transistor.
  • a 100-300 nm thick silicon nitride layer 60 is deposited by magnetron sputtering or plasma enhanced chemical vapor deposition (PECVD), and then photolithographically and etched to form an extraction contact of each electrode. hole.
  • PECVD plasma enhanced chemical vapor deposition
  • 9 is a gate contact hole
  • 10 is a source contact hole
  • 11 is a drain contact hole.
  • Fig. 8 shows a structural view after forming a metal electrode.
  • a 100-300 nm thick metal titanium film is deposited by magnetron sputtering, and then the metal extraction electrode and the interconnection line of each electrode of the transistor are formed by photolithography and etching, and the top gate electrode is connected at the same time.
  • 12 is a gate lead
  • 13 is a source lead
  • 14 is a drain lead.
  • the value of the parasitic element such as the parasitic capacitance is reduced or absent due to the positive alignment between the bottom gate electrode and the top gate electrode, thereby improving the performance of the transistor.

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Description

一种晶体管的制造方法 技术领域
本发明涉及晶体管的制造，尤其是一种双栅薄膜晶体管的制造方法。
背景技术
薄膜晶体管作为开关控制元件或周边驱动电路的集成元件，是平板显示技术中的核心器件之一，其性能直接影响平板显示的效果。现有技术中的薄膜晶体管包括单栅结构和双栅结构。双栅结构与单栅结构的薄膜晶体管相比，具有更强的驱动能力、更陡的亚阈斜率、显著减少的电路占地面积等优势。而且，合理和巧妙使用双栅的组合能实现新功能的器件和电路。但是，双栅结构薄膜晶体管，尤其是平面双栅的最大问题是其制备工艺复杂，特别是结构的自对准难以实现。迄今所提出的方法均是非自对准的。非自对准的工艺会导致器件特性存在大的离散性和产生较大的寄生元件（比如寄生电容），而这是平板显示应用所不能接受的。因此如何获得自对准的双栅制造方法一直是半导体晶体管工艺中的难题。
 技术问题
本发明要解决的主要技术问题是，提供一种晶体管的制造方法，使用该方法能实现双栅薄膜晶体管的顶栅电极和底栅电极的精确对准。
 技术解决方案
为解决上述技术问题，本发明提供一种晶体管的制造方法，包括：
在衬底的正面依次形成底栅电极、有源区和导电薄膜；
在所述导电薄膜上涂布光刻胶，光刻曝光时，从所述衬底的背面进行曝光形成光刻胶图形；
以光刻后形成的光刻胶图形为掩膜，刻蚀所述导电薄膜形成顶栅电极。
其中，所述底栅电极为不透明材料制成。
在一种实施例中，在所述底栅电极和有源区之间还形成有底栅介质层，在所述有源区和导电薄膜之间还形成有顶栅介质，在光刻曝光后，以光刻后形成的光刻胶图形为掩膜同时刻蚀所述导电薄膜和所述顶栅介质分别形成顶栅电极和顶栅介质层；所述衬底、底栅介质层、有源区、顶栅介质和导电薄膜为透明材质。
在一种实施例中，在衬底的正面依次形成底栅电极、有源区和导电薄膜包括：
在衬底的正面生长一层金属薄膜，然后光刻和刻蚀所述金属薄膜形成底栅电极；
在所述衬底和所述底栅电极上生长一层底栅介质层；
在底栅介质层上生长一层用于形成有源区的金属氧化物半导体层，紧接着生长一层有源区保护层薄膜，然后同时光刻和刻蚀所述金属氧化物半导体层和有源区保护层薄膜形成有源区和有源区保护层，所述有源区中，位于所述底栅电极和顶栅电极正对的区域为沟道区，所述沟道的两侧分别为源区和漏区；
在保护层上生长一层顶栅介质，使顶栅介质覆盖有源区和保护层并延伸到所述底栅介质层上；
在顶栅介质上生长一层用于形成顶栅电极的导电薄膜。
在形成顶部栅电极后，还包括对源区和漏区用等离子进行轰击处理。
在一种实施例中，所述等离子为氩、氢或氨。
在一种实施例中，采用氩等离子轰击时的能量为100～200W，气压为0.1～1Torr
在一种实施例中，所述底栅电极的材料为铬、钼、钛或铝，所述底栅电极的厚度为100～300nm；所述顶栅电极的材料为氧化铟锡或氧化锌铝，厚度为100～300nm；所述有源区的材料为氧化锌基或氧化铟基，所述有源区的厚度为50～200nm。
在一种实施例中，所述底栅介质层和顶栅介质层的材料为氮化硅或氧化硅，厚度为100～400nm，由化学气相淀积PECVD或磁控溅射的方法生长而成，或者，所述底栅介质层和顶栅介质层为氧化铝，氧化钽或氧化铪，厚度为100～400nm，用磁控溅射的方法生长而成。
 附图说明
图1示出了在衬底上形成底栅电极后的结构图；
图2示出了在形成底栅介质层、有源区和有源区保护层后的结构示意图；
图3示出了形成顶栅介质层后的结构图；
图4示了曝光时的结构示意图；
图5示出了刻蚀形成顶栅介质和顶栅电极以及对源漏进行等离子处理的结构示意图；
图6示出了图5去除光刻胶后的结构；
图7示出了形成晶体管各电极的接触孔的结构图；
图8示出了形成金属电极后的结构图。
 本发明的实施方式
下面通过具体实施方式结合附图对本发明作进一步详细说明。
现有技术中，双栅结构的薄膜晶体管的制造工艺决定了其顶栅电极和底栅电极不可能精确对准，这导致晶体管存在较大的寄生电容，使其性能受到限制。本发明通过不透光的设计，采用自对准工艺制作双栅结构的薄膜晶体管，例如在一种实施例中，在制作底栅电极时采用不透光的设计，例如可采用不透光的材料使底栅电极不透光。而在制作衬底、顶栅电极以及底栅电极和顶栅电极之间的其它层时采用具有透光特性的设计，例如可采用透光材料或通过厚度的设计使其具有透光特性；在光刻形成顶栅电极图案时，通过从衬底的背面向上曝光，使底栅电极起到天然掩模版的作用，提高了最终形成的顶栅电极和底栅电极的对准精度。
下面以一种实施例为例，具体说明如何形成双栅结构的薄膜晶体管。
图1示出了在衬底上形成底栅电极后的结构图。衬底1采用玻璃衬底或其它具有透光特性的衬底，用磁控溅射或热蒸的方法在衬底1上生长一层厚度为100～300nm的不透明薄膜，该薄膜的材料可以是铬、钼、钛或铝等；通过光刻或刻蚀该薄膜形成底栅电极2。本领域技术人员可以理解，在其它实施例中，底栅电极2还可以采用其他具有不透光特性的材料，也可以根据材料的要求采用其它成膜工艺在衬底1上形成不透明薄膜，不透明薄膜的厚度也可以根据材料的性能而不同，只要符合双栅结构的薄膜晶体管的参数要求和达到不透光的要求即可。
图2示出了在形成底栅介质层、有源区和有源区保护层后的结构示意图。覆盖在底部栅电极2和衬底1上的是底栅介质层3，底栅介质层3可以是绝缘介质薄膜，也可以是金属氧化物薄膜。在一种具体实例中，在衬底1和底部栅电极2上生长一层绝缘介质薄膜，使其覆盖底部栅电极2并延伸到衬底1上，例如可以采用等离子增强化学汽相淀积PECVD的方法生长一层100～400nm厚的绝缘介质薄膜，该绝缘介质薄膜可以是氮化硅薄膜或氧化硅薄膜，该绝缘介质薄膜作为底栅介质层3。在另一具体实例中，也可以采用磁控溅射法生长一层100～400nm厚的金属氧化物薄膜，其材料可以是氧化铝，氧化钽或氧化铪等，该金属氧化物薄膜作为底栅介质层3；生长底栅介质层3后，再在底栅介质层3上依次淀积一层50～200nm厚的非晶或多晶的金属氧化物薄膜和20～80nm厚的金属氧化物薄膜或绝缘介质薄膜，可以采用射频磁控溅射的方法实现，经光刻和刻蚀分别形成有源区4和有源区保护层5。用于形成有源区的非晶或多晶的金属氧化物薄膜的材料可以是氧化锌基或氧化铟等，当为氧化铟时，溅射生长所述氧化铟金属氧化物半导体薄膜所述的陶瓷靶的纯度等于或优于99.99%。
图3示出了形成有源区和有源区保护层后的结构图。在有源区保护层5的表面生长一层100～400nm厚的介质薄膜，该介质薄膜延伸并覆盖底栅介质层3，生长的方法可以是用磁控溅射的方法生长一层100～400nm厚的金属氧化物薄膜，其材料可以是氧化铝，氧化钽或氧化铪等；也可以是用磁控溅射的方法生长一层100～400nm厚的绝缘介质薄膜，其材料可以是氮化硅或氧化硅；也可以是等离子增强化学汽相淀积PECVD生长一层100～400nm厚的绝缘介质薄膜，其材料可以是氮化硅或氧化硅等。该金属氧化物薄膜或绝缘介质薄膜与有源区保护层5共同形成顶栅介质层6，有源区保护层5的材料可以与顶栅介质层3的材料相同，也可以不同。比如，一种实施方式中，图2中有源区保护层5采用氧化硅，图3绝缘介质薄膜的材料也为氧化硅。
可以理解的是，在另外的实施例中，如果在图2所示步骤中，只生长用于形成有源区的金属氧化物薄膜，经光刻和刻蚀形成有源区，没有同时形成有源区保护层5，则此步中，直接在有源区表面生长一层用于形成顶栅介质层6的金属氧化物薄膜或绝缘介质薄膜并延伸覆盖底栅介质层3的表面。在图2中形成有源区保护层5，可以通过有源区保护层5的阻挡作用保护有源区的上表面在后序的工艺过程中免受污染和损伤，尤其是在光刻和刻蚀形成有源区4和制造顶栅介质层6的过程中免受污染和损伤，主要污染和损伤来源于在光刻和刻蚀有源区4后，干法去胶或生长栅介质层6时可能使有源区表面出现缺陷，也有可能当基片在不同工序间传递时污染有源区4，导致器件的特性变坏。
本实施例在生长用于形成有源区的金属氧化物半导体层后，立刻在其上生长一层保护介质层，同时光刻和刻蚀保护介质层和金属氧化物半导体层分别形成保护层和被其保护的有源区。该保护层虽然最终作为顶栅介质的一部分，相当于顶栅介质紧贴有源区上表面的部分在制造时与有源区是一同生长的，使得有源区和顶部栅介质的结合效果更好，并且防止在光刻和刻蚀有源区及制造顶栅介质层时，对有源区上表面的污染和损坏，使器件的性能更加稳定性。
图4示出了曝光时的结构示意图。在图3结构的基础上，首先，采用射频磁控溅射淀积一层100～300nm厚的透明导电薄膜70，用于形成顶栅电极7的材料，该导电薄膜70的材料可以是氧化铟锡或氧化铝锌等。然后，在透明导电薄膜70的表面涂布一层正性光刻胶，曝光时，从衬底1的背面曝光，图示中箭头所示方向为曝光方向，然后进行显影。光刻显影后，形成的光刻胶图形为图示中的8，由于光刻中底部栅电极起到掩膜版的作用，因此光刻胶图形8的形状和大小与底部栅电极表面的形状和大小相同，并且两者之间正对。可以理解的是，涂布的光刻胶也可以是负性的光刻胶，负性光刻胶经光刻显影后形成的图形与正性光刻胶形成的图形相反，此时要形成自对准的结构需采用剥离（lift-off）技术。
本实施例在光刻形成顶栅电极图案的过程中，涂胶时，在用于形成顶栅电极的透明导电薄膜的正面涂布光刻胶；曝光时，从玻璃衬底的背面进行曝光；由于玻璃衬底、有源区和导电薄膜具有透光特性，底部栅电极具有遮光特性。因此，曝光时，底部栅电极起到了天然掩模版的作用。此种方式，一方面省去了另外制造掩模版的成本，另一方面，由于底部栅电极作为掩模版，刻蚀导电薄膜形成的顶部栅电极与底部栅电极形成精确对准，减小了寄生元件的产生，提高了器件性能的均匀性。
图5示出了形成顶栅介质层和顶栅电极的结构。刻蚀图4中覆盖有光刻胶图形8的顶栅介质6和导电薄膜70，分别形成顶栅介质层61和顶栅电极7。有源区4中，底栅电极2和顶栅电极7之间正对的区域是沟道区，沟道区两侧的区域分别为源区和漏区。形成顶栅介质层61和顶栅电极7后即可去除光刻胶图形8。
在另一实施例中，在保留光刻胶8的情况下，先对源区和漏区进行等离子处理，这样一方面可减小源区和漏区自身的寄生电阻，另一方面，轰击时，由于光刻胶图形8对顶栅电极7有保护作用，不必担心等离子处理对顶栅电极造成影响。如图5所示，箭头所示方向为等离子的轰击方向，处理时，采用氩、氢或氨等气体轰击源区和漏区的表面，增加其载流子浓度，从而减小其寄生电阻的值。比如， 一种实施方式中，采用的氩等离子的能量为100～200W，气压为0.1～1Torr。
图6示出了图5去除光刻胶后的结构。去除顶栅电极7上的光刻胶8，可以采用丙酮超声的方法或干法去胶去除。
图7示出了形成晶体管各电极的接触孔的结构图。在图6结构的基础上，用磁控溅射法或等离子增强化学汽相淀积PECVD淀积一层100～300nm厚的氮化硅层60，然后光刻和刻蚀形成各电极的引出接触孔。在一种实施方式中，9为栅极接触孔，10为源极接触孔，11为漏极接触孔。
图8示出了形成金属电极后的结构图。在图7结构的基础上用磁控溅射法淀积一层100～300nm厚的金属钛膜，然后光刻和刻蚀形成晶体管各电极的金属引出电极和互连线，同时连接顶部栅电极7和底部栅电极2。在一种实施方式中，12为栅极引出线，13为源极引出线，14为漏极引出线。
采用以上方法制作的双栅金属氧化物薄膜晶体管，由于底栅电极和顶栅电极之间正对准，使得寄生电容等寄生元件的值减小或没有，从而提高了晶体管的性能。
以上内容是结合具体的实施方式对本发明所作的进一步详细说明，不能认定本发明的具体实施只局限于这些说明。对于本发明所属技术领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本发明的保护范围。

Claims (10)

  1. 一种晶体管的制造方法，其特征在于，包括：
    在衬底的正面依次形成底栅电极、有源区和导电薄膜；
    在所述导电薄膜上涂布光刻胶，光刻曝光时，从所述衬底的背面进行曝光形成光刻胶图形；
    根据光刻后形成的光刻胶图形刻蚀所述导电薄膜形成顶栅电极。
  2. 如权利要求1所述的晶体管的制造方法，其特征在于，所述底栅电极为不透明材料制成。
  3. 如权利要求2所述的晶体管的制造方法，其特征在于，在所述底栅电极和有源区之间还形成有底栅介质层，在所述有源区和导电薄膜之间还形成有顶栅介质，在光刻曝光后，以光刻后形成的光刻胶图形为掩膜同时刻蚀所述导电薄膜和所述顶栅介质分别形成顶栅电极和顶栅介质层；所述衬底、底栅介质层、有源区、顶栅介质和导电薄膜为透明材质。
  4. 如权利要求3所述的晶体管的制造方法，其特征在于，所述在衬底的正面依次形成底栅电极、有源区和导电薄膜具体包括：
    在衬底的正面生长一层金属薄膜，然后光刻和刻蚀所述金属薄膜形成底栅电极；
    在所述衬底和所述底栅电极上生长一层底栅介质层；
    在底栅介质层上生长一层用于形成有源区的金属氧化物半导体层，紧接着生长一层有源区保护层薄膜，然后同时光刻和刻蚀所述金属氧化物半导体层和有源区保护层薄膜分别形成有源区和覆盖所述有源区上表面的保护层，所述有源区中，位于所述底栅电极和顶栅电极正对的区域为沟道区，所述沟道的两侧分别为源区和漏区；
    在保护层上生长一层顶栅介质，使顶栅介质覆盖有源区和保护层并延伸到所述底栅介质层上；
    在顶栅介质上生长一层用于形成顶栅电极的导电薄膜。
  5. 如权利要求4所述的晶体管的制造方法，其特征在于，所述保护层和顶栅介质层的材质相同或不同。
  6. 如权利要求1所述的晶体管的制造方法，其特征在于，在形成顶部栅电极后，还包括对源区和漏区用等离子进行轰击处理。
  7. 如权利要求6所述的晶体管的制造方法，其特征在于，所述等离子为氩、氢或氨。
  8. 如权利要求7所述的晶体管的制造方法，其特征在于，采用氩等离子轰击时的能量为100～200W，气压为0.1～1Torr
  9. 如权利要求1所述的晶体管的制造方法，其特征在于，所述底栅电极的材料为铬、钼、钛或铝，所述底栅电极的厚度为100～300nm；所述顶栅电极的材料为氧化铟锡或氧化铝锌，厚度为100～300nm；所述有源区的材料为氧化锌基或氧化铟基，所述有源区的厚度为50～200nm。
  10. 如权利要求2所述的晶体管的制造方法，其特征在于，所述底栅介质层和顶栅介质层的材料为氮化硅或氧化硅，厚度为100～400nm，由化学气相淀积PECVD或磁控溅射的方法生长而成，或者，所述底栅介质层和顶栅介质层为氧化铝、氧化钽或氧化铪，厚度为100～400nm，用磁控溅射的方法生长而成。
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