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WO2014085971A1 - 一种金属氧化物tft器件及制造方法 - Google Patents

一种金属氧化物tft器件及制造方法 Download PDF

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Publication number
WO2014085971A1
WO2014085971A1 PCT/CN2012/085792 CN2012085792W WO2014085971A1 WO 2014085971 A1 WO2014085971 A1 WO 2014085971A1 CN 2012085792 W CN2012085792 W CN 2012085792W WO 2014085971 A1 WO2014085971 A1 WO 2014085971A1
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Prior art keywords
gate
layer
drain
source
electrode
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English (en)
French (fr)
Inventor
魏鹏
余晓军
刘自鸿
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Shenzhen Royole Technologies Co Ltd
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Shenzhen Royole Technologies Co Ltd
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Priority to PCT/CN2012/085792 priority Critical patent/WO2014085971A1/zh
Priority to CN201280001860.6A priority patent/CN104040693B/zh
Publication of WO2014085971A1 publication Critical patent/WO2014085971A1/zh
Priority to US14/731,081 priority patent/US9543328B2/en
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    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
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Definitions

  • the invention belongs to the technical field of electronic devices, and in particular relates to a metal oxide TFT device and a manufacturing method thereof.
  • TFT Metal oxide thin film transistor
  • Cgs gate-source parasitic capacitance
  • Cgd gate-drain parasitic capacitance
  • the prior art has a self-aligned device which is a device designed by a specific process to automatically align the source, the drain and the gate during the process manufacturing process, without manual or Alignment of the source, drain and gate can be achieved by mechanically optically aligning two different masks.
  • This self-aligned device is widely used in traditional single crystal silicon chips ( In the manufacturing process of MOSFETs, however, the self-aligned process of transistors in conventional silicon chips cannot be directly applied to metal oxide TFTs.
  • the prior art proposes a self-aligned process, using a top gate as a mask, automatically aligning to form a source, a drain, and passing Ar
  • the surface of the metal oxide indium gallium zinc oxide (IGZO) is treated by plasma or NH3 plasma containing more hydrogen to reduce the contact resistance of the source and drain, but Ar
  • the plasma only partially improves the surface resistance of the source and drain regions in contact with the metal.
  • the source and drain regions are still very resistant, and the plasma and other processes require an additional process to increase the cost, and hydrogen can diffuse into the channel. Extending the source and drain regions to the channel, resulting in an increase in the overlap region of the gate and the source and drain, and a large parasitic capacitance, thereby reducing the metal oxide
  • the performance of TFT devices are described in order to solve this problem.
  • etch barrier layer needs to be formed over the semiconductor layer to form separately by double exposure Etching the barrier layer and the source and drain, and the two back exposure self-alignments increase the use of the lithography mask and greatly increase the difficulty of the process. At the same time, the etch barrier also adversely affects the semiconductor channel, which in turn affects the TFT. Electrical characteristics.
  • An object of the present invention is to provide a method of fabricating a metal oxide TFT device, which is intended to solve the conventional method A problem that creates parasitic capacitance and is complicated in process.
  • the present invention is achieved by a method of fabricating a metal oxide TFT device comprising the steps of:
  • An insulating layer, a semiconductor layer and a photoresist are sequentially disposed on the gate;
  • a passivation layer is deposited on the substrate and the source and drain are taken out of the passivation layer.
  • Another object of the present invention is to provide a metal oxide TFT device comprising:
  • a gate electrode and an insulating layer are sequentially stacked on the substrate;
  • a source and a drain are disposed side by side on the semiconductor layer, and an inner side of the source and the drain are aligned with both sides of the gate;
  • a passivation layer encapsulating one side of the substrate with a gate
  • the source and drain are led out of the passivation layer by a conductive material.
  • An insulating layer, a semiconductor layer and a photoresist are sequentially disposed on the gate, the gate lead and the storage capacitor electrode;
  • a passivation layer is deposited onto the substrate and the source, drain, and gate leads are drawn out of the passivation layer.
  • It is still another object of the present invention to provide a metal oxide TFT pixel circuit comprising:
  • a gate electrode, a gate lead and a storage capacitor electrode are disposed side by side on the substrate;
  • An insulating layer disposed on the gate, the gate lead and the storage capacitor electrode
  • a source and a drain are disposed side by side on the semiconductor layer, and an inner side of the source and the drain are aligned with both sides of the gate;
  • a passivation layer encapsulating one side of the substrate with a gate
  • the source, drain and gate leads are led out of the passivation layer by a conductive material.
  • the bottom gate is used as a mask, the position of the semiconductor channel is covered by the photoresist by one back exposure, and the alignment of the source drain and the gate is realized by the method of stripping the photoresist, and the process is simple and the alignment precision is high.
  • the overlapping area of the source and drain electrodes and the gate can be precisely controlled 2 ⁇ m Within the specification, it is much higher than the precision of the traditional mask alignment, effectively reducing the parasitic capacitance, improving the circuit speed of the device, and making the channel size control more precise, which is beneficial to minimize the channel size and improve the device performance. .
  • the source and drain electrodes are formed by stripping the photoresist, it is not necessary to form an etch barrier layer, and only one back exposure is required, thereby simplifying the process, reducing the use of the lithography mask, and improving the production efficiency. And the adverse effect of the etch stop layer on the semiconductor channel is avoided.
  • the source and drain do not need to use a transparent material, so that the selectivity of the electrode material is greatly improved.
  • mask alignment in the production process is no longer a critical alignment requirement, which reduces manufacturing difficulties.
  • FIG. 1 is a schematic structural view of a conventional metal oxide thin film transistor device
  • FIG. 2 is a flow chart showing a method of manufacturing a metal oxide TFT device according to a first embodiment of the present invention
  • 3-1 to 3-11 are metal oxide TFTs provided by the first embodiment of the present invention.
  • FIG. 4 is a schematic structural view of a metal oxide TFT device according to a first embodiment of the present invention.
  • FIG. 5 is a flow chart showing a method of manufacturing a metal oxide TFT pixel circuit according to a second embodiment of the present invention.
  • 6-1 to 6-11 are metal oxide TFTs according to a second embodiment of the present invention.
  • FIGS. 3-1 ⁇ 3-11 A schematic structural view corresponding to the manufacturing method is shown, and for convenience of explanation, only the portions related to the present embodiment are shown.
  • the method includes the following steps:
  • step S101 a substrate 11 is selected, and a gate 12 is prepared on the substrate 11; as shown in FIG. 3-1 .
  • the substrate 11 is selected to be made of a material transparent to light waves used in the photolithography process, and then the gate is formed using the first photolithographic mask. 12 .
  • a buffer layer may be disposed on the substrate 11.
  • step S102 an insulating layer 13, a semiconductor layer 14, and a photoresist are sequentially disposed over the gate electrode 12. ; Figure 3-2, 3-3, 3-4.
  • an insulating layer 13 is first deposited over the substrate 11 and the gate 12, as shown in Fig. 3-2. Then in the insulating layer A semiconductor layer 14 is deposited over 13 , such as a metal oxide semiconductor such as IGZO, and a portion of the semiconductor layer 14 that is aligned with the gate electrode 12 is a channel 141 Used to provide a channel for carrier transfer between source and drain, as shown in Figure 3-3. Thereafter, a photoresist 15 is applied over the semiconductor layer 14 for subsequent lithography, as shown in FIG. 3-4.
  • step S103 the gate 12 is used as a mask, and is exposed from the back of the substrate 11, leaving the semiconductor layer 14 covered.
  • the photoresist portion of the channel portion 15 as shown in Figures 3-4, 3-5.
  • the metal material as the gate electrode 12 is opaque, and the other structures are transparent materials, so the gate electrode 12 As a mask, it can be exposed and developed from the back of the substrate 11, and the portion of the photoresist 15 opposite to the gate electrode 12 is not exposed, and the other exposed portions are peeled off, so that only the semiconductor layer is covered.
  • the channel portion of the photoresist 15 is covered.
  • step S104 an electrode layer 16 is deposited over the semiconductor layer 14 and the remaining photoresist 15; as shown in Fig. 3-6a .
  • the electrode layer 16 may be a non-transparent metal electrode layer.
  • an electrode contact layer 17 before depositing the electrode layer 16, and then deposit the electrode layer 16
  • the electrode contact layer 17 is used to reduce the contact resistance and improve the carrier injection efficiency, as shown in Fig. 3-6b.
  • step S105 the remaining photoresist 15 and the electrode layer 16 covering the photoresist 15 are stripped away to expose the gate. 12 Aligned channel 141; as shown in Figure 3-7.
  • step S106 the remaining electrode layer 16 and the semiconductor layer 14 are etched to form an isolated source 161 and a drain. 162; as shown in Figure 3-8.
  • This step can be formed by a second lithography mask 20, which is simple in process and does not require precise alignment of the mask.
  • step S107 a passivation layer 18 is deposited on the substrate 11, and the source 161 and the drain 162 are deposited. Lead out to the passivation layer 18. See Figures 3-9, 3-10, 3-11.
  • the passivation layer 18 can be etched using a third photolithographic mask to form a source 161 and a drain.
  • a via 181 of 162 is then deposited with a conductive material 19, preferably a transparent conductive material, such as a transparent metal, to the passivation layer 18.
  • the conductive material 19 covers the passivation layer 18 and is implanted into the via 181. Medium contact with source 161 and drain 162.
  • the conductive material 19 is etched using a fourth lithography mask, and conductive leads are formed to lead the source 161 and the drain 162.
  • a metal oxide TFT device is fabricated, it being understood that the above is only for the metal oxide TFT
  • the manufacturing process of the main structure of the device has been described.
  • the device also includes other conventional functional structures, which can be fabricated by conventional methods, and will not be described in detail herein.
  • the bottom gate is used as a mask, and the position of the semiconductor channel is covered by the photoresist by one back exposure, and the source drain and the gate are realized by the method of stripping the photoresist.
  • the self-alignment of the channel is simple in process and high in alignment accuracy.
  • the overlap area of the source and drain electrodes and the gate can be precisely controlled at 2 ⁇ m Within the specification, it is much higher than the precision of the traditional mask alignment, effectively reducing the parasitic capacitance, improving the circuit speed of the device, and making the channel size control more precise, which is beneficial to minimize the channel size and improve the device performance. .
  • the source and drain electrodes are formed by stripping the photoresist, it is not necessary to form an etch barrier layer, and only one back exposure is required, thereby simplifying the process, reducing the use of the lithography mask, and improving the production efficiency. And the adverse effect of the etch stop layer on the semiconductor channel is avoided.
  • the source and drain do not need to use a transparent material, so that the selectivity of the electrode material is greatly improved.
  • mask alignment in the production process is no longer a critical alignment requirement, which reduces manufacturing difficulties.
  • the embodiment of the present invention further provides a metal oxide TFT based on the above manufacturing method.
  • a device which can be fabricated by the above manufacturing process.
  • the device is a bottom gate, top contact structure TFT device, which mainly includes a substrate 11 on the substrate 11
  • the gate electrode 12, the insulating layer 13 and the semiconductor layer 14 are stacked in this order, and the source electrode 161 and the drain electrode 162 are arranged side by side on the surface of the semiconductor layer 14, and the semiconductor layer 14 is at the source.
  • a channel 141 is formed between the 161 and the drain 162 for carrier transport, and both sides of the channel 141 are aligned with the inner sides of the source 161 and the drain 162.
  • a passivation layer is provided on the substrate 11 18, Seal all structures above the substrate 11 inside. Wherein the source 161 and the drain 162 are led out to the passivation layer through the conductive material 19 In addition, an electrical connection is made to an external circuit.
  • an electrode contact layer 17 may be disposed between the semiconductor layer 14 and the source 161 and the drain 162. It is used to reduce contact resistance, improve carrier injection efficiency, and thus improve the electrical characteristics of TFT devices.
  • the passivation layer 18 may be provided with a via 181 to the source 161 and the drain 162, and the via 181
  • the transparent conductive material 19 is filled with the source 161 and the drain 162 out of the passivation layer 18.
  • the source 161 and the drain 162 and the gate 12 of the device are as described above by the method of back exposure and stripping of the photoresist.
  • the overlap area can be reduced to less than 2 ⁇ m, effectively reducing parasitic capacitance and improving device performance.
  • the metal oxide TFT may also include other functional structures, which are not described in detail in the embodiment, and the metal oxide TFT device fabricated by the above method is within the protection scope of the present invention.
  • Embodiment 2 is a diagrammatic representation of Embodiment 1:
  • FIG. 5 is a flow chart showing a method of manufacturing a metal oxide TFT pixel circuit according to a second embodiment of the present invention.
  • 6-1 to 6-11 show schematic structural views corresponding to the manufacturing method, and for convenience of explanation, only parts related to the present embodiment are shown.
  • the method includes the following steps:
  • step S201 a substrate 21 is selected, and a gate 221 and a gate lead 222 are prepared on the substrate 21. And storage capacitor electrode 223; as shown in Figure 6-1.
  • a buffer layer may also be disposed on the substrate 21.
  • step S202 an insulating layer is sequentially disposed over the gate electrode 221, the gate lead 222, and the storage capacitor electrode 223. 23, semiconductor layer 24 and photoresist 25; as shown in Figures 6-2, 6-3, 6-4.
  • an insulating layer 23 is first deposited over the substrate 21 and the gate 221, as shown in Fig. 6-2. Then in the insulating layer A semiconductor layer 24 is deposited on top of the semiconductor layer 24, such as a metal oxide semiconductor such as IGZO, and a portion of the semiconductor layer 24 opposite to the gate electrode 221 is a channel 241. Used to provide a channel for carrier transfer between source and drain, as shown in Figure 6-3. Thereafter, a photoresist 25 is applied over the semiconductor layer 24 for subsequent lithography, as shown in Figure 6-4.
  • step S203 the gate electrode 221, the gate lead 222 and the storage capacitor electrode 223 are used as a mask from the substrate 21
  • the metal material as the gate electrode 221 is opaque, and the other structures are transparent materials, so the gate electrode 221 As a mask, it can be exposed and developed from the back of the substrate 21, and the portion of the photoresist 25 opposite to the gate 221 is not exposed, and the other exposed portions are peeled off, so that only the semiconductor layer is covered.
  • the channel 241 of the photoresist 25 is covered.
  • step S204 an electrode layer 26 is deposited over the semiconductor layer 24 and the remaining photoresist 25; 6-6a.
  • the electrode layer 26 may be a non-transparent metal electrode layer.
  • an electrode contact layer 27 before depositing the electrode layer 26, and then deposit the electrode layer 26
  • the electrode contact layer 27 is used to reduce the contact resistance and improve the carrier injection efficiency, as shown in Fig. 6-6b.
  • step S205 the remaining photoresist 25 and the electrode layer 26 covering the photoresist 25 are stripped off, exposed and gated. 221, the portion of the gate lead 222 and the storage capacitor electrode 223 are aligned; as shown in Figure 6-7.
  • step S206 the remaining electrode layer 26 and the semiconductor layer 24 are etched to remove the gate lead 222 and the storage capacitor electrode.
  • the upper electrode layer 26 and the semiconductor layer 24 form an isolated source 261 and drain 262 over the gate 221 . As shown in Figure 6-8.
  • This step can be formed by a second lithography mask 30, which is simple in process and requires no precise alignment of the mask.
  • step S207 a passivation layer 28 is deposited on the substrate 21, and the source 261, the drain 262, and the gate lead are deposited. 222 is taken out of the passivation layer 28 . See Figures 6-9, 6-10, 6-11.
  • the passivation layer 28 may be etched using a third lithography mask to form a source 261 and a drain. 262 and a via 281 of the gate lead 222, and then depositing a conductive material 29, preferably a transparent conductive material, to the passivation layer 28, the conductive material 29 covering the passivation layer 28 and injecting vias In 281, it is in contact with source 261, drain 262, and gate lead 222. Then, the conductive material 29 is etched by using a fourth lithography mask to form a conductive lead to source 261 and drain 262. And the gate lead 222 leads.
  • Inverter gate The gate lead and the storage capacitor electrode are masks, and the source drain and the semiconductor channel are automatically aligned by back exposure and stripping of the photoresist to form a metal oxide of the self-aligned bottom gate and top contact structure. TFT Pixel circuit. This method has the same effect as the above embodiment, and will not be described in detail in this embodiment.
  • Embodiments of the present invention further provide a metal oxide TFT pixel circuit which can be fabricated by the above method.
  • the TFT pixel circuit of the bottom gate and top contact structure mainly includes a substrate 21 on the substrate 21 A gate electrode 221, a gate lead 222 and a storage capacitor electrode 223 are arranged side by side, and an insulating layer 23 is disposed on the gate electrode 221 and the storage capacitor electrode 223 in the insulating layer 23 A surface of the surface corresponding to the gate electrode 221 is provided with a semiconductor layer 24, and a source electrode 261 and a drain electrode 262 are arranged side by side on the semiconductor layer 24, and the semiconductor layer 24 is located at the source electrode 261 and the drain electrode. Between 262 is a channel 241 for carrier transport, and both sides of the gate 221 are aligned with the inner sides of the source 261 and the drain 262.
  • a passivation layer 28 is provided on the substrate 21. All the structures above the substrate 21 are sealed. The source 261, the drain 262, and the gate lead 222 are led out to the passivation layer through the conductive material 29 In addition, an electrical connection is made to an external circuit.
  • an electrode contact layer 27 may be disposed between the semiconductor layer 24 and the source 261 and the drain 262. It is used to reduce contact resistance, improve carrier injection efficiency, and thus improve the electrical characteristics of TFT devices.
  • the passivation layer 28 may have a via 281 that opens to the source 261, the drain 262, and the gate lead 222.
  • the via 281 is filled with a transparent conductive material 29 that leads the source 261, the drain 262, and the gate lead 222 out of the passivation layer 28.
  • the source 261 and the drain 262 and the gate 221 of the device are formed by the above-described method of back exposure and stripping of the photoresist.
  • the overlap area can be reduced to less than 2 ⁇ m, effectively reducing parasitic capacitance and improving device performance.
  • the pixel circuit may further include other functional structures, which are not described in detail in the embodiment, and the metal oxide TFT pixel circuit fabricated by the above method is within the protection scope of the present invention.

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Abstract

提供一种金属氧化物薄膜晶体管（TFT）器件的制造方法，包括：选取基板，在基板上制备栅极（S101）；在栅极上依次设置绝缘层、半导体层及光刻胶（S102）；以栅极为掩膜，自基板背部曝光，保留覆盖半导体层的沟道部分的光刻胶（S103）；向半导体层和光刻胶之上沉积电极层（S104）；剥离光刻胶及覆盖光刻胶的电极层，露出沟道（S105）；刻蚀电极层和半导体层，形成隔离的源漏极（S106）；沉积钝化层，将源漏极引出（S107）。该方法以栅极为掩膜，通过背部曝光及剥离光刻胶的方式实现自对准，工艺简单且对准精度高，减弱了寄生电容，提高了器件性能，且不需制作刻蚀阻挡层，简化了工艺，避免了刻蚀阻挡层对半导体沟道的不良影响，且掩膜板对准不再是关键的对准要求，降低了制造难度。

Description

一种金属氧化物 TFT 器件及制造方法 技术领域
本发明属于电子器件技术领域，特别涉及一种金属氧化物 TFT 器件及其制造方法。
背景技术
金属氧化物薄膜晶体管 (TFT) 是一种可广泛用于各种电子系统的基本电路组成器件，其具有多种优势，如高电子迁移率、低温制造工艺、较高的稳定性、透明度高等等。如图 1 所示，在传统的 TFT 制造工艺中， TFT 器件的栅极 (Gate)101 与源极 (Source)102 、漏极 (Drain)103 的对准是采用两层不同的掩膜板通过手动或者机械的光学对准方式实现的。 由于对准设备的精度等因素的限制，这种方式会导致源极 102 、漏极 103 与栅极 101 之间存在一定的重叠，因而产生较大的栅源寄生电容 (Cgs) 及栅漏寄生电容（ Cgd ）。 较大的寄生电容通常会降低器件的截止频率 ( 截止频率反比于寄生电容 ) ，从而降低电路的运行速度；并且，较大的寄生电容也导致显示电极电压偏离设计要求，从而需要复杂的栅极驱动电路来补偿偏差，增加了电路设计的复杂性；此外，无法精确控制的寄生电容也增加了电路设计的复杂性和不确定性，并使沟道 (Channel) 的最小尺寸无法精确，进而限制了沟道尺寸的最小化，从而难以提高器件的性能。另外，传统器件中使用多层掩膜板也会增加工艺复杂度并增加成本，不利于提高生产效率。
为了解决上述问题，现有技术出现一种自对准器件，它是一种通过特定的工艺设计、可以在工艺制造过程中自动将源极、漏极与栅极相对准的器件，无需手动或者通过机械光学对准两层不同掩膜板即可实现源极、漏极与栅极的对准。这种自对准器件广泛应用于传统的单晶硅芯片（ MOSFET ）的制造过程中，但是，传统硅芯片中的晶体管的自对准工艺却无法直接应用于金属氧化物 TFT 上。
为解决该问题，现有技术提出一种自对准工艺，利用顶栅极作为掩膜，自动对准形成源、漏极，并通过 Ar 等离子体或者含氢较多的 NH3 等离子体处理金属氧化物氧化铟镓锌（ IGZO ）的表面，以降低源、漏极的接触电阻，但是 Ar 等离子体只是部分改善了源、漏区与金属接触的表面电阻，源、漏区电阻仍然很大，而且等离子体等处理需要一道额外工艺处理，增加了成本，而氢则能扩散到沟道，使源、漏区延伸到沟道，导致栅极和源、漏极的重叠区域增大，寄生电容变大，进而减低金属氧化物 TFT 器件的性能。
在其他现有的自对准工艺中， 如中国专利申请 CN201080017247 ， 需要在半导体层之上形成刻蚀阻挡层，通过两次曝光分别形成 刻蚀阻挡层和源漏极，两次背面曝光自对准，增加了光刻掩膜的使用并大幅度的增加了工艺实现的难度。同时，刻蚀阻挡层也会对半导体沟道产生不良影响，进而影响 TFT 的电学特性。
 技术问题
本发明的目的 在于提供一种 金属氧化物 TFT 器件的制造方法，旨在解决传统方法容易 产生寄生电容且工艺复杂的问题。
技术解决方案
本发明是这样实现的， 一种金属氧化物 TFT 器件的制造方法，包括下述步骤：
选取一基板，在所述基板之上制备栅极；
在所述栅极之上依次设置绝缘层、半导体层及光刻胶；
以所述栅极为掩膜，自所述基板的背部曝光，保留覆盖所述半导体层的沟道部分的光刻胶；
向所述半导体层和保留的光刻胶之上沉积电极层；
剥离去除所述保留的光刻胶及覆盖所述光刻胶的电极层，露出与所述栅极对准的沟道；
刻蚀保留的电极层和半导体层，形成隔离的源极和漏极；
向所述基板上沉积钝化层，并将所述源极和漏极引出至所述钝化层之外。
本发明的另一目的 在于提供 一种金属氧化物 TFT 器件，包括：
基板；
栅极和绝缘层，依次叠层设置于所述基板之上；
半导体层，设置于所述绝缘层之上；
源极和漏极，并排设置于所述半导体层之上，且所述源极和漏极的内侧边与所述栅极的两边对准；
钝化层，包封于所述基板设有栅极的一面；
所述源极和漏极通过导电材料引出至所述钝化层之外。
本发明的再一目的 在于提供一种 金属氧化物 TFT 像素电路的制造方法，包括下述步骤：
选取一基板，在所述基板之上制备栅极、栅极引线和存储电容电极；
在所述栅极、栅极引线和存储电容电极之上依次设置绝缘层、半导体层及光刻胶；
以所述栅极、栅极引线和存储电容电极为掩膜，自所述基板的背部曝光，保留覆盖所述半导体层对应于所述栅极、栅极引线和存储电容电极的部分的光刻胶；
向所述半导体层和保留的光刻胶之上沉积电极层；
剥离去除所述保留的光刻胶及覆盖所述光刻胶的电极层，露出与所述栅极、栅极引线和存储电容电极对准的部分；
刻蚀保留的电极层和半导体层，去除所述栅极引线和存储电容电极上方的电极层和半导体层，并在所述栅极的上方形成隔离的源极和漏极；
向所述基板上沉积钝化层，并将所述源极、漏极和栅极引线引出至所述钝化层之外。
本发明的又一目的 在于提供 一种金属氧化物 TFT 像素电路，包括：
基板；
栅极、栅极引线和存储电容电极，并排设置于所述基板之上；
绝缘层，设置于所述栅极、栅极引线和存储电容电极之上；
半导体层，设置于所述绝缘层上与所述栅极对应的区域；
源极和漏极，并排设置于所述半导体层上，且所述源极和漏极的内侧边与所述栅极的两边对准；
钝化层，包封于所述基板设有栅极的一面；
所述源极、漏极和栅极引线通过导电材料引出至所述钝化层之外。
 有益效果
本发明以底栅极为掩膜，通过一次背部曝光固定光刻胶覆盖半导体沟道的位置，并结合剥离光刻胶的方式实现源漏极与栅极的对准，工艺简单且对准精度高。源漏电极与栅极的重叠区域可精确控制在 2 μ m 以内，远高于传统掩膜对位的精度，有效的减弱了寄生电容，提高了器件的电路速度，并且使沟道尺寸的控制更加精确，有利于实现沟道尺寸的最小化，提高器件性能。
另外，由于采用剥离光刻胶的方法形成源漏极，也不需制作刻蚀阻挡层，且只需一次背部曝光，从而简化了工艺，减少了光刻掩膜的使用，提高了生产效率，并且避免了刻蚀阻挡层对半导体沟道的不良影响。
并且，源漏极无需采用透明材料，使电极材料的可选性大大提高。而且生产流程中的掩膜板对准不再是关键的对准要求，进而降低了制造难度。
 附图说明
图 1 是现有金属氧化物薄膜晶体管器件的结构示意图；
图 2 是本发明第一实施例提供的金属氧化物 TFT 器件的制造方法流程图；
图 3-1 至图 3-11 是本发明第一实施例提供的金属氧化物 TFT 器件的制造方法中各步骤对应的结构示意图；
图 4 是本发明第一实施例提供的金属氧化物 TFT 器件的结构示意图；
图 5 是本发明第二实施例提供的金属氧化物 TFT 像素电路的制造方法流程图；
图 6-1 至图 6-11 是本发明第二实施例提供的金属氧化物 TFT 像素电路的制造方法中各步骤对应的结构示意图。
 本发明的实施方式
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
以下结合具体实施例对本发明的具体实现进行详细描述：
图 2 示出了本发明第一实施例提供的金属氧化物 TFT 器件的制造方法流程图，图 3-1~3-11 示出了与该制造方法相对应的结构示意图，为了便于说明，仅示出了与本实施例相关的部分。
如图 2 ，该方法包括下述步骤：
在步骤 S101 中，选取一基板 11 ，在基板 11 之上制备栅极 12 ；如图 3-1 。
在此步骤中，基板 11 选择对光刻工艺中使用的光波透明的材料制作，然后使用第一个光刻掩膜制作栅极 12 。可选的，还可以在基板 11 之上设置一缓冲层。
在步骤 S102 中，在栅极 12 之上依次设置绝缘层 13 、半导体层 14 及光刻胶 15 ；如图 3-2 、 3-3 、 3-4 。
在此步骤中，首先在基板 11 及栅极 12 之上沉积绝缘层 13 ，如图 3-2 。然后在绝缘层 13 之上沉积半导体层 14 ，如 IGZO 等金属氧化物半导体，半导体层 14 与栅极 12 对位的部分即为沟道 141 ，用于为源漏极之间的载流子传输提供通道，如图 3-3 。之后，在半导体层 14 之上涂覆光刻胶 15 ，待后续光刻使用，如图 3-4 。
在步骤 S103 中，以栅极 12 为掩膜，自基板 11 的背部曝光，保留覆盖半导体层 14 的沟道部分的光刻胶 15 ；如图 3-4 、 3-5 。
在本实施例中，作为栅极 12 的金属材料是非透明的，而其他结构均为透明材质，因此栅极 12 可以作为掩膜，从基板 11 的背部曝光、显影，光刻胶 15 与栅极 12 相对位的部分未被曝光，其他被曝光的部分被剥离，这样仅保留覆盖了半导体层 14 的沟道部分的光刻胶 15 。
在步骤 S104 中，向半导体层 14 和保留的光刻胶 15 之上沉积电极层 16 ；如图 3-6a 。
在本实施例中，电极层 16 可以为非透明的金属电极层。
进一步的，还可以在沉积电极层 16 之前先沉积一层电极接触层 17 ，然后 再沉积电极层 16 ，电极接触层 17 用于降低接触电阻，提高载流子的注入效率，如图 3-6b 。
在步骤 S105 中，剥离去除保留的光刻胶 15 及覆盖光刻胶 15 的电极层 16 ，露出与栅极 12 对准的沟道 141 ；如图 3-7 。
在步骤 S106 中，刻蚀保留的电极层 16 和半导体层 14 ，形成隔离的源极 161 和漏极 162 ；如图 3-8 。
此步骤可采用第二个光刻掩膜 20 一次刻蚀成型，工艺简单，且掩膜板无需精确对准。
在步骤 S107 中，向基板 11 上沉积钝化层 18 ，并将源极 161 和漏极 162 引出至钝化层 18 之外。如图 3-9 、 3-10 、 3-11 。
作为本实施例的一种实现方式，可以使用第三个光刻掩膜刻蚀钝化层 18 ，形成通向源极 161 和漏极 162 的过孔 181 ，然后向钝化层 18 沉积导电材料 19 ，优选为透明导电材料，如透明金属，导电材料 19 覆盖钝化层 18 并注入过孔 181 中，与源极 161 和漏极 162 接触。然后，采用第四个光刻掩膜刻蚀导电材料 19 ，形成导电引线将源极 161 和漏极 162 引出。
经过上述步骤后，金属氧化物 TFT 器件得以制成，可以理解，以上仅对金属氧化物 TFT 器件的主体结构的制造工艺进行了说明，当然，该器件还包括其他常规的功能结构，其可采用常规的方法制作，本发明不再赘述。
本发明实施例以底栅极为掩膜，通过一次背部曝光固定光刻胶覆盖半导体沟道的位置，并结合剥离光刻胶的方式实现源漏极与栅极 / 沟道的自对准，工艺简单且对准精度高。源漏电极与栅极的重叠区域可精确控制在 2 μ m 以内，远高于传统掩膜对位的精度，有效的减弱了寄生电容，提高了器件的电路速度，并且使沟道尺寸的控制更加精确，有利于实现沟道尺寸的最小化，提高器件性能。
另外，由于采用剥离光刻胶的方法形成源漏极，也不需制作刻蚀阻挡层，且只需一次背部曝光，从而简化了工艺，减少了光刻掩膜的使用，提高了生产效率，并且避免了刻蚀阻挡层对半导体沟道的不良影响。
并且，源漏极无需采用透明材料，使电极材料的可选性大大提高。而且生产流程中的掩膜板对准不再是关键的对准要求，进而降低了制造难度。
基于上述制造方法，本发明实施例进一步提供一种金属氧化物 TFT 器件，其可通过上述制造工艺制成。
参考附图 4 ，该器件是一种底栅极、顶接触结构的 TFT 器件，主要包括一基板 11 ，在基板 11 之上依次叠层设置栅极 12 、绝缘层 13 和半导体层 14 ，在半导体层 14 的表面并排设置有源极 161 和漏极 162 ，半导体层 14 在源极 161 和漏极 162 之间形成了可供载流子传输的沟道 141 ，沟道 141 的两边与源极 161 和漏极 162 的内侧边对准。基板 11 上设有钝化层 18 ，将基板 11 之上的所有结构密封在内。其中，源极 161 和漏极 162 通过导电材料 19 引出至钝化层 18 之外，与外部电路实现电性连接。
进一步的，在半导体层 14 和源极 161 与漏极 162 之间可以设有电极接触层 17 ，用于降低接触电阻，提高载流子的注入效率，进而改善 TFT 器件的电学特性。
进一步的，钝化层 18 可以开设有通向源极 161 和漏极 162 的过孔 181 ，过孔 181 中填充有透明的导电材料 19 ，将源极 161 和漏极 162 引出至钝化层 18 之外。
进一步的，通过上述的背部曝光及剥离光刻胶的方法，该器件的源极 161 和漏极 162 与栅极 12 的重叠区域的宽度可缩小到 2 μ m 以内，有效的减小了寄生电容，提高了器件性能。
可以理解，该金属氧化物 TFT 器件还可包括其他功能结构，本实施例不再赘述，并且，凡通过上述方法制成的金属氧化物 TFT 器件均在本发明的保护范围内。
实施例二：
图 5 示出了本发明第二实施例提供的 金属氧化物 TFT 像素电路的制造方法流程图，图 6-1~6-11 示出了与该制造方法相对应的结构示意图，为了便于说明，仅示出了与本实施例相关的部分。
如图 5 ，该方法包括下述步骤：
在步骤 S201 中，选取一基板 21 ，在基板 21 之上制备栅极 221 、栅极引线 222 和存储电容电极 223 ；如图 6-1 。
在此步骤中，还可以先在基板 21 之上设置一缓冲层。
在步骤 S202 中，在栅极 221 、栅极引线 222 和存储电容电极 223 之上依次设置绝缘层 23 、半导体层 24 及光刻胶 25 ；如图 6-2 、 6-3 、 6-4 。
在此步骤中，首先在基板 21 及栅极 221 之上沉积绝缘层 23 ，如图 6-2 。然后在绝缘层 23 之上沉积半导体层 24 ，如 IGZO 等金属氧化物半导体，半导体层 24 与栅极 221 对位的部分即为沟道 241 ，用于为源漏极之间的载流子传输提供通道，如图 6-3 。之后，在半导体层 24 之上涂覆光刻胶 25 ，待后续光刻使用，如图 6-4 。
在步骤 S203 中，以栅极 221 、栅极引线 222 和存储电容电极 223 为掩膜，自基板 21 的背部曝光，保留覆盖半导体层 24 对应于栅极 221 、栅极引线 222 和存储电容电极 223 的部分的光刻胶 25 ；如图 6-4 、 6-5 。
在本实施例中，作为栅极 221 的金属材料是非透明的，而其他结构均为透明材质，因此栅极 221 可以作为掩膜，从基板 21 的背部曝光、显影，光刻胶 25 与栅极 221 相对位的部分未被曝光，其他被曝光的部分被剥离，这样仅保留覆盖了半导体层 24 的沟道 241 的光刻胶 25 。
在步骤 S204 中 ，向半导体层 24 和保留的光刻胶 25 之上沉积电极层 26 ； 如图 6-6a 。
在本实施例中，电极层 26 可以为非透明的金属电极层。
进一步的，还可以在沉积电极层 26 之前先沉积一层电极接触层 27 ，然后 再沉积电极层 26 ，电极接触层 27 用于降低接触电阻，提高载流子的注入效率，如图 6-6b 。
在步骤 S205 中，剥离去除保留的光刻胶 25 及覆盖光刻胶 25 的电极层 26 ，露出与栅极 221 、栅极引线 222 和存储电容电极 223 对准的部分；如图 6-7 。
在步骤 S206 中，刻蚀保留的电极层 26 和半导体层 24 ，去除栅极引线 222 和存储电容电极 223 上方的电极层 26 和半导体层 24 ，在栅极 221 的上方形成隔离的源极 261 和漏极 262 。如图 6-8 。
此步骤可采用第二个光刻掩膜 30 一次刻蚀成型，工艺简单，且掩膜板无需精确对准。
在步骤 S207 中，向基板 21 上沉积钝化层 28 ，并将源极 261 、漏极 262 和栅极引线 222 引出至钝化层 28 之外 。如图 6-9 、 6-10 、 6-11 。
作为本实施例的一种实现方式，可以使用第三个光刻掩膜刻蚀钝化层 28 ，形成通向源极 261 、漏极 262 和栅极引线 222 的过孔 281 ，然后向钝化层 28 沉积导电材料 29 ，优选为透明导电材料，导电材料 29 覆盖钝化层 28 并注入过孔 281 中，与源极 261 、漏极 262 和栅极引线 222 接触。然后，采用第四个光刻掩膜刻蚀导电材料 29 ，形成导电引线将源极 261 、漏极 262 和栅极引线 222 引出。
可以理解，以上仅对 金属氧化物 TFT 像素电路的主体结构的制造工艺进行了说明，当然，该器件还包括其他常规的功能结构，其可采用常规的方法制作，本发明不再赘述。
本发明实施例以底栅极 、栅极引线和存储电容电极为掩膜，通过背部曝光及剥离光刻胶的方式自动对准源漏极和半导体沟道，制成了自对准的底栅极、顶接触结构的金属氧化物 TFT 像素电路。该方法具有同上述实施例相同的效果，本实施例不再赘述。
本发明实施例进一步提供一 种金属氧化物 TFT 像素电路，该器件可以通过上述方法制成。
参考图 6-11 ，该底栅极、顶接触结构的 TFT 像素电路主要包括一基板 21 ，在基板 21 之上并排设有栅极 221 、栅极引线 222 和存储电容电极 223 ，在栅极 221 和存储电容电极 223 之上设置绝缘层 23 ，在绝缘层 23 的表面与栅极 221 对应的区域设置有半导体层 24 ，在半导体层 24 上并排设有源极 261 和漏极 262 ，半导体层 24 位于源极 261 和漏极 262 之间部分为供载流子传输的沟道 241 ，栅极 221 的两边与源极 261 和漏极 262 的内侧边对准。另外，在基板 21 上设有钝化层 28 ，将基板 21 之上的所有结构密封在内。其中，源极 261 、漏极 262 和栅极引线 222 通过导电材料 29 引出至钝化层 28 之外，与外部电路实现电性连接。
进一步的，在半导体层 24 和源极 261 与漏极 262 之间可以设有电极接触层 27 ，用于降低接触电阻，提高载流子的注入效率，进而改善 TFT 器件的电学特性。
进一步的，钝化层 28 可以开设有通向源极 261 、漏极 262 和栅极引线 222 的过孔 281 ，过孔 281 中填充有透明的导电材料 29 ，将源极 261 、漏极 262 和栅极引线 222 引出至钝化层 28 之外。
进一步的，通过上述的背部曝光及剥离光刻胶的方法，该器件的源极 261 和漏极 262 与栅极 221 的重叠区域的宽度可缩小到 2 μ m 以内，有效的减小了寄生电容，提高了器件性能。
可以理解，该 金属氧化物 TFT 像素电路还可包括其他功能结构，本实施例不再赘述，并且，凡通过上述方法制成的金属氧化物 TFT 像素电路均在本发明的保护范围内。
以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。

Claims (18)

  1. 一种金属氧化物 TFT 器件的制造方法，其特征在于，包括下述步骤：
    选取一基板，在所述基板之上制备栅极；
    在所述栅极之上依次设置绝缘层、半导体层及光刻胶；
    以所述栅极为掩膜，自所述基板的背部曝光，保留覆盖所述半导体层的沟道部分的光刻胶；
    向所述半导体层和保留的光刻胶之上沉积电极层；
    剥离去除所述保留的光刻胶及覆盖所述光刻胶的电极层，露出与所述栅极对准的沟道；
    刻蚀保留的电极层和半导体层，形成隔离的源极和漏极；
    向所述基板上沉积钝化层，并将所述源极和漏极引出至所述钝化层之外。
  2. 如权利要求 1 所述的制造方法，其特征在于，在向所述半导体层和保留的光刻胶之上沉积电极层的步骤具体为：
    先向所述半导体层和保留的光刻胶上沉积电极接触层；
    再向所述电极接触层之上沉积电极层。
  3. 如权利要求 1 或 2 所述的制造方法，其特征在于，将所述源极和漏极引出至所述钝化层之外的步骤具体为：
    刻蚀所述钝化层，形成通向所述源极和漏极的过孔；
    向所述过孔中沉积导电材料，形成导电引线，将所述源极和漏极引出。
  4. 如权利要求 3 所述的制造方法，其特征在于，所述导电材料为透明导电材料。
  5. 一种金属氧化物 TFT 像素电路的制造方法，其特征在于，包括下述步骤：
    选取一基板，在所述基板之上制备栅极、栅极引线和存储电容电极；
    在所述栅极、栅极引线和存储电容电极之上依次设置绝缘层、半导体层及光刻胶；
    以所述栅极、栅极引线和存储电容电极为掩膜，自所述基板的背部曝光，保留覆盖所述半导体层对应于所述栅极、栅极引线和存储电容电极部分的光刻胶；
    向所述半导体层和保留的光刻胶之上沉积电极层；
    剥离去除所述保留的光刻胶及覆盖所述光刻胶的电极层，露出与所述栅极、栅极引线和存储电容电极对准的部分；
    刻蚀保留的电极层和半导体层，去除所述栅极引线和存储电容电极上方的电极层和半导体层，并在所述栅极的上方形成隔离的源极和漏极；
    向所述基板上沉积钝化层，并将所述源极、漏极和栅极引线引出至所述钝化层之外。
  6. 如权利要求 5 所述的制造方法，其特征在于，在向所述半导体层和保留的光刻胶之上沉积电极层的步骤具体为：
    先向所述半导体层和保留的光刻胶上沉积电极接触层；
    再向所述电极接触层之上沉积电极层。
  7. 如权利要求 5 或 6 所述的制造方法，其特征在于，将所述源极、漏极和栅极引线引出至所述钝化层之外的步骤具体为：
    刻蚀所述钝化层，形成通向所述源极、漏极和栅极引线的过孔；
    向所述过孔中沉积导电材料，形成导电引线，将所述源极、漏极和栅极引线引出。
  8. 如权利要求 7 所述的制造方法，其特征在于，所述导电材料为透明导电材料。
  9. 一种金属氧化物 TFT 器件，其特征在于，包括：
    基板；
    栅极和绝缘层，依次叠层设置于所述基板之上；
    半导体层，设置于所述绝缘层之上；
    源极和漏极，并排设置于所述半导体层之上，且所述源极和漏极的内侧边与所述栅极的两边对准；
    钝化层，包封于所述基板设有栅极的一面；
    所述源极和漏极通过导电材料引出至所述钝化层之外。
  10. 如权利要求 9 所述的金属氧化物 TFT 器件，其特征在于，所述源极和漏极与所述栅极的重叠区域的宽度均小于 2 μ m 。
  11. 如权利要求 9 所述的金属氧化物 TFT 器件，其特征在于，在所述半导体层和所述源极与漏极之间还设有与源极和漏极对齐的电极接触层。
  12. 如权利要求 9 、 10 或 11 所述的金属氧化物 TFT 器件，其特征在于，所述钝化层具有通向所述源极和漏极的过孔，所述过孔中填充有将所述源极和漏极引出的导电材料。
  13. 如权利要求 12 所述的金属氧化物 TFT 器件，其特征在于，所述导电材料为透明导电材料。
  14. 一种金属氧化物 TFT 像素电路，其特征在于，包括：
    基板；
    栅极、栅极引线和存储电容电极，并排设置于所述基板之上；
    绝缘层，设置于所述栅极、栅极引线和存储电容电极之上；
    半导体层，设置于所述绝缘层上与所述栅极对应的区域；
    源极和漏极，并排设置于所述半导体层上，且所述源极和漏极的内侧边与所述栅极的两边对准；
    钝化层，包封于所述基板设有栅极的一面；
    所述源极、漏极和栅极引线通过导电材料引出至所述钝化层之外。
  15. 如权利要求 14 所述的金属氧化物 TFT 像素电路，其特征在于，所述源极和漏极与所述栅极的重叠区域的宽度均小于 2 μ m 。
  16. 如权利要求 14 所述的金属氧化物 TFT 像素电路，其特征在于，在所述半导体层和所述源极与漏极之间还设有与源极和漏极对齐的电极接触层。
  17. 如权利要求 14 、 15 或 16 所述的金属氧化物 TFT 像素电路，其特征在于，所述钝化层具有通向所述源极、漏极和栅极引线的过孔，所述过孔中填充有将所述源极、漏极和栅极引线引出的导电材料。
  18. 如权利要求 17 所述的金属氧化物 TFT 像素电路，其特征在于，所述导电材料为透明导电材料。
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CN102768992A (zh) * 2012-08-10 2012-11-07 广州新视界光电科技有限公司 一种薄膜晶体管驱动背板的制作方法

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CN105632920A (zh) * 2014-10-27 2016-06-01 业鑫科技顾问股份有限公司 薄膜晶体管基板的制作方法
CN105632920B (zh) * 2014-10-27 2019-05-21 鸿富锦精密工业（深圳）有限公司 薄膜晶体管基板的制作方法
CN107402485A (zh) * 2017-08-31 2017-11-28 合肥京东方显示技术有限公司 阵列基板及其制作方法、液晶显示设备及其制作方法
CN113053741A (zh) * 2021-03-08 2021-06-29 北海惠科光电技术有限公司 金属电极的制备方法、金属电极及显示面板
CN113327892A (zh) * 2021-05-31 2021-08-31 惠科股份有限公司 阵列基板的制备方法、阵列基板及液晶显示面板
CN113327893A (zh) * 2021-05-31 2021-08-31 惠科股份有限公司 阵列基板的制备方法、阵列基板及液晶显示面板

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