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WO2018201542A1 - 一种oled显示面板及其制备方法 - Google Patents

一种oled显示面板及其制备方法 Download PDF

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Publication number
WO2018201542A1
WO2018201542A1 PCT/CN2017/086234 CN2017086234W WO2018201542A1 WO 2018201542 A1 WO2018201542 A1 WO 2018201542A1 CN 2017086234 W CN2017086234 W CN 2017086234W WO 2018201542 A1 WO2018201542 A1 WO 2018201542A1
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WIPO (PCT)
Prior art keywords
layer
semiconductor oxide
contact
pattern layer
silicon nitride
Prior art date
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Ceased
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PCT/CN2017/086234
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English (en)
French (fr)
Inventor
张晓星
徐源竣
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to JP2019560294A priority Critical patent/JP2020520557A/ja
Priority to EP17908502.2A priority patent/EP3621105B1/en
Priority to US15/541,746 priority patent/US20180323246A1/en
Priority to KR1020197035592A priority patent/KR20200003143A/ko
Publication of WO2018201542A1 publication Critical patent/WO2018201542A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/411—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by materials, geometry or structure of the substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an OLED display panel and a method of fabricating the same.
  • TFTs due to the top gate structure have a small parasitic capacitance, TFT
  • the size can be smaller, which is a better choice for OLED driving, but the semiconductor oxide TFT of the top gate structure needs to conduct conductor treatment on the semiconductor oxide in contact with the source and drain regions during the fabrication process, thereby reducing the source and The contact impedance of the drain realizes the switching function of the TFT.
  • the semiconductor oxide in contact with the source and the drain is generally electrically conductive by means of hydrogen plasma or argon plasma treatment, but since the OLED display panel has other annealing processes after forming the TFT, these annealing The process re-semiconducts the conductive oxide to increase the contact resistance with the source and drain, lowers the TFT characteristics, and even causes the TFT to lose its switching function.
  • the invention mainly provides an OLED display panel and a preparation method thereof, and aims to solve the problem that a portion of a semiconductor oxide having a conductor characteristic is re-semiconducted during the preparation process of the OLED display panel, and the contact resistance with the source and the drain is increased. problem.
  • a technical solution adopted by the present invention is to provide a method for fabricating an OLED display panel, wherein the method includes: depositing a buffer layer on a substrate and forming a semiconductor stacked in sequence on the buffer layer An oxide pattern layer, a gate insulating layer, and a gate pattern layer; and a dielectric layer covering the semiconductor oxide pattern layer, the gate insulating layer, and the gate pattern layer is formed on the buffer layer,
  • the dielectric layer includes a silicon nitride layer in contact with the semiconductor oxide pattern layer; the dielectric layer is annealed to have a portion of the semiconductor oxide pattern layer during annealing a conductor characteristic; forming a source and a drain in contact with the partial semiconductor oxide pattern layer having a conductor characteristic; wherein the buffer layer includes a silicon oxide layer in contact with the semiconductor oxide pattern layer; wherein
  • the gate insulating layer includes a third portion and a fourth portion adjacent to the third portion, the third portion is disposed opposite to the gate pattern layer, and the fourth portion
  • another technical solution adopted by the present invention is to provide a method for fabricating an OLED display panel, wherein the method includes: depositing a buffer layer on a substrate and forming a stacked layer on the buffer layer; a semiconductor oxide pattern layer, a gate insulating layer, and a gate pattern layer; and a dielectric layer covering the semiconductor oxide pattern layer, the gate insulating layer, and the gate pattern layer is formed on the buffer layer,
  • the dielectric layer includes a silicon nitride layer in contact with the semiconductor oxide pattern layer; the dielectric layer is annealed to form a portion of the semiconductor oxide pattern layer during annealing Having a conductor characteristic; forming a source and a drain in contact with the partial semiconductor oxide pattern layer having a conductor characteristic.
  • an OLED display panel wherein the display panel includes: a buffer layer deposited on the substrate and a semiconductor oxide sequentially stacked on the buffer layer a pattern layer, a gate insulating layer and a gate pattern layer, wherein a portion of the semiconductor oxide pattern layer has a conductor property; and a layer covering the semiconductor oxide pattern layer, the gate insulating layer and the gate pattern layer An electrical layer comprising a silicon nitride layer in contact with the semiconductor oxide pattern layer; a source and a drain in contact with the portion of the semiconductor oxide pattern layer having a conductor characteristic.
  • the present invention deposits a buffer layer on a substrate and forms a semiconductor oxide pattern layer, a gate insulating layer and a gate pattern layer which are sequentially stacked on the buffer layer; Forming a dielectric layer covering the semiconductor oxide pattern layer, the gate insulating layer and the gate pattern layer on the buffer layer, the dielectric layer comprising a silicon nitride layer in contact with the semiconductor oxide pattern layer; and annealing the dielectric layer, In the annealing process, the silicon nitride layer causes a portion of the semiconductor oxide pattern layer to have a conductor characteristic; a method of forming a source and a drain in contact with a portion of the semiconductor oxide pattern layer having a conductor characteristic, utilizing hydrogen in the silicon nitride More features, such that a portion of the semiconductor oxide pattern layer having a conductor characteristic in contact with the silicon nitride layer can be continuously doped with hydrogen atoms to maintain the conductor characteristics, thereby causing the portion
  • FIG. 1 is a schematic flow chart of an embodiment of a method for fabricating an OLED display panel provided by the present invention
  • FIG. 2 is a schematic structural view of an embodiment of an OLED display panel prepared in each step of FIG. 1;
  • step S11 in FIG. 1 is a schematic diagram of a specific process of step S11 in FIG. 1;
  • FIG. 4 is a schematic diagram of a specific process of step S14 in FIG. 1.
  • an embodiment of a method for fabricating an OLED display panel provided by the present invention includes:
  • S11 depositing a buffer layer 102 on the substrate 101 and forming a semiconductor oxide pattern layer 103, a gate insulating layer 104 and a gate pattern layer 105 which are sequentially stacked on the buffer layer 102;
  • the step S11 may specifically include:
  • the buffer layer 102 may be deposited on the substrate 101 by physical vapor deposition or plasma vapor deposition, wherein a silicon oxide may be deposited on the substrate 101.
  • a silicon nitride layer may be deposited on the substrate 101, and then a silicon oxide layer having a thickness of not less than 3000 angstroms may be deposited on the silicon nitride layer to serve as the buffer layer 102.
  • the substrate 101 may be a glass substrate including, but not limited to, a silicon wafer substrate.
  • a semiconductor oxide pattern layer 103 is formed on the silicon oxide layer in the buffer layer 102, and a semiconductor oxide layer having a thick bottom of 400 angstroms to 600 angstroms may be deposited on the silicon oxide layer in the buffer layer 102, and then passed through Photolithography process of photoresist coating, exposure, development and lift-off to form a patterned semiconductor oxide layer. Since silicon oxide does not contain hydrogen, the patterned semiconductor oxide layer is not electrically conductive in this step S112. .
  • the semiconductor oxide pattern layer 103 includes a first portion 1031 and a second portion 1032 adjacent to the first portion 1031.
  • the second portion 1032 is located on opposite sides of the first portion 1031.
  • the semiconductor oxide is IGZO, that is, indium gallium zinc oxide.
  • the gate insulating layer 104 is disposed opposite to the first portion 1031 of the semiconductor oxide pattern layer 103.
  • the gate insulating layer 104 includes a third portion 1041 and a fourth portion 1042 adjacent to the third portion 1041.
  • the fourth portion 1042 is located on opposite sides of the third portion 1041, and the third portion 1041 is disposed opposite to the gate pattern layer 105.
  • a silicon oxide layer having a thickness of 1000 ⁇ to 2000 ⁇ and covering the semiconductor oxide pattern layer 103 may be deposited on the buffer layer 102 by physical vapor deposition or plasma vapor deposition, and then in the silicon oxide layer.
  • the metal layer is a layer including, but not limited to, a molybdenum, aluminum or copper metal.
  • the fourth portion 1042 has a length of 0.3 ⁇ m to 1 ⁇ m.
  • the gate insulating layer 104 and the gate pattern layer 105 may be separately formed in two steps, and a silicon oxide layer may be deposited on the buffer layer 102 for photoresist coating, exposure, development, etching, and After the stripping lithography process, a gate insulating layer 104 is formed opposite to the semiconductor oxide pattern layer 103, and then a metal layer is deposited on the gate insulating layer 104, followed by photoresist coating, exposure, development, etching, and stripping. A photolithography process is performed to form the gate pattern layer 105 such that the gate pattern layer 105 is disposed opposite the third portion 1041 of the gate insulating layer 104.
  • the dielectric layer 106 includes a silicon nitride layer in contact with the semiconductor oxide pattern layer 103.
  • a silicon nitride layer having a thickness of 4000 angstroms to 5000 angstroms may be deposited on the buffer layer 102 by using a physical vapor deposition method or a plasma vapor deposition method to form the dielectric layer 106, or a buffer layer 102 may be deposited on the buffer layer 102.
  • a silicon nitride layer having a layer thickness of 3000 angstroms, and then depositing a silicon oxide layer having a thickness of 3000 angstroms on the silicon nitride layer to collectively form the dielectric layer 106, and the dielectric layer 106 is known by the above steps.
  • the thickness of the silicon nitride layer is greater than the thicknesses of the semiconductor oxide pattern layer 103 and the gate insulating layer 104 to be in contact with the second portion 1032 of the semiconductor oxide pattern layer 103 and the fourth portion 1042 of the gate insulating layer 104.
  • the silicon nitride layer contains hydrogen atoms
  • the hydrogen atoms diffuse to the lower semiconductor oxide pattern layer 103 shown in FIG. 2 under high temperature, during the diffusion process.
  • the second portion 1032 of the semiconductor oxide pattern layer 103 due to contact with the silicon nitride layer, diffuses hydrogen atoms to the second portion 1032 such that the second portion 1032 is doped with hydrogen atoms to have conductor characteristics.
  • the gate insulating layer 104 is a silicon oxide layer
  • the first portion 1031 disposed opposite to the gate insulating layer 104 is protected by the gate insulating layer 104, preventing hydrogen atoms from diffusing to the first portion 1031, so that after annealing, A portion of the 1031 still retains the semiconductor characteristics
  • the size of the gate insulating layer 104 in the cross section is larger than that of the gate pattern layer 105, further preventing the hydrogen atoms in the silicon nitride layer from diffusing downward to the first portion 1031.
  • the first portion 1031 is still left to retain semiconductor characteristics.
  • step S14 may specifically include:
  • the patterned contact hole can be formed by photoresist coating and exposure, and then dry etching is performed to remove the contact hole 1061.
  • the contact hole 1061 is formed on the dielectric layer 106 and the second portion 1032 on both sides of the semiconductor oxide pattern layer 103.
  • S142 Forming a source 107 and a drain 108 in contact with a portion of the semiconductor oxide pattern layer through the contact hole 1061 on the dielectric layer 106.
  • a metal layer may be deposited on the dielectric layer 106 and the contact hole 1061 by physical vapor deposition to form a metal layer, and then a photoresist layer is deposited on the deposited metal layer, followed by exposure, development, etching, and stripping. The process is performed to obtain a patterned source 107 and drain 108, since the contact hole 1061 is in communication with the second portion 1032 of the semiconductor oxide pattern layer 103 to pattern the source 107 and drain 108 and the semiconductor oxide pattern. The second portion 1032 of layer 103 is in contact.
  • this embodiment further includes:
  • a silicon nitride layer or a silicon oxide layer may be deposited on the dielectric layer 106 using physical vapor deposition or plasma vapor deposition to form a planar layer 109, and a silicon nitride layer or oxide is deposited on the planar layer 109.
  • the silicon layer is formed by photoresist coating, exposure, development, and etching to form a pixel light-emitting region, and the silicon nitride layer or the silicon oxide layer having the pixel light-emitting region is the pixel defining layer 110.
  • an anode layer 1111, an electron transport layer 1112, a light-emitting layer 1113, a hole transport layer 1114, and a cathode layer 1115 are sequentially formed at positions opposite to the pixel light-emitting regions on the pixel defining layer 110.
  • an embodiment of an OLED display panel includes a buffer layer 102 deposited on a substrate 101 and a semiconductor oxide pattern layer 103, a gate insulating layer 104, and a gate pattern layer sequentially stacked on the buffer layer 102. 105.
  • a dielectric layer 106 covering the semiconductor oxide pattern layer 103, the gate insulating layer 104, and the gate pattern layer 105, and a source 107 and a drain 108 in contact with the semiconductor oxide pattern layer 103.
  • the semiconductor oxide pattern layer 103 includes a first portion 1031 and a second portion 1032 adjacent to the first portion 1031.
  • the first portion 1031 is disposed opposite to the gate insulating layer 104, and the second portion 1032 has a conductor characteristic.
  • the dielectric layer 106 includes a silicon nitride layer in contact with the semiconductor oxide pattern layer 103. Since silicon nitride contains hydrogen atoms, hydrogen atoms in the silicon nitride layer are prepared toward the semiconductor oxide pattern layer 103 at the time of preparation. Diffusion, such that the second portion 1032 in contact with the silicon nitride layer is doped with hydrogen atoms to have conductor characteristics, and the first portion 1031 is disposed opposite to the gate insulating layer 104 and protected by the gate insulating layer 104 to prevent the first portion 1031 from being doped Hydrogen atoms retain semiconductor properties.
  • the display panel in this embodiment further includes a flat layer 109, a pixel defining layer 110, and an OLED device layer 111 which are sequentially stacked on the dielectric layer 106.
  • the present invention forms a buffer layer on a substrate and forms a semiconductor oxide pattern layer, a gate insulating layer and a gate pattern layer which are sequentially stacked on the buffer layer; and forms a cover semiconductor oxide pattern layer on the buffer layer.
  • the dielectric layer includes a silicon nitride layer in contact with the semiconductor oxide pattern layer; and the dielectric layer is annealed to form a silicon nitride layer during the annealing process
  • Making a portion of the semiconductor oxide pattern layer have a conductor characteristic; a method of forming a source and a drain in contact with a portion of the semiconductor oxide pattern layer having a conductor characteristic, utilizing a feature of more hydrogen in the silicon nitride, and the silicon nitride
  • the portion of the semiconductor oxide pattern layer having the conductor property of the layer contact can be continuously doped with hydrogen atoms to maintain the conductor characteristics, so that the contact resistance between the portion of the semiconductor oxide pattern layer and the source and the drain can be continuously maintained. Low state to implement TFT function.

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Abstract

本发明提供了一种OLED显示面板及其制备方法，通过这种方法，本发明利用氮化硅中含氢较多的特点，使得与氮化硅层接触的具有导体特性的部分半导体氧化物图案层能够持续的掺杂有氢原子而保持导体特性，进而使得该部分半导体氧化物图案层与源极和漏极的接触阻抗能够持续的保持在较低的状态，以实现TFT功能。

Description

一种OLED显示面板及其制备方法
【技术领域】
本发明涉及显示技术领域，特别是涉及一种OLED显示面板及其制备方法。
【背景技术】
目前，由于顶栅结构的半导体氧化物TFT具有较小的寄生电容，TFT 尺寸可以较小，成为OLED驱动的较好选择，但是顶栅结构的半导体氧化物TFT在制作过程中需要对与源极和漏极接触区域的半导体氧化物做导体化处理，从而降低源极和漏极的接触阻抗，实现TFT的开关功能。
现有技术中，一般采用氢气等离子或氩气等离子处理的方式使得与源极和漏极接触的半导体氧化物导体化，但是由于OLED显示面板在形成TFT之后还会有其他的退火工艺，这些退火工艺会使得导体化的氧化物重新半导体化而使得与源极和漏极的接触阻抗变大，降低了TFT特性，甚至使TFT失去开关功能。
【发明内容】
本发明主要是提供一种OLED显示面板及其制备方法，旨在解决OLED显示面板制备过程中半导体氧化物具有导体特性的部分会重新半导体化而导致与源极和漏极的接触阻抗变大的问题。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种OLED显示面板的制备方法，其中，所述方法包括：在基板上沉积缓冲层并在所述缓冲层上形成依次层叠的半导体氧化物图案层、栅极绝缘层及栅极图案层；在所述缓冲层上形成覆盖所述半导体氧化物图案层、所述栅极绝缘层及所述栅极图案层的介电层，所述介电层包括与所述半导体氧化物图案层接触的氮化硅层；对所述介电层进行退火处理，以在退火过程中，所述氮化硅层使得部分半导体氧化物图案层具有导体特性；形成与具有导体特性的所述部分半导体氧化物图案层接触的源极和漏极；其中，所述缓冲层包括与所述半导体氧化物图案层接触的氧化硅层；其中，所述栅极绝缘层包括第三部分及与所述第三部分相邻的第四部分，所述第三部分与所述栅极图案层相对设置，所述第四部分与所述氮化硅层接触。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种OLED显示面板的制备方法，其中，所述方法包括：在基板上沉积缓冲层并在所述缓冲层上形成依次层叠的半导体氧化物图案层、栅极绝缘层及栅极图案层；在所述缓冲层上形成覆盖所述半导体氧化物图案层、所述栅极绝缘层及所述栅极图案层的介电层，所述介电层包括与所述半导体氧化物图案层接触的氮化硅层；对所述介电层进行退火处理，以在退火过程中，所述氮化硅层使得部分半导体氧化物图案层具有导体特性；形成与具有导体特性的所述部分半导体氧化物图案层接触的源极和漏极。
为解决上述技术问题，本发明采用的又一个技术方案是：提供一种OLED显示面板，其中，所述显示面板包括：在基板上沉积的缓冲层及在所述缓冲层上依次层叠的半导体氧化物图案层、栅极绝缘层及栅极图案层，其中，部分半导体氧化物图案层具有导体特性；覆盖所述半导体氧化物图案层、所述栅极绝缘层及所述栅极图案层的介电层，所述介电层包括与所述半导体氧化物图案层接触的氮化硅层；与具有导体特性的所述部分半导体氧化物图案层接触的源极和漏极。
本发明的有益效果是：区别于现有技术的情况，本发明通过在基板上沉积缓冲层并在缓冲层上形成依次层叠的半导体氧化物图案层、栅极绝缘层及栅极图案层；在缓冲层上形成覆盖半导体氧化物图案层、栅极绝缘层及栅极图案层的介电层，介电层包括与半导体氧化物图案层接触的氮化硅层；对介电层进行退火处理，以在退火过程中，氮化硅层使得部分半导体氧化物图案层具有导体特性；形成与具有导体特性的部分半导体氧化物图案层接触的源极和漏极的方法，利用氮化硅中含氢较多的特点，使得与氮化硅层接触的具有导体特性的部分半导体氧化物图案层能够持续的掺杂有氢原子而保持导体特性，进而使得该部分半导体氧化物图案层与源极和漏极的接触阻抗能够持续的保持在较低的状态，以实现TFT功能。
【附图说明】
图1是本发明提供的OLED显示面板的制备方法实施例的流程示意图；
图2是图1中各步骤制备而成的OLED显示面板实施例的结构示意图；
图3是图1中步骤S11的具体流程示意图；
图4是图1中步骤S14的具体流程示意图。
【具体实施方式】
为使本领域的技术人员更好地理解本发明的技术方案，下面结合附图和具体实施方式对本发明所提供的一种OLED显示面板及其制备方法做进一步详细描述。
共同参阅图1及图2，本发明提供的OLED显示面板的制备方法实施例包括：
S11：在基板101上沉积缓冲层102并在缓冲层102上形成依次层叠的半导体氧化物图案层103、栅极绝缘层104及栅极图案层105；
参阅图3，该步骤S11可具体包括：
S111：在基板101上沉积缓冲层102；
具体的，在沉积缓冲层102之前，将基板101清洗干净，然后可使用物理气相沉积法或等离子体气相沉积法在基板101上沉积缓冲层102，其中，可以在基板101上沉积一层氧化硅层作为缓冲层102，也可以先在基板101上沉积一层氮化硅层，然后在该氮化硅层上沉积一层厚度不小于3000埃的氧化硅层以共同作为缓冲层102。
其中，基板101可以是包括但不限于的玻璃基板、硅片基板。
S112：在缓冲层102上形成半导体氧化物图案层103；
具体的，在缓冲层102中的氧化硅层上形成半导体氧化物图案层103，可在缓冲层102中的氧化硅层上沉积一层厚底为400埃至600埃的半导体氧化物层，然后经过光阻涂布、曝光、显影及剥离的光刻工艺，形成图案化的半导体氧化物层，由于氧化硅中不含氢，在该步骤S112中，图案化的半导体氧化物层不会被导体化。
其中，半导体氧化物图案层103包括第一部分1031及与第一部分1031相邻的第二部分1032，在本实施例图示中，第二部分1032位于第一部分1031相对的两侧。
可选的，该半导体氧化物为IGZO，即为铟镓锌氧化物。
S113：在半导体氧化物图案层103上形成依次层叠的栅极绝缘层104及栅极图案层105；
其中，栅极绝缘层104与半导体氧化物图案层103的第一部分1031相对设置，栅极绝缘层104包括第三部分1041及与第三部分1041相邻的第四部分1042，在本实施例图示中，第四部分1042位于第三部分1041相对的两侧，且第三部分1041与栅极图案层105相对设置。
具体的，可使用物理气相沉积法或等离子体气相沉积法在缓冲层102上沉积一层厚度为1000埃至2000埃且覆盖半导体氧化物图案层103的氧化硅层，然后在该氧化硅层再沉积一层金属层，进而在进行光阻涂布、曝光及显影之后，对金属层及氧化硅层同时蚀刻，以形成栅极图案层105及栅极绝缘层104，且在蚀刻的过程中，如图2所示，通过合适的蚀刻条件使得栅极绝缘层104相对的两侧超出栅极图案层105，两侧超出的部分即为第四部分1042，中间与栅极图案层105相对设置的即为第三部分1041。
其中，金属层是包括但不限于钼、铝或铜金属层。
可选的，第四部分1042的长度为0.3μm ~1μm。
在其他实施例中，栅极绝缘层104及栅极图案层105可在两个步骤中分别形成，可先在缓冲层102上沉积氧化硅层，进行光阻涂布、曝光、显影、蚀刻及剥离的光刻工艺之后形成与半导体氧化物图案层103相对设置的栅极绝缘层104，然后在栅极绝缘层104上沉积金属层，再进行光阻涂布、曝光、显影、蚀刻及剥离的光刻工艺以形成栅极图案层105，且使得栅极图案层105与栅极绝缘层104的第三部分1041相对设置。
S12：在缓冲层102上形成覆盖半导体氧化物图案层103、栅极绝缘层104及栅极图案层105的介电层106；
其中，介电层106包括与半导体氧化物图案层103接触的氮化硅层。
具体的，可使用物理气相沉积法或等离子体气相沉积法在缓冲层102上沉积一层厚度为4000埃至5000埃的氮化硅层以形成介电层106，或者在缓冲层102上沉积一层厚度为3000埃的氮化硅层，然后在该氮化硅层上沉积一层厚度为3000埃的氧化硅层以共同形成介电层106，且通过上述步骤可知，该介电层106中氮化硅层的厚度大于半导体氧化物图案层103及栅极绝缘层104的厚度而能够与半导体氧化物图案层103的第二部分1032、栅极绝缘层104的第四部分1042接触。
S13：对介电层106进行退火处理，以在退火过程中，氮化硅层使得部分半导体氧化物图案层具有导体特性；
具体的，由于氮化硅层中含有氢原子，在对介电层106的退火过程中，氢原子会在高温作用下向图2所示下方的半导体氧化物图案层103扩散，在扩散过程中，半导体氧化物图案层103的第二部分1032由于与氮化硅层接触，氢原子会扩散至第二部分1032使得第二部分1032掺杂有氢原子而具有导体特性。
其中，由于栅极绝缘层104为氧化硅层，与栅极绝缘层104相对设置的第一部分1031会被栅极绝缘层104保护，防止氢原子扩散至第一部分1031，而使得在退火之后，第一部分1031仍然保留半导体特性，且根据上述步骤S113可知，栅极绝缘层104在截面上的尺寸大于栅极图案层105，进一步防止了氮化硅层中的氢原子在向下扩散至第一部分1031而使得第一部分1031仍然保留半导体特性。
S14：形成与具有导体特性的部分半导体氧化物图案层接触的源极107和漏极108。
参阅图4，该步骤S14可具体包括：
S141：在介电层106上开设与部分半导体氧化物图案层连通的接触孔1061；
具体的，可通过光阻涂布、曝光的方法形成图案化的接触孔，然后进行干法刻蚀，去除后即可得到接触孔1061。
其中，在介电层106上与半导体氧化物图案层103两侧的第二部分1032均有接触孔1061。
S142：在介电层106上通过接触孔1061形成与部分半导体氧化物图案层接触的源极107和漏极108。
具体的，可使用物理气相沉积法在介电层106上及接触孔1061中沉积金属，形成金属层，然后在沉积的金属层上沉积光阻层，再进行曝光、显影、刻蚀和剥离的制程，以得到图案化的源极107及漏极108，由于接触孔1061与半导体氧化物图案层103的第二部分1032连通，以使图案化的源极107和漏极108与半导体氧化物图案层103的第二部分1032接触。
进一步的，本实施例还包括：
S15：在介电层106上形成依次层叠的平坦层109及像素定义层110；
具体的，可使用物理气相沉积法或等离子体气相沉积法在介电层106上沉积氮化硅层或氧化硅层，以形成平坦层109，并在平坦层109上沉积氮化硅层或氧化硅层并通过光阻涂布、曝光、显影及蚀刻形成像素发光区，具有像素发光区的氮化硅层或氧化硅层即为像素定义层110。
S16：在像素定义层110上形成OLED器件层111。
具体地，在像素定义层110上像素发光区相对的位置依次形成阳极层1111、电子传输层1112、发光层1113、空穴传输层1114及阴极层1115。
进一步参阅图2，本发明提供的OLED显示面板实施例包括在基板101上沉积的缓冲层102及在缓冲层102上依次层叠的半导体氧化物图案层103、栅极绝缘层104及栅极图案层105、覆盖半导体氧化物图案层103、栅极绝缘层104及栅极图案层105的介电层106以及与半导体氧化物图案层103接触的源极107和漏极108。
其中，半导体氧化物图案层103包括第一部分1031及与第一部分1031相邻的第二部分1032，第一部分1031与栅极绝缘层104相对设置，第二部分1032具有导体特性。
具体地，介电层106包括与半导体氧化物图案层103接触的氮化硅层，由于氮化硅中含有氢原子，在制备时，氮化硅层中的氢原子向半导体氧化物图案层103扩散，使得与氮化硅层接触的第二部分1032掺杂有氢原子而具有导体特性，第一部分1031与栅极绝缘层104相对设置而被栅极绝缘层104保护以防止第一部分1031掺杂氢原子，保留了半导体特性。
进一步地，本实施例中的显示面板还包括在介电层106上依次层叠的平坦层109、像素定义层110以及OLED器件层111。
本实施例中的各膜层可使用上述方法相对应的步骤分别制备而成，在此不再赘述。
区别于现有技术，本发明通过在基板上沉积缓冲层并在缓冲层上形成依次层叠的半导体氧化物图案层、栅极绝缘层及栅极图案层；在缓冲层形成覆盖半导体氧化物图案层、栅极绝缘层及栅极图案层的介电层，介电层包括与半导体氧化物图案层接触的氮化硅层；对介电层进行退火处理，以在退火过程中，氮化硅层使得部分半导体氧化物图案层具有导体特性；形成与具有导体特性的部分半导体氧化物图案层接触的源极和漏极的方法，利用氮化硅中含氢较多的特点，使得与氮化硅层接触的具有导体特性的部分半导体氧化物图案层能够持续的掺杂有氢原子而保持导体特性，进而使得该部分半导体氧化物图案层与源极和漏极的接触阻抗能够持续的保持在较低的状态，以实现TFT功能。
以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。  

Claims (15)

  1. 一种OLED显示面板的制备方法，其中，所述方法包括：
    在基板上沉积缓冲层并在所述缓冲层上形成依次层叠的半导体氧化物图案层、栅极绝缘层及栅极图案层；
    在所述缓冲层上形成覆盖所述半导体氧化物图案层、所述栅极绝缘层及所述栅极图案层的介电层，所述介电层包括与所述半导体氧化物图案层接触的氮化硅层；
    对所述介电层进行退火处理，以在退火过程中，所述氮化硅层使得部分半导体氧化物图案层具有导体特性；
    形成与具有导体特性的所述部分半导体氧化物图案层接触的源极和漏极；
    其中，所述缓冲层包括与所述半导体氧化物图案层接触的氧化硅层；
    其中，所述栅极绝缘层包括第三部分及与所述第三部分相邻的第四部分，所述第三部分与所述栅极图案层相对设置，所述第四部分与所述氮化硅层接触。
  2. 根据权利要求1所述的方法，其中，所述半导体氧化物图案层包括第一部分及与所述第一部分相邻的第二部分，所述第一部分与所述栅极绝缘层相对设置，所述第二部分与所述氮化硅层接触，所述对所述介电层进行退火处理，以在退火过程中，所述氮化硅层使得部分半导体氧化物图案层具有导体特性包括：
    对所述介电层进行退火处理，在退火过程中，所述氮化硅层使得与所述氮化硅层接触的所述第二部分具有导体特性。
  3. 根据权利要求2所述的方法，其中，所述氮化硅层中包含氢原子，所述在退火过程中，所述氮化硅层使得与所述氮化硅层接触的所述第二部分具有导体特性包括：
    在退火过程中，所述氮化硅层中的氢原子向所述半导体氧化物图案层扩散，使得与所述氮化硅层接触的所述第二部分掺杂有所述氢原子而具有导体特性。
  4. 根据权利要求3所述的方法，其中，所述栅极绝缘层为氧化硅层，与所述栅极绝缘层相对设置的所述第一部分在退火之后保留半导体特性。
  5. 根据权利要求1所述的方法，其中，形成与具有导体特性的所述部分半导体氧化物图案层接触的源极和漏极包括：
    在所述介电层中开设与所述部分半导体氧化物图案层连通的接触孔；
    在所述介电层上通过所述接触孔形成与所述部分半导体氧化物图案层接触的所述源极和所述漏极。
  6. 一种OLED显示面板的制备方法，其中，所述方法包括：
    在基板上沉积缓冲层并在所述缓冲层上形成依次层叠的半导体氧化物图案层、栅极绝缘层及栅极图案层；
    在所述缓冲层上形成覆盖所述半导体氧化物图案层、所述栅极绝缘层及所述栅极图案层的介电层，所述介电层包括与所述半导体氧化物图案层接触的氮化硅层；
    对所述介电层进行退火处理，以在退火过程中，所述氮化硅层使得部分半导体氧化物图案层具有导体特性；
    形成与具有导体特性的所述部分半导体氧化物图案层接触的源极和漏极。
  7. 根据权利要求6所述的方法，其中，所述半导体氧化物图案层包括第一部分及与所述第一部分相邻的第二部分，所述第一部分与所述栅极绝缘层相对设置，所述第二部分与所述氮化硅层接触，所述对所述介电层进行退火处理，以在退火过程中，所述氮化硅层使得部分半导体氧化物图案层具有导体特性包括：
    对所述介电层进行退火处理，在退火过程中，所述氮化硅层使得与所述氮化硅层接触的所述第二部分具有导体特性。
  8. 根据权利要求7所述的方法，其中，所述氮化硅层中包含氢原子，所述在退火过程中，所述氮化硅层使得与所述氮化硅层接触的所述第二部分具有导体特性包括：
    在退火过程中，所述氮化硅层中的氢原子向所述半导体氧化物图案层扩散，使得与所述氮化硅层接触的所述第二部分掺杂有所述氢原子而具有导体特性。
  9. 根据权利要求8所述的方法，其中，所述栅极绝缘层为氧化硅层，与所述栅极绝缘层相对设置的所述第一部分在退火之后保留半导体特性。
  10. 根据权利要求6所述的方法，其中，所述缓冲层包括与所述半导体氧化物图案层接触的氧化硅层。
  11. 根据权利要求6所述的方法，其中，所述栅极绝缘层包括第三部分及与所述第三部分相邻的第四部分，所述第三部分与所述栅极图案层相对设置，所述第四部分与所述氮化硅层接触。
  12. 根据权利要求6所述的方法，其中，形成与具有导体特性的所述部分半导体氧化物图案层接触的源极和漏极包括：
    在所述介电层中开设与所述部分半导体氧化物图案层连通的接触孔；
    在所述介电层上通过所述接触孔形成与所述部分半导体氧化物图案层接触的所述源极和所述漏极。
  13. 一种OLED显示面板，其中，所述显示面板包括：
    在基板上沉积的缓冲层及在所述缓冲层上依次层叠的半导体氧化物图案层、栅极绝缘层及栅极图案层，其中，部分半导体氧化物图案层具有导体特性；
    覆盖所述半导体氧化物图案层、所述栅极绝缘层及所述栅极图案层的介电层，所述介电层包括与所述半导体氧化物图案层接触的氮化硅层；
    与具有导体特性的所述部分半导体氧化物图案层接触的源极和漏极。
  14. 根据权利要求13所述的显示面板，其中，所述半导体氧化物图案层包括第一部分及与所述第一部分相邻的第二部分，所述第一部分与所述栅极绝缘层相对设置，所述第二部分与所述氮化硅层接触而具有导体性。
  15. 根据权利要求14所述的显示面板，其中，所述氮化硅层中含有氢原子，所述显示面板在制备过程中，所述氮化硅层中的氢原子向所述半导体氧化物图案层扩散，使得与所述氮化硅层接触的所述第二部分掺杂有所述氢原子而具有导体特性。
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