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US20050156283A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
US20050156283A1
US20050156283A1 US10/505,179 US50517904A US2005156283A1 US 20050156283 A1 US20050156283 A1 US 20050156283A1 US 50517904 A US50517904 A US 50517904A US 2005156283 A1 US2005156283 A1 US 2005156283A1
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US
United States
Prior art keywords
semiconductor
region
semiconductor substrate
semiconductor device
recess
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US10/505,179
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English (en)
Inventor
Norifumi Tokuda
Shigeru Kusunoki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Assigned to MITSUBISHI DENKI KABUSHIKI KAISHA reassignment MITSUBISHI DENKI KABUSHIKI KAISHA ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KUSUNOKI, SHIGERU, TOKUDA, NORIFUMI
Publication of US20050156283A1 publication Critical patent/US20050156283A1/en
Priority to US11/561,823 priority Critical patent/US7635892B2/en
Priority to US12/580,303 priority patent/US20100038707A1/en
Abandoned legal-status Critical Current

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    • H10P95/00—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H10D12/032—Manufacture or treatment of IGBTs of vertical IGBTs
    • H10D12/038—Manufacture or treatment of IGBTs of vertical IGBTs having a recessed gate, e.g. trench-gate IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/64—Electrodes comprising a Schottky barrier to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/60—Schottky-barrier diodes 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/141—Anode or cathode regions of thyristors; Collector or emitter regions of gated bipolar-mode devices, e.g. of IGBTs
    • H10D62/142—Anode regions of thyristors or collector regions of gated bipolar-mode devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/50—Physical imperfections
    • H10D62/53—Physical imperfections the imperfections being within the semiconductor body 

Definitions

  • the present invention relates to a semiconductor device, and particularly to a semiconductor device in which the main current flows in the thickness direction of the semiconductor substrate.
  • the breakdown voltage increases as the semiconductor substrate thickness increases to a certain thickness determined by the resistivity of the substrate; the breakdown voltage becomes substantially fixed at the certain thickness or more.
  • increasing the semiconductor substrate thickness increases the on-state resistance, which increases power dissipation and deteriorates performance.
  • the optimum substrate thickness is determined in consideration of the balance between performance and breakdown voltage.
  • First Patent Document discloses a structure for reducing the weight of a semiconductor wafer, where a plurality of recesses are formed on the back to reduce the weight without lowering the mechanical strength.
  • Second Patent Document discloses a structure for preventing unauthorized reading of the circuit pattern provided on a semiconductor chip, where a plurality of recesses are formed on the back of the semiconductor chip so that the semiconductor chip easily breaks when subjected to unauthorized reading.
  • determining the substrate thickness requires considering not only the performance and breakdown voltage but also the mechanical strength of the semiconductor substrate and the photolithography processing conditions.
  • Use of epitaxial-growth substrates is proposed in order to satisfy these conditions, but thickening epitaxial-growth layers takes time and increases cost.
  • An object of the invention is to provide a semiconductor device in which a main current flows in the thickness direction of the semiconductor substrate and which offers satisfactory performance and breakdown voltage and also satisfactory mechanical strength of the semiconductor substrate, and which needs no inconvenient control of the exposure system etc. during photolithography process.
  • a semiconductor device including a first main electrode provided on a first main surface of a semiconductor substrate and a second main electrode provided on a second main surface of said semiconductor substrate and wherein a main current flows in a thickness direction of said semiconductor substrate
  • said semiconductor substrate has at least one recess formed in said second main surface and therefore at least has a first region having a first thickness and a second region having a second thickness smaller than said first thickness, said second region corresponds to a region where said at least one recess is formed, said second main electrode is provided in said recess, and said second thickness is set at such a thickness as to satisfy the breakdown voltage of said semiconductor device.
  • the first thickness for example, can be set so that the semiconductor wafer is less likely to crack or break during manufacturing and so that no special focal depth control is needed for the exposure system etc.; this reduces occurrence of defects during manufacturing and reduces the manufacturing cost, and offers a semiconductor device achieving a balance between the reduction of on-state resistance and the sustainment of breakdown voltage.
  • a semiconductor device including a first main electrode provided on a first main surface of a semiconductor substrate and a second main electrode provided on a second main surface of said semiconductor substrate and wherein a main current flows in a thickness direction of said semiconductor substrate
  • said semiconductor substrate has at least one recess formed in said second main surface and therefore at least has a first region having a first thickness and a second region having a second thickness smaller than said first thickness, and wherein said second thickness is set at such a thickness as to keep a breakdown voltage of said semiconductor device, said second region corresponds to a region where said at least one recess is formed, said at least one recess is filled with a conductor layer, and said second main electrode is provided on a surface of said conductor layer.
  • the first thickness for example, can be set so that the semiconductor wafer is less likely to crack or break during manufacturing and so that no special focal depth control is needed for the exposure system etc.; this reduces occurrence of defects during manufacturing and reduces the manufacturing cost, and offers a semiconductor device achieving a balance between reducing the on-state resistance and keeping the breakdown voltage. Furthermore, filling the at least one recess with a conductor layer enhances the mechanical strength of the semiconductor substrate and facilitates handling of the semiconductor substrate during semiconductor device manufacturing process.
  • FIG. 1 is a cross-sectional view showing the structure of a semiconductor substrate used to manufacture a semiconductor device of the present invention
  • FIG. 2 is a plan view of the semiconductor substrate for a semiconductor device of the present invention.
  • FIG. 3 is a plan view showing the structure of a wafer of semiconductor substrates for semiconductor devices of the invention.
  • FIG. 4 is a cross-sectional view showing the structure of a semiconductor device of a first preferred embodiment of the invention.
  • FIG. 5 is a cross-sectional view showing the structure of a semiconductor device of a second preferred embodiment of the invention.
  • FIG. 6 is a cross-sectional view showing the structure of a semiconductor device of a third preferred embodiment of the invention.
  • FIG. 7 is a cross-sectional view showing the structure of a semiconductor device of a fourth preferred embodiment of the invention.
  • FIG. 8 is a cross-sectional view showing the structure of a semiconductor device of a fifth preferred embodiment of the invention.
  • FIG. 9 is a cross-sectional view showing the structure of a semiconductor device of a sixth preferred embodiment of the invention.
  • FIG. 10 is a cross-sectional view showing another example of structure of the semiconductor substrate for a semiconductor device of the invention.
  • FIG. 11 is a cross-sectional view showing another example of structure of the semiconductor substrate for a semiconductor device of the invention.
  • FIG. 12 is a cross-sectional view showing another example of structure of the semiconductor substrate for a semiconductor device of the invention.
  • FIG. 13 is a plan view showing the structure of a semiconductor substrate used to manufacture a semiconductor device of the invention.
  • FIG. 14 is a plan view showing the structure of a wafer of semiconductor substrates for semiconductor devices of the invention.
  • FIG. 15 is a plan view showing the positioning of dicing lines
  • FIG. 16 is a cross-sectional view showing the positioning of the dicing lines
  • FIG. 17 is a plan view showing the structure of a semiconductor wafer on which dicing lines are positioned
  • FIG. 18 is a plan view showing the structure of a semiconductor wafer on which dicing lines are positioned
  • FIG. 19 is a plan view showing the positioning of field contact rings
  • FIG. 20 is a cross-sectional view showing the positioning of the field, contact rings
  • FIG. 21 is a plan view showing the structure of a semiconductor substrate having a plurality of recesses
  • FIG. 22 is a plan view showing the structure of a wafer of semiconductor substrates having a plurality of recesses
  • FIG. 23 is a plan view showing the structure of a semiconductor substrate having a plurality of recesses
  • FIG. 24 is a cross-sectional view showing a modification of the structure of the semiconductor substrate for a semiconductor device of the invention.
  • FIG. 25 is a cross-sectional view showing the structure of a semiconductor substrate used to manufacture a semiconductor device of the invention.
  • FIG. 26 is a plan view showing the structure of a semiconductor substrate used to manufacture a semiconductor device of the invention.
  • FIG. 27 is a plan view showing the structure of a semiconductor substrate used to manufacture a semiconductor device of the invention.
  • FIG. 28 is a cross-sectional view showing the structure of a semiconductor device according to a seventh preferred embodiment of the invention.
  • FIG. 29 is a cross-sectional view showing a process step for manufacturing the semiconductor device of the seventh preferred embodiment of the invention.
  • FIG. 30 is a cross-sectional view showing a process step for manufacturing the semiconductor device of the seventh preferred embodiment of the invention.
  • FIG. 31 is a cross-sectional view showing a process step for manufacturing the semiconductor device of the seventh preferred embodiment of the invention.
  • FIG. 32 is a cross-sectional view showing a process step for manufacturing the semiconductor device of the seventh preferred embodiment of the invention.
  • FIG. 33 is a cross-sectional view showing a process step for manufacturing the semiconductor device of the seventh preferred embodiment of the invention.
  • FIG. 34 is a cross-sectional view showing a more specific structure of the semiconductor device of the seventh preferred embodiment of the invention.
  • FIG. 35 is a cross-sectional view showing a more limited application of the semiconductor device of the seventh preferred embodiment of the invention.
  • FIG. 36 is a cross-sectional view showing the structure of a first modification of the semiconductor device of the seventh preferred embodiment of the invention.
  • FIG. 37 is a cross-sectional view showing the structure of a second modification of the semiconductor device of the seventh preferred embodiment of the invention.
  • FIGS. 1 to 3 Before describing the preferred embodiments of the invention, the structure of a semiconductor substrate that is common to the preferred embodiments is now described referring to FIGS. 1 to 3 .
  • FIG. 1 is a cross-sectional view of a semiconductor substrate 1 used in common in the preferred embodiments.
  • the semiconductor substrate 1 shown in FIG. 1 has a first main surface MS 1 , a second main surface MS 2 on the opposite side, and a recess 9 defined in the second main surface MS 2 by side surfaces 91 and a bottom surface 92 .
  • the semiconductor substrate 1 has a peripheral region 1 A (first region) with a thickness A and a central region 1 B (second region) with a thickness B which is smaller than the thickness A.
  • the vertical thickness from the bottom surface 92 of the recess 9 to the first main surface MS 1 is the thickness B which is smaller than the thickness A.
  • the thickness A is set so that the semiconductor wafer will not break or crack during the semiconductor device manufacturing process and so that the photolithography process needs no special focal depth control of the exposure system etc. For example, it is set at 500-650 ⁇ m with a 6-inch semiconductor wafer.
  • the thickness B is determined in consideration of the reduction of on-state resistance and the requirement of breakdown voltage; for example, it is set at 60 ⁇ m with a semiconductor device having a breakdown voltage of 600 V.
  • FIG. 2 is a plan view of the semiconductor substrate 1 seen from the first main surface MS 1 side.
  • the recess 9 is located substantially in the center of the semiconductor substrate 1 and has a rectangular shape in plan view.
  • the area around the recess 9 forms the peripheral region 1 A with the thickness A.
  • the cross-section along line X-X seen in the arrow direction in FIG. 2 corresponds to FIG. 1 .
  • the recess 9 may of course be circular or oval, or more complicatedly shaped, in plan view.
  • FIGS. 1 and 2 is a semiconductor substrate processed into a semiconductor chip
  • the formation of the recess 9 is performed as a wafer processing step with a semiconductor wafer.
  • FIG. 3 shows recesses 9 corresponding to individual chips in a semiconductor wafer WF 1 , where a plurality of recesses 9 are disposed in a matrix on one main surface of the semiconductor wafer WF 1 .
  • This semiconductor wafer WF 1 is diced along given dicing lines to obtain a plurality of semiconductor substrates 1 .
  • a semiconductor device in which the main current flows in the thickness direction is manufactured using the semiconductor substrate 1 having regions with different thicknesses, which provides a first effect that the semiconductor wafer is less likely to break or crack, no special focal depth control is needed for the exposure system etc., and that the semiconductor device offers a good balance between the reduction of on-state resistance and the keeping of breakdown voltage.
  • the individual thinner regions have smaller areas relative to the total wafer area, which suppresses bowing of the thinner regions. Even if the semiconductor chips bow, they bow similarly because all semiconductor chip regions have the same structure, which provides a second effect of reducing characteristic variations among the semiconductor chips.
  • IGBTs Insulated Gate Bipolar Transistors
  • the parts relevant to the IGBT characteristics can be formed in the thinner central regions 1 B so that the radiation energy of the energy beam (electron beam, ion beam, etc.) radiated for carrier lifetime control can be reduced.
  • This provides a third effect that the formation depth of the lifetime control region can be more precise to enable lifetime control region formation with a smaller distribution width, so as to provide semiconductor devices with reduced characteristic variations.
  • FIG. 4 shows the structure of a semiconductor device 100 according to a first preferred embodiment.
  • the semiconductor device 100 has the semiconductor substrate 1 described with FIG. 1 and an electrode ML; the electrode ML is provided all over the second main surface MS 2 including the side walls 91 and the bottom surface 92 of the recess 9 in the semiconductor substrate 1 and is made of a material that makes ohmic contact (or Schottky contact) with the semiconductor substrate 1 .
  • the ohmic-contact material can be aluminum (Al) or an aluminum alloy.
  • the Schottky-contact material can be titanium (Ti), hafnium (Hf), nickel (Ni), or tungsten (W), for example.
  • Schottky diode With ohmic contact, no barrier is formed at the junction between the metal and semiconductor layer, so that current can flow in both directions. On the other hand, with Schottky contact, a barrier is formed at the junction between the metal and semiconductor layer, so that current can flow only in one direction but not in the opposite direction. Therefore Schottky contact can itself constitute a diode (Schottky diode).
  • the electrode ML on the second main surface of the semiconductor substrate 1 , where the recess 9 is formed is made of a material that makes ohmic contact, then an IGBT using the ohmic electrode as its collector electrode, or a diode using the ohmic electrode as its anode, can be formed to achieve a reduction of the element resistance in the current flowing state, which structure is suitable for relatively low operating frequency devices.
  • the electrode ML is made of a material that makes Schottky contact
  • an IGBT using the Schottky electrode as its collector electrode, or a diode using the Schottky electrode as its anode electrode can be formed to obtain an element with reduced power dissipation at switching, which structure is suitable for relatively high operating frequency devices.
  • the use of the semiconductor substrate 1 provides the first to third effects described earlier.
  • FIG. 5 shows the structure of a semiconductor device 200 according to a second preferred embodiment.
  • the semiconductor device 200 has the semiconductor substrate 1 described with FIG. 1 and a semiconductor region IP 1 provided in the entire second main surface MS 2 including the surface of the recess 9 of the semiconductor substrate 1 .
  • the impurity concentration of the semiconductor region IP 1 is set higher than the impurity concentration of the semiconductor substrate 1 .
  • the impurity concentration of the semiconductor substrate 1 is 1 ⁇ 10 13 /cm 3 to 1 ⁇ 10 15 /cm 3
  • the impurity concentration of the semiconductor region IP 1 is set at 1 ⁇ 10 20 /cm 3 or higher.
  • IGBTs, diodes, and MOSFETs MOS field effect transistors
  • IGBTs, diodes, and MOSFETs MOS field effect transistors
  • electrodes relevant to characteristics of the elements i.e. anodes, cathodes, collectors, drains, etc.
  • the central region 1 B having the thickness B determined in consideration of on-state resistance reduction and breakdown voltage.
  • the use of the semiconductor substrate 1 provides the first to third effects described earlier.
  • FIG. 6 shows the structure of a semiconductor device 300 according to a third preferred embodiment.
  • the semiconductor device 300 has the semiconductor substrate 1 described with FIG. 1 and a semiconductor region IP 2 provided in the entire second main surface MS 2 including the surface of the recess 9 of the semiconductor substrate 1 .
  • the impurity conductivity type of the semiconductor region IP 2 is set opposite to the impurity conductivity type of the semiconductor substrate 1 .
  • the impurity conductivity type of the semiconductor substrate 1 is N type
  • the impurity conductivity type of the semiconductor region IP 2 is P type. This provides a diode in which the second main surface MS 2 side works as the anode.
  • Reversing the impurity conductivity type of the semiconductor substrate 1 and that of the semiconductor region IP 2 provides a diode in which the second main surface MS 2 side works as the cathode.
  • the use of the semiconductor substrate 1 provides the first and second effects described earlier.
  • FIG. 7 shows the structure of a semiconductor device 400 according to a fourth preferred embodiment.
  • the semiconductor device 400 has the semiconductor substrate 1 described referring to FIG. 1 and a semiconductor region IP 3 provided in the entire second main surface MS 2 including the surface of the recess 9 of the semiconductor substrate 1 .
  • the impurity conductivity type of the semiconductor region IP 3 is the same as the impurity conductivity type of the semiconductor substrate 1 .
  • the impurity conductivity type of the semiconductor substrate 1 is N type
  • the impurity conductivity type of the semiconductor region IP 3 is N type. Then, by forming a P-type semiconductor region (not shown) on the first main surface MS 1 side, a diode having the second main surface MS 2 as the cathode can be obtained.
  • the second main surface MS 2 can be made suitable for ohmic contact by setting the impurity concentration of the semiconductor region IP 3 higher than that of the semiconductor substrate 1 .
  • the use of the semiconductor substrate 1 provides the first and second effects described earlier.
  • FIG. 8 shows the structure of a semiconductor device 500 according to a fifth preferred embodiment.
  • the semiconductor device 500 has the semiconductor substrate 1 described with FIG. 1 , an electrode ML 2 provided on the bottom surface 92 of the recess 9 of the semiconductor substrate 1 , electrodes ML 1 provided on the peripheral region 1 A on the second main surface MS 2 side, and insulating films IL provided on the side walls 91 of the recess 9 , for electrically insulating the electrodes ML 1 and ML 2 .
  • FIG. 9 shows the structure of a semiconductor device 600 according to a sixth preferred embodiment.
  • the semiconductor device 600 has the semiconductor substrate 1 described with FIG. 1 , a semiconductor region IP 5 provided in the surface of the bottom 92 of the recess 9 of the semiconductor substrate 1 , semiconductor regions IP 4 provided in the surface of the peripheral region 1 A on the second main surface MS 2 side, and insulating films IL provided on the side walls 91 of the recess 9 , for electrically insulating the semiconductor regions IP 4 and IP 5 .
  • a control electrode and a first main electrode are formed on the first main surface MS 1 and an N-channel MOS transistor is formed on the first main surface MS 1 side.
  • the semiconductor region IP 5 in the surface of the bottom 92 of the recess 9 is formed as a P-type semiconductor region and the semiconductor regions IP 4 in the surface of the peripheral region 1 A are formed as N-type semiconductor regions, and second main electrodes are formed respectively on the semiconductor regions IP 4 and IP 5 .
  • the P-type semiconductor region IP 5 , the N-type semiconductor substrate 1 , and the N-channel MOS transistor form an IGBT
  • the N-type semiconductor regions IP 4 , the N-type semiconductor substrate 1 , and the P-type semiconductor region forming the N-channel MOS transistor form a diode.
  • the IGBT and diode operate in a complementary manner when the potential applied to the first and second main electrodes is varied, forming a half bridge.
  • the area ratio between the cathode and collector electrodes can be varied by varying the area of the recess 9 .
  • An energy beam (electron beam, ion beam, etc.) for carrier lifetime control can be applied to the peripheral region 1 A from the second main surface MS 2 side to form a lifetime control region, so as to effect lifetime control only in the peripheral region 1 A. It is then possible to reduce the recovery of the diode without deteriorating IGBT operation.
  • a more specific structure of the semiconductor device 600 will be described later in a seventh preferred embodiment.
  • a substrate having three kinds of thicknesses may be used. That is to say, on the second main surface MS 2 opposite to the first main surface MS 1 , it has a two-stepped recess 9 A having bottom surfaces 93 and 94 at different depths.
  • the semiconductor substrate 2 has a peripheral region 2 A (first region) with a thickness A, a first central region 2 B (second region) with a thickness B, and a second central region 2 C with a thickness C.
  • the thickness A of the peripheral region 2 A is the thickest
  • the vertical thickness from the bottom surface 93 of the recess 9 A to the first main surface MS 1 is the thinnest thickness B
  • the vertical thickness from the bottom surface 94 of the-recess 9 A to the first main surface MS 1 is the thickness C, where the thickness C is intermediate between the thickness A and thickness B.
  • the thickness A and the thickness B are set respectively at 500 to 650 ⁇ m and 60 ⁇ m, and with a semiconductor device with a breakdown voltage of 1200 V, the thickness C is set at 120 ⁇ m.
  • the recess 9 A thus has the bottom surfaces 93 and 94 at different depths and hence the semiconductor substrate 2 has three kinds of thicknesses, which enables formation of more kinds of semiconductor elements.
  • the semiconductor substrate 3 of FIG. 11 has recesses 9 and 9 B at different depths in the second main surface MS 2 opposite to the first main surface MS 1 .
  • the semiconductor substrate 3 has a peripheral region 3 A (first region) with a thickness A, a thinnest region 3 B (second region) with a thickness B that corresponds to the recess 9 , and an intermediate thickness region 3 C with a thickness C that corresponds to the recess 9 B.
  • the dimensional relation among the thicknesses A, B and C is set like that of the semiconductor substrate 2 .
  • the thickness is not limited to three kinds; semiconductor substrates having three or more kinds of thicknesses can be obtained by forming a multi-stepped recess or a plurality of recesses with different depths.
  • the structure of a semiconductor substrate having two kinds of thicknesses is not limited to that of the semiconductor substrate 1 of FIG. 1 ; the structure may be like that shown in FIG. 12 .
  • the semiconductor substrate 4 shown in FIG. 12 has a recess 9 formed in one side area of the second main surface MS 2 and it thus has a thinnest region 4 B (second region) having a thickness B that corresponds to the recess 9 and a peripheral region 4 A (first region) having a thickness A around the first region 4 B.
  • the side area opposite to the side area where the recess 9 is formed has no recess and therefore it forms a uniform thickness region 4 C (first region) having the single thickness A.
  • the semiconductor substrate 4 thus structured allows formation of plural kinds of semiconductor elements having different functions and characteristics; in the thinnest region 4 B and peripheral region 4 A, a semiconductor device in which the main current flows in the substrate thickness direction can be formed as in the semiconductor substrate 1 , and a semiconductor device in which the main current flows in the substrate plane direction can be formed in the single-thickness region 4 C.
  • the recess 9 of the semiconductor substrate 1 is rectangular-shaped in plan view, surrounded by the peripheral region 1 A; however, it may be shaped like a stripe as shown in FIG. 13 . That is to say, the semiconductor substrate 5 shown in FIG. 13 has peripheral regions 5 A (first region) only along its two parallel sides and a central region 5 B (second region) between the peripheral regions 5 A: the central region 5 B corresponds to a recess 90 shaped like a stripe.
  • the cross-section taken along line Y-Y in FIG. 13 seen from the direction of arrows, corresponds to FIG. 1 .
  • the recess 9 or recess 90 is located substantially in the center of the substrate. Therefore, when the semiconductor substrate is processed to produce a semiconductor chip, the semiconductor chip can be placed horizontally on the die pad during die bonding. That is to say, the peripheral regions on the four sides or two parallel sides come in contact with the die pad so that the semiconductor chip is not inclined with respect to the die pad. Thus, during interconnecting process by wire-bonding, the wires and semiconductor chips can always be bonded at the same angle, enabling uniform wire bonding. This prevents current convergence due to non-uniform contact resistance in the bonded parts.
  • FIG. 14 is a plan view of a semiconductor wafer for obtaining semiconductor substrates 5 of FIG. 13 .
  • FIG. 14 shows a semiconductor wafer WF 2 with stripe-like recesses 90 ; a plurality of stripe-shaped recesses 90 are arranged in parallel on one main surface of the semiconductor wafer WF 2 .
  • the semiconductor wafer WF 2 can be diced along given dicing lines to obtain a plurality of semiconductor substrates 5 .
  • the semiconductor devices 100 to 600 described in the first to sixth preferred embodiments are separated along given dicing lines into individual chips.
  • the dicing lines and semiconductor substrates 1 are positioned as shown in FIG. 15 .
  • a semiconductor substrate 1 is surrounded by vertical dicing lines DL 1 and horizontal dicing lines DL 2 .
  • FIG. 16 shows the cross-section taken along line W-W in FIG. 15 .
  • the areas where the dicing lines DL 1 and DL 2 are located have the thickness A; during dicing, this prevents the semiconductor substrate 1 from warping when hit by the edge of a dicer, thereby preventing the semiconductor substrate 1 from being damaged and the dicing lines from being bent.
  • FIG. 17 is a plan view showing the semiconductor wafer WF 1 for obtaining the semiconductor substrates 1 together with the dicing lines DL 1 and DL 2 disposed thereon.
  • FIG. 18 is a plan view showing the semiconductor wafer WF 2 for obtaining the semiconductor substrates 5 together with the dicing lines DL 1 and DL 2 disposed thereon.
  • the vertical dicing lines DL 2 extend over the stripe-shaped recesses 90 and therefore cut thinner portions, but the semiconductor substrate 1 will not warp while being diced because both sides of the recesses 90 form the thick peripheral regions 1 A as mentioned earlier.
  • the semiconductor devices 100 to 600 of the first to sixth preferred embodiments have not specifically shown the structure of the first main surface; with high-voltage semiconductor devices, field contact rings (also called field limiting rings) are often formed in the first main surface in order to relax electric fields in the peripheral area of the semiconductor chip.
  • field contact rings also called field limiting rings
  • Field contact rings contain impurities of a conductivity type opposite to that of the substrate to form junctions with the substrate; they are desirably formed in thicker areas to relax electric fields nearly along the substrate shape, and thinned areas where recesses are formed are not always appropriate for field contact rings.
  • field contact rings FCR may be provided as shown in FIG. 19 in the peripheral region 1 A surrounding the recess 9 to effectively alleviate electric fields vertical to the substrate main surface.
  • FIG. 20 shows the cross-section along line Z-Z in FIG. 19 . As shown in FIG. 20 , a sufficient thickness is ensured under the field contact rings FCR to allow a margin for transient extension of depletion layers.
  • field contact rings FCR can be formed as long as the thickness B of the central region 5 B, corresponding to the recess 90 , is larger than the depth of the field contact rings FCR and therefore field contact rings FCR may be formed not only in the peripheral regions 5 A of the semiconductor substrate 5 but also across the central region 5 B.
  • FIG. 19 shows filed contact rings FCR surrounding just a single recess 9 , they may be formed also in substrates having a plurality of recesses, like the semiconductor substrate 3 shown in FIG. 11 .
  • FIG. 21 shows the structure of a semiconductor substrate 6 having two recesses 19 in the area surrounded by filed contact rings FCR.
  • the area other than the recesses 19 is thicker; it can be said that the cross-sectional view along U-U in FIG. 21 corresponds to the cross-sectional structure of the semiconductor substrate 3 of FIG. 11 and the cross-sectional view along line V-V corresponds to the cross-sectional structure of the semiconductor substrate 4 of FIG. 12 .
  • FIG. 22 is a plan view showing a semiconductor wafer for obtaining semiconductor substrates having a plurality of recesses, like the semiconductor substrate 6 shown in FIG. 21 .
  • FIG. 22 shows a plurality of recesses 19 provided in each chip area on a semiconductor wafer WF 3 , where the plurality of recesses 19 are disposed in a matrix on one main surface of the semiconductor wafer WF 3 .
  • the semiconductor wafer WF 3 is diced along given dicing lines to obtain a plurality of semiconductor substrates 6 .
  • the number of recesses formed in a semiconductor substrate is not limited to two, and recesses are not necessarily shaped the same and are not always positioned symmetrically.
  • the semiconductor substrate 60 shown in FIG. 23 has rectangular recesses 191 and 192 and an L-shaped recess 193 .
  • the recess 191 and recesses 192 are all rectangular but have different areas, with just a single recess 191 and a plurality of recesses 192 .
  • a semiconductor wafer for obtaining semiconductor substrates having such recesses has a plan view where a plurality of dot-like recesses are formed densely all over one main surface of the semiconductor wafer.
  • the side surfaces of the recesses are vertical to the substrates' main surfaces. Therefore, the side surfaces of the recesses cannot be seen when the recesses are seen from the second main surface side.
  • the side surfaces 96 of the recess 9 C may be inclined to form an angle ⁇ exceeding 90° with the substrate main surface. Then, when the recess is seen from the second main surface side, the side surfaces of the recess can be seen.
  • the peripheral region 7 A first region
  • the central region 7 B second region
  • the inclination angle that the side surfaces 96 form with the bottom surface 95 is shown as angle ⁇ just for convenience, assuming that the bottom surface 95 is parallel to the substrate's main surface.
  • the maximum value of the angle ⁇ is around 175°.
  • the side surfaces 96 inclined at an angle exceeding 90° prevent transfer errors and cuts of the angular portions of the recesses 9 C that would otherwise occur as the angular portions are caught on some projections of the transfer system.
  • an electrode ML is formed all over the second main surface MS 2 as shown in FIG. 4 , or when a semiconductor region IP 1 is formed in the second main surface MS 2 as shown in FIG. 5 , this facilitates formation of the electrodes ML and semiconductor region IP 1 on the side surfaces.
  • a semiconductor substrate having a plurality of thicknesses can be obtained by forming a plurality of recesses at different depths; likewise, as shown in FIG. 25 , a plurality of recesses with the same depth may be formed so that a plurality of elements of the same kind can be fabricated.
  • the semiconductor substrate 8 of FIG. 25 has a plurality of recesses 9 D defined by side surfaces 97 and bottom surfaces 98 in the second main surface MS 2 opposite to the first main surface MS 1 . It thus has recessed regions 8 B (second region) having a thickness B and corresponding to the recesses 9 D and the remaining mesa regions 8 A (first region) having a thickness A.
  • FIG. 26 shows an example of plan view of the semiconductor substrate 8 seen from the second main surface side.
  • the recesses 9 D are shaped in stripes, where a plurality of stripe-shaped recesses 9 D are arranged in parallel in the main surface of the semiconductor substrate 8 .
  • a cross-section cut across the plurality of recesses 9 D corresponds to the sectional structure of FIG. 26 .
  • FIG. 27 shows another example of plan view of the semiconductor substrate 8 .
  • the recesses 9 D are rectangular in shape, where a plurality of rectangular recesses 9 D are arranged in a matrix in the main surface of the semiconductor substrate 8 .
  • the seventh preferred embodiment of the invention now describes the structure of a semiconductor device 700 manufactured using the semiconductor substrate 8 shown in FIG. 25 . It is assumed here that the semiconductor substrate 8 is shaped as shown in FIG. 26 in plan view.
  • FIG. 28 shows the sectional structure of the semiconductor device 700 according to the sixth preferred embodiment of the invention. Note that the cross-section of FIG. 28 shows a semiconductor device structure that is formed with one recess 9 D in the semiconductor substrate 8 of FIG. 25 . It is assumed that the semiconductor substrate 8 is processed as a high-resistivity N-type substrate.
  • a P-type semiconductor region 902 is formed in the entire first main surface MS 1 of the semiconductor substrate 8 .
  • Two trenches 903 extend from the first main surface MS 1 through the P-type semiconductor region 902 to reach the inside of the semiconductor substrate 8 , with their inner walls covered by gate insulating films 904 .
  • Each trench 903 , covered by the gate insulating film 904 is filled with a conductor to form a gate electrode 905 .
  • relatively high concentrated N-type semiconductor regions 906 are selectively formed in such a way that at least parts of them are in contact with the gate insulating films 904 .
  • relatively high concentration P-type semiconductor regions 907 are formed between opposite N-type semiconductor regions 906 between the trenches. The P-type semiconductor regions 907 are provided to obtain good electric contact with the P-type semiconductor region 902 .
  • First main electrodes 908 are provided each in contact with top portions of adjacent N-type semiconductor regions 906 and a P-type semiconductor region 907 .
  • the first main electrodes 908 apply potential to the N-type semiconductor regions 906 and P-type semiconductor regions 907 from an external terminal ET. Depending on operation of the semiconductor device 700 , the first main electrodes 908 may function as the emitter electrode, or the anode or source electrode. Control voltage is applied to the gate electrodes 905 from an external terminal GT.
  • a P-type collector region 912 is provided in the surface of the semiconductor substrate 8 in the portion that corresponds to the bottom surface 98 .
  • N-type semiconductor regions 913 reside in the surface of the mesa region 8 A of the second main surface MS 2 .
  • Sidewall insulating films 914 are formed on the side surfaces of the recess 9 D to provide electrical separation in the substrate surface between the P-type collector region 912 and the N-type semiconductor regions 913 .
  • a second main electrode 916 a and third main electrodes 916 b reside in contact with the P-type collector region 912 and the N-type semiconductor regions 913 .
  • the second main electrode 916 a applies potential to the P-type collector region 912 from an external terminal CT and the third main electrodes 916 b apply potential to the N-type semiconductor regions 913 from an external terminal KT.
  • the second main electrode 916 a functions as the collector electrode, and the third main electrodes 916 b function as the cathode electrode or the drain electrode, depending on operation of the semiconductor device 700 .
  • a lifetime control region 915 where carrier lifetime is shortened is provided close to the second main surface MS 2 .
  • This region is formed by radiation of an electron beam or an ion beam such as proton or He.
  • the semiconductor device 700 operates as IGBT, diode, and MOSFET, depending on voltage conditions applied to the first to third main electrodes. That is to say, when the external terminal ET is at ground potential and the external terminal CT is at positive potential, then it operates as IGBT according to the signal applied to the external terminal GT.
  • the external terminal ET When the external terminal ET is at ground potential, the external terminal KT is at negative potential, and the external terminal GT is supplied with an off signal, then it operates as diode.
  • the external terminal ET when the external terminal ET is at ground potential and the external terminal KT is at positive potential, it operates as MOSFET according to the signal applied to the external terminal GT.
  • the P-type collector region 912 and N-type semiconductor regions 913 are formed at a distance so that it operates as IGBT when the external terminal CT and external terminal KT are at a same positive potential. That is to say, the distance between them (i.e. resistance value) is set so that, when a set small current flows to the cathode, the potential of the semiconductor substrate in the vicinity of the collector region is not less than the work function difference of the PN junction.
  • the first main electrodes 908 serve as the emitter electrode
  • the second main electrode 916 a serves as the collector electrode
  • the N-type semiconductor regions 906 in the first main surface MS 1 serve as the emitter region
  • the P-type semiconductor region 902 serves as the body region including channel region
  • the P-type semiconductor regions 907 serve as the body contact region.
  • the first main electrodes 908 serve as the anode electrode
  • the third main electrodes 916 b serve as the cathode electrode
  • the P-type semiconductor region 902 in the first main surface MS 1 serves as the anode region
  • the P-type semiconductor regions 907 serve as the anode contact region
  • the N-type semiconductor regions 913 in the surface of the mesa region 8 A on the second main surface MS 2 side serve as the cathode region.
  • the first main electrodes 908 serve as the source electrode
  • the third main electrodes 916 b serve as the drain electrode
  • the N-type semiconductor regions 906 serve as the source region
  • the P-type semiconductor region 902 serves as the body region including channel region
  • the P-type semiconductor regions 907 serve as the body contact region
  • the N-type semiconductor regions 913 serve as the drain region.
  • a method for manufacturing the semiconductor device 700 will now be described referring to the cross-sectional views of FIGS. 29 to 33 showing a sequence of process steps.
  • the semiconductor substrate 8 and a process for forming the components on the first main surface MS l side are described referring to FIG. 28 .
  • the high-resistivity N-type semiconductor substrate 8 its resistivity and the distance L between the bottom of P-type collector region 912 and the bottom of trench 903 vary depending on the voltage class; for example, in 1200-V class, the resistivity is set at 40 to 60 ⁇ cm and the distance L is set at about 100 to 200 ⁇ m, and the resistivity is set lower and the distance L is set shorter in lower voltage classes.
  • the P-type semiconductor region 902 serves as the body region including channel region, so that its impurity concentration and depth are set on the basis of the threshold voltage of the MOSFET or IGBT.
  • the impurity concentration and diffusion depth are determined by ion implantation conditions and thermal diffusion conditions.
  • the impurity concentration is usually set so that it is 1 ⁇ 10 17 /cm 3 to 1 ⁇ 10 18 /cm 3 in the region in contact with the source electrode of MOSFET or emitter electrode of IGBT and the diffusion depth is set at several ⁇ m so that it does not extend over the trenches 903 .
  • the trenches 903 are provided by etching at a pitch of 2 to 10 ⁇ m, with their width at 0.5 to 3.0 ⁇ m and depth at 3 to 20 ⁇ m.
  • the gate insulating film 904 on the inner surfaces of the trenches 903 is an insulating film forming MOSFET, whose thickness is optimized on the basis of the gate driving voltage, saturation current, capacitance, etc.
  • a silicon oxide film having a thickness of 10 to 200 nm is formed by thermal oxidation or deposition, for example.
  • the gate electrodes 905 buried in the trenches 903 are formed of a high-impurity-concentration polycrystalline silicon film, a refractory metal material like tungsten silicide, or a multi-layered film thereof. In general, they are obtained by depositing, on the first main surface MS 1 , a conductive film to a thickness not less than half the width of the trenches 903 and planarizing it by, e.g. anisotropic etching; they may be obtained by forming a mask with given pattern through photolithography, depositing a conductive film, and etching it.
  • the optimum concentration for the P-type semiconductor region 902 varies depending on the work function of the material of the gate electrodes 905 ; in extreme cases, a buried channel structure may be adopted in which N-type semiconductor regions are formed along the sides of the trenches 903 and a thin layer of the same conductivity type (N type) as the emitter region is formed in regions in contact with the gate insulating films.
  • the N-type semiconductor regions 906 and P-type semiconductor regions 907 are both formed by patterning with photolithography and ion implantation, whose surface concentration is set at 1 ⁇ 10 20 /cm 3 or more.
  • the first main electrodes 908 are made by forming an interlayer insulating film (not shown) covering the N-type semiconductor regions 906 and P-type semiconductor regions 907 , selectively forming openings by photolithography and etching, and depositing a conductive film of a compound of aluminum and silicon, for example.
  • a protective film (not shown) is formed on the first main electrodes 908 and connection to an external power supply is made through openings in given areas of the protective film.
  • the first main surface MS 1 is covered with a resist mask RM 1 .
  • a resist mask RM 2 having an opening for the formation of recess 9 D is formed on the second main surface MS 2 and the semiconductor substrate 8 is etched by anisotropic etching using that resist mask RM 2 to form the recess 9 D.
  • the depth of the recess 9 D is optimized according to the voltage class of the semiconductor device 700 , the final thickness of the semiconductor substrate 8 , cost, etc.
  • the distance L (see FIG. 28 ) between the P-type collector region 912 and the bottom of trench 903 is set at 100 to 200 ⁇ m in 1200-V class, as mentioned earlier; the distance L is set shorter in lower voltage classes.
  • the minimum value of the depth of the recess 9 D is set so that IGBT operates when the same potential is applied to the P-type collector region 912 as the IGBT collector and the drain regions 913 (see FIG. 28 ) as MOSFET and a voltage is applied to the gate electrodes 905 such that a channel turns ON.
  • the depth of the recess 9 D is thus determined on the basis of the resistivity of the mesa region 8 A of the semiconductor substrate 8 , the impurity concentration of the P-type collector region 912 , the area ratio between the P-type collector region 912 and N-type semiconductor regions 913 , the rated current density, the allowable range of the relation between voltage and current when MOSFET operation changes to IGBT operation, i.e. the allowable range for snap back, and so forth.
  • the width and pitch of the recesses 9 D can be set arbitrarily; the width is typically 0.2 to 100 ⁇ m, which is set so that imbalance will not occur in the area ratio between the P-type collector region 912 and the N-type semiconductor regions 913 , as mentioned earlier.
  • the formation of the recess 9 D may be performed at other stages than that mentioned above; however, it is desirable to form it before formation of the first main electrodes 908 , when metal contamination by electrode material, generally heavy metal, is taken into consideration.
  • an insulating film IL 1 is formed all over the second main surface.
  • the insulating film IL 1 is formed by selective oxidation or deposition.
  • an anisotropic etching process is applied so that it remains as sidewall insulating films 914 only on the side surfaces 97 of the recess 9 D.
  • the sidewall insulating films 914 can be formed either before or after the formation of the P-type collector region 912 and the N-type semiconductor regions 913 ; however, it is desirable to form the sidewall insulating films 914 before formation of the N-type semiconductor regions 913 and P-type collector region 912 because several percent to several tens of percent of the impurities for their formation may be introduced into the regions corresponding to the side surfaces 97 of the recess 9 D.
  • a resist mask RM 3 having an opening corresponding to the recess 9 D is formed on the second main surface MS 2 .
  • the P-type collector region 912 is formed by ion implantation into the surface of the semiconductor substrate 8 in the bottom surface 98 of the recess 9 D.
  • the ion implantation for formation of the P-type collector region 912 preferably adopts an inclined rotational ion implantation process in which ions are implanted in an inclined direction, with the substrate inclined and rotated.
  • the impurity concentrations of the P-type collector region 912 and the N-type semiconductor regions 913 are both set in the range of 1 ⁇ 10 16 to 1 ⁇ 10 21 /cm 3 . Basically, either of them may be formed first, but it is desirable to form the P-type collector region 912 first, as will be explained later.
  • the recess 9 D is covered with a resist mask RM 4 and then an electron beam or proton or He ions, for example, are applied from the second main surface MS 2 side to form a crystal defect region in a portion of the mesa region 8 A close to the second main surface MS 2 , thus forming the lifetime control region 915 with shortened carrier lifetime.
  • the formation of the lifetime control region 915 may be performed at other stages than that mentioned above, but it is desirably formed after annealing of the P-type collector region 912 and the N-type semiconductor regions 913 , because a lesser degree of activation by annealing suffices for the lifetime control region 915 than for the activation of the P-type collector region 912 and N-type semiconductor regions 913 .
  • the lifetime control region 915 suppresses carrier amplification rate and enhances recovery characteristic.
  • the first main electrodes 908 are formed on the first main surface MS 1 and the second main electrode 916 a and third main electrodes 916 b are formed on the second main surface, thus completing the semiconductor device 700 .
  • the second main electrode 916 a and third main electrodes 916 b are made of a multi-layered metal film containing gold or silver.
  • the semiconductor device 700 of FIG. 28 has shown a structure in which the second main electrode 916 a resides at the bottom 98 of the recess 9 D in direct contact with the P-type collector region 912 and is connected to the external terminal CT; however, in practice, as shown in FIG. 34 , for example, the recess 9 D is filled with a conductor layer 920 and the second main electrode 916 a is formed not at the bottom 98 of the recess 9 D but on the surface of the conductor layer 920 .
  • This structure facilitates connection with the external terminal CT and filling the recess 9 D with the conductor layer 920 increases the mechanical strength of the semiconductor substrate 8 , which facilitates handling of the semiconductor substrate 8 during the semiconductor device manufacturing process.
  • the conductor layer 920 which is a refractory metal layer such as tungsten (W) or titanium (Ti), is buried in the recess 9 D after the formation of the P-type collector region 912 described referring to FIG. 32 . It is desirable to fill the recess 9 D in an earlier stage of the manufacturing process; forming the N-type semiconductor regions 913 and the lifetime control region 915 after the recess 9 D has been filled means that the ion implantation processes are applied to mechanically strengthened semiconductor substrate 8 , which facilitates handling, e.g. transfer, of the semiconductor substrate 8 .
  • the semiconductor device 700 of FIG. 28 has shown the second main electrode 916 a and third main electrodes 916 b as independent electrodes; however, as shown in FIG. 35 as a semiconductor device 700 A, the recess 9 D may be filled with conductor layer 920 with a common main electrode 916 lying over both of the surfaces of the N-type semiconductor regions 913 and the surface of the conductor layer 920 .
  • the common main electrode 916 is connected to the external terminal CT.
  • the semiconductor device 700 A when a same positive potential is applied to the N-type semiconductor regions 913 and P-type collector region 912 , the semiconductor device 700 A can operate as IGBT since the P-type collector region 912 and the N-type semiconductor regions 913 (cathode region) are separated at a distance.
  • the first main electrodes 908 serve as the emitter electrode
  • the common main electrode 916 serves as the collector electrode
  • the N-type semiconductor regions 906 in the first main surface MS 1 serve as the emitter region
  • the P-type semiconductor region 902 serves as the body region including channel region
  • the P-type semiconductor regions 907 serve as the body contact region.
  • the first main electrodes 908 serve as the anode electrode
  • the common main electrode 916 serves as the cathode electrode
  • the P-type semiconductor region 902 in the first main surface MS 1 serves as the anode region
  • the P-type semiconductor regions 907 serve as the anode contact region
  • the N-type semiconductor regions 913 in the surface of the mesa region 8 A on the second main surface MS 2 side serve as the cathode region.
  • the common main electrode 916 is formed on the second main surface MS 2 , which simplifies the manufacturing process as compared with a process in which a plurality of main electrode patterns are formed on the second main surface MS 2 side.
  • the semiconductor devices 700 and 700 A of the seventh preferred embodiment have shown structures in which the N-type semiconductor regions 913 are provided in the surface of the mesa region 8 A on the second main surface MS 2 side; however, as shown in FIG. 36 as a semiconductor device 700 B, P-type semiconductor regions 912 a may replace the N-type semiconductor regions 913 .
  • This structure does not need electrical separation between the P-type collector region 912 and the P-type semiconductor regions 912 a, which removes the need for sidewall insulating films on the side surfaces of the recess 9 D.
  • the semiconductor device 700 B has a recess 9 D filled with a conductor layer 920 with a common main electrode 916 lying over the surfaces of both of the P-type semiconductor regions 912 a and the conductor layer 920 .
  • the common main electrode 916 is connected to the external terminal CT.
  • the semiconductor device 700 B when a same positive potential is applied to the P-type collector region 912 and P-type semiconductor regions 912 a, the semiconductor device 700 B can operate as IGBT.
  • the semiconductor device 700 B when the semiconductor device 700 B operates as IGBT, the first main electrodes 908 serve as the emitter electrode, the common main electrode 916 serves as the collector electrode, the N-type semiconductor regions 906 in the first main surface MS 1 serve as the emitter region, the P-type semiconductor region 902 serves as the body region including channel region, and the P-type semiconductor regions 907 serve as the body contact region.
  • N-type semiconductor regions 913 are provided in the surface of the mesa region 8 A on the second main surface MS 2 side; however, as shown in FIG. 37 as a semiconductor device 700 C, P-type semiconductor regions 912 a may replace the N-type semiconductor regions 913 , with P-type semiconductor regions 912 b formed in the surface of the N-type semiconductor substrate 8 in the portions defining the sides of the recess 9 D, where the P-type collector region 912 and the P-type semiconductor regions 912 a are thus electrically connected through the P-type semiconductor regions 912 b.
  • the recess 9 D is filled with a conductive layer 920 and a common main electrode 916 is disposed over the surfaces of the P-type semiconductor regions 912 a and the conductor layer 920 .
  • the common main electrode 916 is connected to the external terminal CT.
  • the semiconductor device 700 C when a same positive potential is applied to the P-type collector region 912 and P-type semiconductor regions 912 a, the semiconductor device 700 C can operate as IGBT.
  • the semiconductor device 700 C when the semiconductor device 700 C operates as IGBT, the first main electrodes 908 serve as the emitter electrode, the common main electrode 916 serves as the collector electrode, the N-type semiconductor regions 906 in the first main surface MS 1 serve as the emitter region, the P-type semiconductor region 902 serves as the body region including channel region, and the P-type semiconductor regions 907 serve as the body contact region.
  • the P-type semiconductor regions 912 b reside in the surface of the N-type semiconductor substrate 8 in the portions defining the sides of the recess 9 D and the recess 9 D is filled with the conductor layer 920 ; therefore, during IGBT operation, holes can easily flow into the semiconductor device 700 C from the external terminal CT through the P-type semiconductor regions 912 b, which enables high-speed operation.
  • P-type collector region 912 P-type semiconductor regions 912 a and P-type semiconductor regions 912 b offers an increased area of P-type impurity region, which increases current during IGBT operation and reduces the on-state voltage.
  • the P-type semiconductor regions 912 b can be formed without complicating the manufacturing process, by utilizing the inclined rotational ion implantation process that is performed to form the P-type collector region 912 in the surface of the semiconductor substrate 8 in the portion corresponding to the bottom 98 of the recess 9 D. In this case, the P-type semiconductor regions 912 b can be formed by further inclining the substrate than it is inclined for the formation of the P-type collector region 912 .
  • While the semiconductor device 700 described as the seventh preferred embodiment has common trench-type elements on the first main surface MS 1 side, modified structures of trench-type elements may be adopted on the first main surface MS 1 side, or planar-type elements may be adopted. Thyristor structure may also be adopted in place of the transistor structure.
  • the semiconductor substrate 8 is of N type, it can of course be P type.
  • the semiconductor device 700 has the P-type collector region 912 at the bottom of the recess 9 D; however, the P-type collector region may be removed if the bottom surface of the recess 9 D substantially functions as a P-type region without the need for introduction of P-type impurities, depending on the crystalline roughness of the bottom surface of the recess 9 D, for example.
  • a rougher surface offers more P-type characteristics, and even when P-type impurities are introduced, the rougher the recess's bottom surface becomes, the smaller the carrier emission energy at the acute corners becomes, which facilitates hole injection and reduces on-state voltage.
  • the on-state voltage reduction effect provided by roughening the surface of the P-type collector region can be applied also to so-called NPT (non-punch-through) type IGBTs in which no recess exists in the second main surface MS 2 of the semiconductor substrate 8 and the depth of the P-type collector region is 2.0 ⁇ m or less.
  • NPT non-punch-through
  • the semiconductor device 700 has shown the second main electrode 916 a and the third main electrodes 916 b connected respectively to the external terminal CT and the external terminal KT, the second main electrode 916 a and the third main electrodes 916 b may be connected through the sidewall insulating films 914 .
  • the semiconductor device 700 has lifetime control region 915 for suppressing recovery as diode, it can be removed depending on specifications of the semiconductor device 700 .
  • a lifetime control region 915 may be formed in a portion closer to the first main surface MS 1 than the P-type collector region 912 .
  • a lifetime control region may be formed substantially in the entirety of the semiconductor substrate 8 .

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US20100038707A1 (en) 2010-02-18
US7635892B2 (en) 2009-12-22
KR20040095284A (ko) 2004-11-12
WO2004066391A1 (fr) 2004-08-05
US20070075332A1 (en) 2007-04-05
CN100414713C (zh) 2008-08-27
TWI241634B (en) 2005-10-11
EP1601020A1 (fr) 2005-11-30
TW200425275A (en) 2004-11-16
DE60332500D1 (de) 2010-06-17
JPWO2004066394A1 (ja) 2006-05-18
WO2004066394A1 (fr) 2004-08-05

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