TWI852733B - Method of forming semiconductor device - Google Patents

Abstract

The present disclosure provides a semiconductor device and a method of forming the same. The method includes following steps. Stacked patterns are formed on a substrate and each includes a select gate and a mask layer on the select gate. A first dielectric material layer is formed on a top surface and sidewalls of each stacked pattern. A floating gate pattern is formed between the two adjacent stacked patterns, wherein a top surface of the floating gate pattern is lower than a top surface of the mask layer. Spacers are formed on the sidewalls of each stacked pattern. A portion of the floating gate pattern exposed by the spacers is removed to form floating gates facing each other. The spacers, a portion of the first dielectric material layer, and the mask layer are removed to form a first dielectric layer between the select gate and the floating gate.

Description

Method for forming a semiconductor device

The present invention relates to a semiconductor device and a method for forming the same, and in particular to a memory device and a method for forming the same.

Memory can be mainly divided into volatile memory such as dynamic random access memory (DRAM) and non-volatile memory such as flash memory. Flash memory is widely used in various fields, such as consumer electronics, network communication equipment, automotive components, etc., due to its advantages such as easy programming, erasing, and long service life.

Split-gate is a type of flash memory that performs programming operations, such as by a source-side hot electron injection mechanism, and uses a floating gate and an erase gate to perform an erase operation based on poly-to-poly enhance tunneling, so that this type of flash memory has a higher programming/erasing efficiency.

However, with the advancement of technology, semiconductor components are constantly developing towards a "light, thin, short, and small" form factor. Therefore, how to improve the performance of flash memory components without increasing the size of the components is one of the research goals of researchers in this field.

The present invention provides a semiconductor device and a method for forming the same, which forms a floating gate into a rectangular shape so that the charge storage layer subsequently formed between the floating gate and the control gate has a good process margin. In this way, even under the premise that the size of the device continues to shrink, the formed charge storage layer has good uniformity in all aspects (such as shape, size, etc.), so that the semiconductor device has a good gate coupling ratio (GCR). On the other hand, the overlapping portion of the floating gate and the erase gate also has good uniformity due to the reduced variation of the overlapping offset, so the performance of the erase operation can be improved.

An embodiment of the present invention provides a method for forming a semiconductor device, comprising: forming a plurality of stacking patterns on a substrate, wherein each stacking pattern comprises a selection gate and a mask layer on the selection gate; forming a first dielectric material layer on the top surface and sidewalls of each stacking pattern; forming a floating gate pattern between two adjacent stacking patterns, wherein the floating gate The top surface of the pattern is lower than the top surface of the mask layer; a spacer is formed on the sidewalls of each stacked pattern; a portion of the floating gate pattern exposed by the spacer is removed to form a plurality of floating gates facing each other; and the spacer, a portion of the first dielectric material layer and the mask layer are removed to form a first dielectric layer between the selection gate and the floating gate.

In one embodiment of the present invention, the thickness of the mask layer in the direction perpendicular to the substrate is approximately equal to the thickness of the select gate.

In one embodiment of the present invention, the step of forming a floating gate pattern includes: after forming the first dielectric material layer, forming a floating gate material covering the stacked pattern and the first dielectric material layer on the substrate; removing the floating gate material above the top surface of the mask layer by a planarization process to form a floating gate material layer; removing a portion of the floating gate material layer to form a floating gate layer whose top surface is lower than the top surface of the mask layer; and patterning the floating gate layer to form a floating gate pattern between two adjacent stacked patterns.

In one embodiment of the present invention, the planarization process includes a chemical mechanical polishing process (CMP process), and removing the portion of the floating gate material layer includes an etch-back process.

In one embodiment of the present invention, the spacer includes a first portion facing each other and disposed on the gate pattern and a second portion opposite to the first portion and disposed on the substrate. The bottom surface of the first portion is higher than the bottom surface of the second portion.

In one embodiment of the present invention, the method for forming a semiconductor device further includes: forming a charge storage layer in an opening defined by two adjacent floating gates and a substrate; forming a control gate on the charge storage layer; forming an erase gate material covering the select gate, the first dielectric layer, the floating gate, the charge storage layer and the control gate on the substrate; and patterning the erase gate material to form a plurality of erase gates, the erase gates being respectively disposed at opposite sides of the control gate and above the floating gate and the select gate.

In one embodiment of the present invention, the method for forming a semiconductor device further includes: before forming an erase gate material, forming a second dielectric layer on a select gate, a first dielectric layer, a floating gate, a charge storage layer and a control gate, wherein the second dielectric layer separates the erase gate material from the select gate, the first dielectric layer, the floating gate, the charge storage layer and the control gate.

In one embodiment of the present invention, the step of forming a control gate includes a planarization process.

The present invention provides a semiconductor device, which includes a plurality of selection gates, a control gate, a plurality of floating gates, a plurality of erase gates and a charge storage layer. The selection gate is arranged on a substrate. The control gate is arranged on the substrate and between the selection gates. The floating gate is arranged on the substrate and between the selection gate and the control gate, wherein the floating gate is rectangular. The erase gate is arranged at opposite sides of the control gate and is located above the floating gate and the selection gate. The charge storage layer is arranged between the floating gate and the control gate.

In one embodiment of the present invention, the top surface of the floating gate and the top surface of the control gate are coplanar.

Based on the above, in the semiconductor device and the method for forming the semiconductor device of the above embodiment, the floating gate is formed into a rectangular shape so that the charge storage layer formed between the floating gate and the control gate has a good process margin. In this way, even if the size of the device continues to shrink, the formed charge storage layer has good uniformity in all aspects (such as shape, size, etc.), so that the semiconductor device has a good gate coupling ratio (GCR). On the other hand, the overlapping part of the floating gate and the erase gate also has good uniformity due to the reduction of the variation of the overlap offset, so the performance of the erase operation can be improved.

100: Base

102: Mixed area

110: Select gate

120: Mask layer

130: first dielectric material layer

132: First dielectric layer

140: Floating gate material

142: Floating gate material layer

144: Floating gate layer

146: Floating gate pattern

148: Floating gate

150: Gap wall

160: Charge storage material layer

162: Charge storage layer

170: Control gate material layer

172: Control gate layer

174: Control gate

180: Second dielectric layer

190: Erase gate material

192: Erase gate

PR1, PR2, PR3, PR4: Mask pattern

SP: Stacked Patterns

Figures 1 to 14 are cross-sectional schematic diagrams of a method for forming a semiconductor device according to an embodiment of the present invention.

The present invention is more fully described with reference to the drawings of the present embodiment. However, the present invention may be embodied in various forms and should not be limited to the embodiments described herein. The thickness of the layers and regions in the drawings are exaggerated for clarity. The same or similar reference numbers represent the same or similar elements, and the following paragraphs will not be repeated one by one.

It should be understood that when an element is referred to as being "on" or "connected to" another element, it may be directly on or connected to another element, or there may be an intermediate element. If an element is referred to as being "directly on" or "directly connected to" another element, there is no intermediate element. As used herein, "connection" may refer to physical and/or electrical connection, and "electrical connection" or "coupling" may refer to the presence of other elements between two elements. "Electrical connection" as used herein may include physical connection (e.g., wired connection) and physical disconnection (e.g., wireless connection).

As used herein, "approximately", "approximately" or "substantially" includes the values mentioned and the average value within an acceptable deviation range of a specific value that can be determined by a person of ordinary skill in the art, taking into account the measurement in question and the specific amount of error associated with the measurement (i.e., the limitations of the measurement system). For example, "approximately" can mean within one or more standard deviations of the value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, "approximately", "approximately" or "substantially" as used herein can select a more acceptable deviation range or standard deviation based on the optical properties, etching properties or other properties, and can apply to all properties without using one standard deviation.

The terms used herein are intended to illustrate exemplary embodiments only and are not intended to limit the present disclosure. In this context, the singular includes the plural unless otherwise explained in the context.

Figures 1 to 14 are cross-sectional schematic diagrams of a method for forming a semiconductor device according to an embodiment of the present invention.

First, referring to FIG. 1 , a plurality of stacking patterns SP are formed on a substrate 100. Each stacking pattern SP includes a selection gate 110 and a mask layer 120 on the selection gate 110. In some embodiments, the stacking pattern SP may be formed by the following steps. First, a selection gate material layer (not shown) and a mask material layer (not shown) are sequentially formed on the substrate 100. Then, the selection gate material layer and the mask material layer are patterned by a mask pattern PR1 to form a stacking pattern SP including the selection gate 110 and the mask layer 120. In some embodiments, the mask pattern PR1 may include a photoresist material. Then, after the stacking pattern SP is formed, the mask pattern PR1 is removed. In some embodiments, in a direction perpendicular to the surface of the substrate 100, the thickness of the mask layer 120 is approximately equal to the thickness of the select gate 110.

The substrate 100 may include a semiconductor substrate. The semiconductor material in the semiconductor substrate may include an elemental semiconductor, an alloy semiconductor, or a compound semiconductor. For example, the elemental semiconductor may include Si or Ge. The alloy semiconductor may include SiGe, SiGeC, etc. The compound semiconductor may include SiC, a III-V semiconductor material, or a II-VI semiconductor material. The III-V semiconductor material may include GaN, GaP, GaAs, AlN, AlP, AlAs, InN, InP, InAs, GaNP, GaNAs, GaPAs, AlNP, AlNAs, AlPAs, InNP, InNAs, InPAs, GaAlNP, GaAlNAs, GaAlPAs, GaInNP, GaInNAs, GaInPAs, InAlNP, InAlNAs, or InAlPAs. The II-VI Group semiconductor materials may include CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, HgS, HgSe, HgTe, CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdZnSe, CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe or HgZnSTe. The semiconductor material may be doped with a first conductivity type dopant or a second conductivity type dopant complementary to the first conductivity type. For example, the first conductivity type may be N-type and the second conductivity type may be P-type. The select gate 110 may include a material suitable as a select gate (e.g., polysilicon). The mask layer 120 may include an oxide (e.g., silicon oxide).

Next, referring to FIG. 1 and FIG. 2 , a first dielectric material layer 130 is formed on the top surface and sidewalls of each stacking pattern SP. The first dielectric material layer 130 may include an oxide (e.g., silicon oxide). In some embodiments, the mask layer 120 may include an oxide formed by a low-temperature process, and the first dielectric material layer 130 may include an oxide formed by a high-temperature process. That is, the density of the first dielectric material layer 130 is greater than the density of the mask layer 120.

Afterwards, a floating gate pattern 146 as shown in FIG. 5 is formed between two adjacent stacking patterns SP. In some embodiments, the floating gate pattern 146 as shown in FIG. 5 can be formed by the following steps.

Please continue to refer to FIG. 2. After forming the first dielectric material layer 130, a floating gate material 140 covering the stacking pattern SP and the first dielectric material layer 130 is formed on the substrate 100. In some embodiments, the floating gate material 140 may be formed by a deposition process, but is not limited thereto. The floating gate material 140 may include a material suitable as a floating gate (e.g., polysilicon).

Referring to FIG. 2 and FIG. 3 , the floating gate material 140 above the top surface of the mask layer 120 is removed by a planarization process to form a floating gate material layer 142. In some embodiments, the planarization process may include a chemical mechanical polishing process (CMP process). In some embodiments, the first dielectric material layer 130 may serve as a stop layer in the planarization process, that is, the surface of the first dielectric material layer 130 on the top surface of the stacking pattern SP may be flush with the top surface of the floating gate material layer 142.

3 and 4, a portion of the floating gate material layer 142 is removed to form a floating gate layer 144 whose top surface is lower than the top surface of the mask layer 120. In some embodiments, removing the portion of the floating gate material layer 142 includes an etch-back process. In some embodiments, the top surface of the floating gate layer 144 is lower than the top surface of the mask layer 120. In some embodiments, the top surface of the floating gate layer 144 is higher than the top surface of the selection gate 110.

Afterwards, referring to FIG. 4 and FIG. 5 , the floating gate layer 144 is patterned to form a floating gate pattern 146 between two adjacent stacking patterns SP. In some embodiments, the floating gate layer 144 may be patterned through a mask pattern PR2 to form a floating gate pattern 146. In some embodiments, the mask pattern PR2 may include a photoresist material. Afterwards, the mask pattern PR2 is removed after the floating gate pattern 146 is formed. In some embodiments, the top surface of the floating gate pattern 146 is lower than the top surface of the mask layer 120.

Then, referring to FIG. 5 and FIG. 6 , a spacer 150 is formed on the sidewall of each stacking pattern SP. In some embodiments, the spacer 150 may include a first portion facing each other and disposed on the floating gate pattern 146 and a second portion opposite to the first portion and disposed on the substrate 100. In some embodiments, the bottom surface of the first portion of the spacer 150 is higher than the bottom surface of the second portion of the spacer 150. In some embodiments, the shape of the first portion of the spacer 150 is different from the shape of the second portion of the spacer 150. The spacer 150 may include a nitride (e.g., silicon nitride).

6 and 7, the portion of the floating gate pattern 146 exposed by the spacer 150 is removed to form a plurality of floating gates 148 facing each other. Then, the substrate 100 exposed by the floating gate 148 is doped to form a doped region 102. Then, referring to FIG. 7 and 8, the spacer 150, a portion of the first dielectric material layer 130, and the mask layer 120 are removed to form a first dielectric layer 132 between the select gate 110 and the floating gate 148. In this way, the floating gate 148 can be formed into a rectangle as shown in FIG. 8, so that the charge storage layer (such as the charge storage layer 162 shown in FIG. 12 to FIG. 14) formed between the floating gate 148 and the control gate (such as the control gate 174 shown in FIG. 11 to FIG. 14) has a good process margin. In this way, even if the size of the device continues to shrink, the formed charge storage layer has good uniformity in various aspects (such as shape, size, etc.), so that the semiconductor device has a good gate coupling ratio (GCR). On the other hand, the overlapping portion of the floating gate 148 and the erase gate (such as the erase gate 192 shown in FIGS. 12 to 14 ) also has good uniformity due to the reduced variation of the overlapping offset, thereby improving the performance of the erase operation.

Next, a charge storage layer (such as the charge storage layer 162 shown in FIGS. 12-14 ) is formed in the opening defined by the two adjacent floating gates 148 and the substrate 100. Then, a control gate (such as the control gate 174 shown in FIGS. 11-14 ) is formed on the charge storage layer. The charge storage layer 162 may include an oxide-nitride-oxide (ONO) composite layer. The control gate 174 may include a material suitable as a control gate (such as polysilicon). In some embodiments, the charge storage layer 162 and the control gate 174 may be formed by the following steps.

First, referring to FIG8 and FIG9, a charge storage material layer 160 is formed in the opening defined by two adjacent floating gates 148 and the substrate 100, wherein the charge storage material layer 160 also extends to cover the top and side walls of the floating gate 148, the top of the first dielectric layer 132, and the top and side walls of the selection gate 110. Then, a control gate material layer 170 is formed on the charge storage material layer 160. As shown in FIG9, the charge storage material layer 160 can be formed between the control gate material layer 170 and the selection gate 110, the first dielectric layer 132, and the floating gate 148.

Next, referring to FIG. 9 and FIG. 10 , the control gate material layer 170 is subjected to a planarization process to form a control gate layer 172. In some embodiments, the planarization process may include a chemical mechanical polishing process (CMP process). In some embodiments, the charge storage material layer 160 may serve as a stop layer in the planarization process, that is, the surface of the charge storage material layer 160 on the top surface of the floating gate 148 may be flush with the top surface of the control gate layer 172.

Then, referring to FIG. 10 and FIG. 11 , the control gate layer 172 is patterned to form the control gate 174. In some embodiments, the control gate layer 172 may be patterned by a mask pattern PR3 to form the control gate 174. In some embodiments, the mask pattern PR3 may include a photoresist material. Then, after the control gate 174 is formed, the mask pattern PR3 is removed. Since the floating gate 148 is formed in a rectangular shape, the control gate 174 filled in the opening defined by the two adjacent floating gates 148 and the substrate 100 is also formed in a rectangular shape.

11 and 12 , a portion of the charge storage material layer 160 is removed to form a charge storage layer 162 in the opening defined by the two adjacent floating gates 148 and the substrate 100. As shown in FIG12 , the charge storage layer 162 is formed between the control gate 174 and the floating gate 148, and at least based on the manufacturing process described above, the charge storage layer 162 formed between the floating gate 148 and the control gate 174 can have a good process margin. In this way, even if the size of the device continues to shrink, the charge storage layer 162 formed has good uniformity in all aspects (such as shape, size, etc.), so that the semiconductor device has a good gate coupling ratio (GCR). In some embodiments, the top surface of the floating gate 148 and the top surface of the control gate 174 can be coplanar.

Next, referring to FIG. 12 and FIG. 13 , before forming the erase gate material 190, a second dielectric layer 180 is formed on the select gate 110, the first dielectric layer 132, the floating gate 148, the charge storage layer 162, and the control gate 174. In some embodiments, the second dielectric layer 180 may be formed on the top surface of the control gate 174, the top surface of the charge storage layer 162, the top surface and sidewalls of the floating gate 148, the top surface of the first dielectric layer 132, and the top surface and sidewalls of the select gate 110. The second dielectric layer 180 may include an oxide (e.g., silicon oxide).

Then, referring to FIG. 12 and FIG. 13 , an erase gate material 190 is formed on the substrate 100 to cover the select gate 110 , the first dielectric layer 132 , the floating gate 148 , the charge storage layer 162 , and the control gate 174 . The second dielectric layer 180 may be formed between the erase gate material 190 and the select gate 110, the first dielectric layer 132, the floating gate 148, the charge storage layer 162, and the control gate 174 to separate the erase gate material 190 from the select gate 110, the first dielectric layer 132, the floating gate 148, the charge storage layer 162, and the control gate 174. In some embodiments, the erase gate material 190 may include a material suitable as an erase gate (e.g., polysilicon).

Then, referring to FIG. 13 and FIG. 14 , the erase gate material 190 is patterned to form a plurality of erase gates 192. The erase gates 192 are respectively disposed at opposite sides of the control gate 174 and are located above the floating gate 148 and the selection gate 110. In some embodiments, the erase gate material 190 may be patterned by a mask pattern PR4 to form the erase gate 192. In some embodiments, the mask pattern PR4 may include a photoresist material. In some embodiments, the second dielectric layer 180 may serve as a stop layer in the above-mentioned patterning process. Then, after the erase gate 192 is formed, the mask pattern PR4 is removed.

At least based on the manufacturing process described above, the overlapping portion of the floating gate 148 and the erase gate 192 can have good uniformity due to the reduced variation of the overlapping offset, thus improving the performance of the erase operation.

Below, a semiconductor device according to an embodiment of the present invention will be described by way of example using FIG. 14. In addition, although the manufacturing method of the semiconductor device according to an embodiment of the present invention is described using the above-mentioned manufacturing method as an example, the manufacturing method of the semiconductor device according to the present invention is not limited thereto.

14 , the semiconductor device includes a plurality of select gates 110, a control gate 174, a plurality of floating gates 148, a plurality of erase gates 192, and a charge storage layer 162. The select gate 110 is disposed on a substrate 100. The control gate 174 is disposed on the substrate 100 and between the select gates 110. The floating gate 148 is disposed on the substrate 100 and between the select gate 110 and the control gate 174, wherein the floating gate 148 is rectangular. The erase gate 192 is disposed at opposite sides of the control gate 174 and above the floating gate 148 and the select gate 110. The charge storage layer 162 is disposed between the floating gate 148 and the control gate 174. In some embodiments, the top surface of the floating gate 148 is coplanar with the top surface of the control gate 174.

In summary, in the semiconductor device and its formation method of the above-mentioned embodiment, the floating gate is formed into a rectangular shape so that the charge storage layer subsequently formed between the floating gate and the control gate has a good process margin. In this way, even under the premise of the continuous reduction of the device size, the formed charge storage layer has good uniformity in various aspects (such as shape, size, etc.), so that the semiconductor device has a good gate coupling ratio (GCR). On the other hand, the overlapping part of the floating gate and the erase gate also has good uniformity due to the reduction of the variation of the overlap offset, so the performance of the erase operation can be improved.

100: Base

102: Mixed area

110: Select gate

132: First dielectric layer

148: Floating gate

162: Charge storage layer

174: Control gate

180: Second dielectric layer

192: Erase gate

PR4: Mask pattern

Claims (8)

A method for forming a semiconductor device comprises: forming a plurality of stacked patterns on a substrate, wherein each stacked pattern comprises a select gate and a mask layer on the select gate; forming a first dielectric material layer on the top surface and sidewalls of each stacked pattern; forming a floating gate pattern between two adjacent stacked patterns, wherein the top surface of the floating gate pattern is lower than the mask layer; The top surface of the curtain layer; forming a spacer on the side wall of each of the stacked patterns; removing the portion of the floating gate pattern exposed by the spacer to form a plurality of floating gates facing each other; and removing the spacer, a portion of the first dielectric material layer and the mask layer to form a first dielectric layer between the selection gate and the floating gate. A method for forming a semiconductor device as described in claim 1, wherein the thickness of the mask layer in a direction perpendicular to the substrate is approximately equal to the thickness of the selection gate. The method for forming a semiconductor device as described in claim 1, wherein the step of forming the floating gate pattern includes: after forming the first dielectric material layer, forming a floating gate material covering the stacking pattern and the first dielectric material layer on the substrate; removing the floating gate material above the top surface of the mask layer by a planarization process to form a floating gate material layer; removing a portion of the floating gate material layer to form a floating gate layer whose top surface is lower than the top surface of the mask layer; and patterning the floating gate layer to form the floating gate pattern between two adjacent stacking patterns. A method for forming a semiconductor device as described in claim 3, wherein the planarization process includes a chemical mechanical polishing process (CMP process), and removing the portion of the floating gate material layer includes an etch-back process. A method for forming a semiconductor device as described in claim 1, wherein the spacer includes a first portion facing each other and disposed on the gate pattern and a second portion opposite to the first portion and disposed on the substrate, and the bottom surface of the first portion is higher than the bottom surface of the second portion. The method for forming a semiconductor device as described in claim 1 further includes: forming a charge storage layer in an opening defined by two adjacent floating gates and the substrate; forming a control gate on the charge storage layer; forming an erase gate material on the substrate to cover the select gate, the first dielectric layer, the floating gate, the charge storage layer and the control gate; and patterning the erase gate material to form a plurality of erase gates, the erase gates being respectively disposed at opposite sides of the control gate and above the floating gate and the select gate. The method for forming a semiconductor device as described in claim 6 further includes: before forming the erase gate material, forming a second dielectric layer on the select gate, the first dielectric layer, the floating gate, the charge storage layer and the control gate, wherein the second dielectric layer separates the erase gate material from the select gate, the first dielectric layer, the floating gate, the charge storage layer and the control gate. A method for forming a semiconductor device as described in claim 6, wherein the step of forming the control gate includes a planarization process.

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