TWI692015B - Transistor device - Google Patents

Abstract

A transistor device disposed on a substrate and including a semiconductor layer, a first gate, a second gate and two source drain electrode is provided. The semiconductor layer is disposed on the substrate and has a channel region, two lightly doped regions and two source drain regions. Each of the two lightly doped regions has a first boundary adjoined to the channel region and a second boundary adjoined to one of the source drain regions. The first gate extends crossing over the channel region of the semiconductor layer, wherein an edge of the first gate aligns with the first boundary. The second gate stacks on the first gate and is in contact with the first gate, wherein in the thickness direction, the second gate overlaps the two lightly doped regions. The two source drain electrodes are respectively in contact with the two source drain regions.

Description

Transistor device

The present invention relates to an electronic component, and particularly relates to a transistor device.

Transistor devices use semiconductor layers to implement switching and switching functions, and are an indispensable device and/or component in various electronic products. Among various transistor devices, low-temperature polysilicon thin film transistors using polycrystalline silicon semiconductors fabricated at low temperatures as transistor channels have been widely used in display panels due to their superior carrier mobility. Self-aligned top-gate low-temperature polysilicon thin film transistors are widely used as low-temperature polysilicon thin film transistors because they can precisely define the location of the channel area.

In the manufacturing process of self-aligned top-gate low-temperature polysilicon thin film transistors, the gate located above the polysilicon semiconductor can be used as a mask for the doping process to form light doping on both sides of the area where the polysilicon semiconductor is shielded by the gate The area where the polysilicon semiconductor is shielded by the gate constitutes the channel area. The lightly doped regions on both sides of the channel region help to suppress the thermoelectronic effect and improve the performance of the self-aligned top-gate low-temperature polycrystalline silicon thin film transistor.

The invention provides a transistor device, which helps to improve the performance of the transistor.

The transistor device of the present invention is disposed on a substrate and includes a semiconductor layer, a first gate, a second gate, and two source drains. The semiconductor layer is disposed on the substrate and has a channel region, two lightly doped regions, and two source drain regions. Each of the two lightly doped regions has a first boundary adjacent to the channel region and a second boundary adjacent to one of the two source drain regions. The first gate extends across the channel region of the semiconductor layer, where the boundary of the first gate is aligned with the first junction. The second gate is stacked on the first gate and contacts the first gate, wherein the second gate overlaps two lightly doped regions in the thickness direction. The two source drains respectively contact the two source drain regions of the semiconductor layer.

In an embodiment of the invention, the above transistor device further includes a first gate insulating layer. The first gate insulating layer is disposed on the substrate and is located between the semiconductor layer and the first gate electrode.

In an embodiment of the invention, the above transistor device further includes a second gate insulating layer. The second gate insulating layer is disposed on the substrate, and the first gate insulating layer is located between the second gate insulating layer and the substrate.

In an embodiment of the invention, both the first gate insulating layer and the second gate insulating layer are located between the second gate electrode and the semiconductor layer.

In an embodiment of the invention, the first gate insulating layer has a first source drain opening, and the second gate insulating layer has a second source drain opening. The first source drain opening communicates with the second source drain opening to expose one of the two source drain regions, and one of the two source drains extends in the first source drain opening and the second source drain opening Contact One of the two source drain regions.

In an embodiment of the invention, the above-mentioned second gate insulating layer has a gate opening. The gate opening exposes the first gate, and the second gate extends in the gate opening to contact the first gate.

In an embodiment of the invention, the width of the above-mentioned gate opening extends beyond the width of the first gate.

In an embodiment of the invention, the above-mentioned second gate contacts the top surface and the side wall of the first gate in the gate opening.

In an embodiment of the invention, the width of the gate opening is smaller than the width of the first gate.

In an embodiment of the invention, the sidewall of the second gate insulating layer forming the gate opening is an inclined sidewall.

In an embodiment of the invention, the farther away from the first gate insulating layer, the larger the width of the gate opening of the second gate insulating layer.

In an embodiment of the invention, the closer to the two source drains, the greater the distance between the second gate and the semiconductor layer.

In an embodiment of the invention, the above-mentioned second gate and the two source drains are formed by the same film layer.

In an embodiment of the invention, each of the above two source drains is separated from the second gate by a distance, and the distance is greater than 2 microns.

In an embodiment of the invention, the second gate described above blocks the first junction.

In an embodiment of the invention, the two lightly doped regions each include a heavy The overlapped portion overlapping the second gate and the non-overlapping portion not overlapping the second gate.

In an embodiment of the present invention, the above-mentioned overlapping portion extends from the first boundary to the non-overlapping portion with an extension length greater than 0.3 microns.

In an embodiment of the invention, the above non-overlapping portion extends from the overlapping portion to the second boundary with an extension length greater than 0.3 microns.

In an embodiment of the invention, the doping concentration of the two lightly doped regions is higher than that of the channel region.

In an embodiment of the invention, the doping concentration of the two source drain regions is higher than that of the two lightly doped regions.

Based on the above, the transistor device of the embodiment of the present invention has double gates stacked together, wherein the junction of the channel region and the lightly doped region in the semiconductor layer is aligned with the boundary of the first gate, and the second gate is The lightly doped regions partially overlap. In this way, the transistor device of the embodiment of the present invention has lower off-leakage current and has ideal operating performance.

In order to make the above-mentioned features and advantages of the present invention more obvious and understandable, the embodiments are specifically described below in conjunction with the accompanying drawings for detailed description as follows.

10: substrate

100: Transistor device

110: Semiconductor layer

112: Passage area

114A, 114B: lightly doped region

116A, 116B: source-drain region

120: first gate

120S: Side wall

120T: top surface

130: second gate

140, 150: source drain

160: first gate insulating layer

162A, 162B: the first source drain opening

170: second gate insulating layer

170W: Side wall

172A, 172B: second source drain opening

174, 274: gate opening

B114A, B114B: the first junction

C114A, C114B: the second junction

d, y130: distance

LDD1: overlapping part

LDD2: Non-overlapping parts

TD: thickness direction

W120, W174, W274: width

WLDD1, WLDD2: extension length

FIG. 1 is a schematic top view of a transistor device according to an embodiment of the invention.

2 is a schematic cross-sectional view of a transistor device according to an embodiment of the invention.

3 is a schematic cross-sectional view of a transistor device according to another embodiment of the invention. .

FIG. 1 is a schematic top view of a transistor device according to an embodiment of the invention. 2 is a schematic cross-sectional view of a transistor device according to an embodiment of the invention. The cross-sectional view of FIG. 2 can be represented as an embodiment of the cross-sectional structure of the transistor device 100, so the same and similar components in FIGS. 1 and 2 will be marked with the same element symbols. The transistor device 100 of FIGS. 1 and 2 is disposed on the substrate 10 and includes a semiconductor layer 110, a first gate 120, a second gate 130, a source drain 140 and a source drain 150. The contours of the semiconductor layer 110, the first gate 120, the second gate 130, the source drain 140, and the source drain 150 presented in FIG. 1 can be regarded as the vertical projection contours of these components when projected vertically on the substrate 10. Therefore, the overlapping relationship and relative position between components in the upper view can be regarded as the relative relationship of the vertical projection of these components.

The semiconductor layer 110 has a U-shaped pattern in the top view of this embodiment, but it is not limited thereto. Specifically, in FIGS. 1 and 2, the semiconductor layer 110 can be divided into a channel region 112, two lightly doped regions 114A and 114B, and two source-drain regions 116A and 116B. The two lightly doped regions 114A and 114B each extend between one of the two source drain regions 116A and 116B and the channel region 112. For example, the lightly doped region 114A is located between the source and drain regions 116A and the channel region 112, and the lightly doped region 114B is located between the source and drain regions 116B and the channel region 112. In this embodiment, each of the two lightly doped regions 114A and 114B has first junctions B114A and B114B adjacent to the channel region 112, and each of the two lightly doped regions 114A and 114B has two sources The second junctions C114A and C114B adjacent to the polar regions 116A and 116B. First junction B114A The boundary B114B and the second boundary C114A and C114B can be determined by the doping concentration of the semiconductor layer 110, and may not have a physical boundary structure.

Specifically, the semiconductor layer 110 may be a polycrystalline silicon semiconductor or an oxide semiconductor. The lightly doped regions 114A and 114B have a higher doping concentration than the channel region 112, and the source and drain regions 116A and 116B also have a higher doping concentration than the channel region 112. In addition, the source and drain regions 116A and 116B may have a higher doping concentration than the lightly doped regions 114A and 114B. That is to say, the concentration of the semiconductor layer 110 subjected to doping may gradually increase outward from the middle section, but not limited to this. In addition, the doping substance subjected to the doping of the semiconductor layer 110 may be determined according to the required function of the transistor device 100, wherein the doping substance may include a P-type doping substance, an N-type doping substance or a combination of different types of doping substances .

The first gate 120 is shown in an extended pattern in FIG. 1, but it is not limited thereto. The first gate 120 extends across the channel region 112 of the semiconductor layer 110, that is, the channel region 112 overlaps the first gate 120 in the thickness direction TD. Specifically, the first boundary B114A of the lightly doped region 114A and the first boundary B114B of the lightly doped region 114B are aligned with the boundary of the first gate 120. In the process of manufacturing the transistor device 100, after the semiconductor layer 110 and the first gate 120 are sequentially formed on the substrate 10, a light doping process may be performed. At this time, since the channel region 112 in the semiconductor layer 110 is shielded by the first gate 120, it is not doped. At the same time, a portion of the semiconductor layer 110 beside the channel region 112 that is not shielded by the first gate 120 is doped, so that the two lightly doped regions 114A and 114B beside the channel region 112 are formed. In other words, in this embodiment, the channel region 112 of the transistor device 100 is self-aligned to the first gate 120, which can be regarded as a portion of the semiconductor layer 110 overlapping the first gate 120 in the thickness direction TD. The thickness direction TD referred to herein can be regarded as the direction of the thickness of the substrate 10, which is also substantially the same as the direction of the thickness of each film layer.

The second gate 130 overlaps the first gate 120 and the second gate 130 overlaps a larger area of the semiconductor layer 110 in the thickness direction than the first gate 120. For example, the second gate 130 overlaps both the channel region 112 and part of the lightly doped region 114A and part of the lightly doped region 114B in the thickness direction TD. In other words, in this embodiment, the second gate 130 shields the first junction B114A of the lightly doped region 114A and the first junction B114B of the lightly doped region 114B. However, the second boundary C114A of the lightly doped region 114A and the second boundary C114B of the lightly doped region 114B are located outside the second gate 130 and are not blocked by the second gate 130. That is, the two lightly doped regions 114A and 114B each include an overlapping portion LDD1 overlapping the second gate 130 and a non-overlapping portion LDD2 not overlapping the second gate 130. In some embodiments, the overlapping portion LDD1 extends from the first boundary B114A (or B114B) to the non-overlapping portion LDD2 with an extension length greater than 0.3 microns. In some embodiments, the non-overlapping portion LDD2 extends from the overlapping portion LDD1 to the second junction C114A (or C114B) with an extension length WLDD2 greater than 0.3 microns.

The two source drains 140 and 150 may respectively contact the two source drain regions 116A and 116B of the semiconductor layer 110, wherein the source drain 140 may contact the source drain region 116A and the source drain 150 may contact the source drain region 116B. In addition, neither the source drain 140 nor the source drain 150 overlaps the second gate 130. In some embodiments, the source drain 140, the source drain 150, and the second gate 130 are made of the same film layer. In other words, in manufacturing the transistor device 100 In this case, it can be patterned from the same conductive layer. In order to achieve the required electrical transmission path, the source drain 140 and the source drain 150 are each separated from the second gate 130 by a distance d. The distance d is greater than 2 microns in some embodiments, but in other embodiments, the distance d may be sufficient to keep the second gate 130 from electrically connecting the source drain 140 and the source drain 150, which can be based on Process limits.

In this embodiment, after the first gate 120 is fabricated on the substrate 10, the material of the second gate 130 is fabricated on the substrate 10. Therefore, the first gate 120 and the second gate 130 are electrodes composed of different layers. In some embodiments, the first gate 120 and the second gate 130 may be made of different materials, or may be made of the same material. When the first gate 120 and the second gate 130 are made of the same material, since the two electrodes are composed of different film layers, there is a physical junction structure between the two electrodes that is not integrally formed.

In this embodiment, the lightly doped region 114A and the lightly doped region 114B each include an overlapping portion LDD1 overlapping the second gate 130 and a non-overlapping portion LDD2 not overlapping the second gate 130. When the transistor device 100 is turned off, the first gate 120 and the second gate 130 are input with a turn-off voltage, which blocks or suppresses the carrier migration ability in the channel region 112. At this time, the overlapping portion LDD1 is also affected by the electric field formed by the second gate 130 and has poor carrier mobility. In this way, although the overlapping portions LDD1 of the lightly doped region 114A and the lightly doped region 114B are lightly doped, when the transistor device 100 is turned off, it helps to suppress leakage current and improve the performance. When the transistor device 100 is turned on, the first gate 120 and the second gate 130 are input with the turn-on voltage, thereby improving the carrier mobility of the channel region 112. At this time, the lightly doped regions 114A and 114B have their respective The non-overlapping portion LDD2 is not easily affected by the electric field formed by the second gate 130. Therefore, the non-overlapping portion LDD2 of the lightly doped region 114A and the lightly doped region 114B helps to suppress the hot electron effect and provide the function of the lightly doped region in the existing design. Therefore, the transistor device 100 of the present embodiment can have ideal operation performance. In this embodiment, although the overlapping portion LDD1 and the non-overlapping portion LDD2 have the same or similar doping concentration, they can provide different because one overlaps the second gate 130 and the other does not overlap the second gate 130. Degree of carrier transmission characteristics, to enhance the performance of the transistor device 100.

As can be seen from FIG. 2, the transistor device 100 disposed on the substrate 10 includes a first gate insulating layer in addition to the semiconductor layer 110, the first gate 120, the second gate 130, the source drain 140 and the source drain 150 160与第一门 insulation层170。 160 and the second gate insulating layer 170. The first gate insulating layer 160 and the second gate insulating layer 170 are used to isolate conductive members to avoid unnecessary electrical connection between the conductive members.

The first gate insulating layer 160 and the second gate insulating layer 170 are both disposed on the substrate 10, and the first gate insulating layer 160 is located between the second gate insulating layer 170 and the substrate 10. In this embodiment, the first gate insulating layer 160 is stacked on the semiconductor layer 110, and the first gate 120 is stacked on the first gate insulating layer 160. Therefore, the first gate insulating layer 160 is located between the semiconductor layer 110 and the first gate 120 to avoid direct electrical connection between the two components. In addition, the second gate insulating layer 170 is stacked on the first gate insulating layer 160, and the source drain 140, the source drain 150, and the second gate 130 are stacked on the second gate insulating layer 170. Therefore, the first gate insulating layer 160 and the second gate insulating layer 170 are both located between the second gate 130 and the semiconductor layer 110 and are also located between the source and drain electrodes 140 and 150 and Between the semiconductor layers 110.

In order for source drain 140 and source drain 150 to contact semiconductor layer 110, first gate insulating layer 160 has first source drain openings 162A and 162B, and second gate insulating layer 170 has second source drain openings 172A and 172B . The first source-drain opening 162A and the second source-drain opening 172A communicate with each other to penetrate the first gate insulating layer 160 and the second gate insulating layer 170 and expose the source-drain region 116A so as to extend over the first source-drain opening 162A and source drain 140 in second source-drain opening 172A contact source-drain region 116A. The first source-drain opening 162B and the second source-drain opening 172B communicate with each other, penetrate the first gate insulating layer 160 and the second gate insulating layer 170 and expose the source-drain region 116B so as to extend over the first source-drain opening 162B contacts the source drain region 116B in the second source-drain opening 172B.

In addition, in this embodiment, the second gate insulating layer 170 also has a gate opening 174. The gate opening 174 exposes the first gate 120, and the second gate 130 extends in the gate opening 174 to contact the first gate 120. In other words, the gate opening 174 is an opening corresponding to the region where the first gate 120 is located and penetrates the second gate insulating layer 170. In the section of FIG. 2, the width W174 of the gate opening 174 extends beyond the width W120 of the first gate 120. Therefore, the gate opening 174 exposes the top surface 120T and the side wall 120S of the first gate 120, and the second gate 130 can cover the top surface 120T and the side wall 120S of the first gate 120 in the gate opening 174 to increase the first The contact area of the gate 120 and the second gate 130.

In this embodiment, the sidewall 170W of the second gate insulating layer 170 forming the gate opening 174 is an inclined sidewall, so that the width W174 of the gate opening 174 is unequal Wide design. For example, the farther away from the first gate insulating layer 160, the larger the width W174 of the gate opening 174. In this way, in the thickness direction TD, the distance y130 between the second gate 130 and the semiconductor layer 110 may also be arranged at an unequal distance. For example, the closer to the source drain 140 or 150, the greater the distance y130 between the second gate 130 and the semiconductor layer 110. In addition, the first source-drain opening 162A and the second source-drain opening 172A may also have a non-equal width design.

Since the distance y130 between the second gate 130 and the semiconductor layer 110 is not equidistant, the electric field of the second gate 130 acting on the semiconductor layer 110 will also change accordingly. In particular, the portion of the second gate 130 extending beyond the first gate 120 may provide a gradient electric field to the lightly doped regions 114A and 114B of the semiconductor layer 110, such that the closer to the channel region 112, the lightly doped region 114A and 114B receives more electric field. In this way, when the transistor device 100 is in the off state, the situation of the leakage current can be more effectively controlled to achieve the desired performance.

3 is a schematic cross-sectional view of a transistor device according to another embodiment of the invention. The cross-sectional view of FIG. 3 can be represented as another possible implementation of the cross-sectional structure of the transistor device 100, so the same and similar components in FIG. 1 and FIG. 3 will be marked with the same element symbols. As can be seen from FIG. 3, the transistor device 100 disposed on the substrate 10 includes a first gate insulating layer in addition to the semiconductor layer 110, the first gate 120, the second gate 130, the source drain 140 and the source drain 150 160与第一门 insulation层170。 160 and the second gate insulating layer 170. The first gate insulating layer 160 and the second gate insulating layer 170 are used to isolate conductive members to avoid unnecessary electrical connection between the conductive members. Specifically, the cross section shown in FIG. 3 is similar to the cross section shown in FIG. 2, and the difference between the two embodiments is mainly The design of the gate opening 274 of the second gate insulating layer 170.

As can be seen from FIG. 3, the gate opening 274 of the second gate insulating layer 170 of this embodiment has a non-equal width W274, and the farther away from the first gate 120, the larger the width W274. At the same time, the width W120 of the first gate 120 is greater than the minimum of the width W274. That is to say, the gate opening 274 of this embodiment only exposes the top surface 120T of the first gate 120, and the second gate 130 extends from the second gate insulating layer 170 into the gate opening 274 to contact the first gate The top surface 120T of the pole 120. The side wall 170W of the second gate insulating layer 170 forming the gate opening 274 is also an inclined side wall. As such, the closer to the source drain 140 or 150, the greater the distance y130 between the second gate 130 and the semiconductor layer 110.

Similar to the foregoing embodiment, the lightly doped regions 114A and 114B in the semiconductor layer 110 each include an overlapping portion LDD1 overlapping the second gate 130 in the thickness direction TD and a non-overlapping portion LDD2 not overlapping the second gate 130. Although the overlapping portion LDD1 and the non-overlapping portion LDD2 have the same or similar doping concentration, because one overlaps the second gate 130 and the other does not overlap the second gate 130, it is provided when the transistor device 100 operates Different carrier migration capabilities, thereby helping to suppress the leakage current phenomenon in the off state and the hot electron effect in the on state.

The transistor device 100 of the foregoing embodiment can be applied to a display panel as a switching element or an active element. For example, the display panel may include an active device array composed of multiple scan lines, multiple data lines, and multiple transistor structures. In practical applications, the first gate 120 can be connected to the scan line, and one of the source drains 140 and 150 can be connected to the data line. In addition, the other of the source and drain electrodes 140 and 150 is used to connect to the pixel electrode that is expected to drive the display medium. Therefore, in practical applications In the above, the first gate 120 may be a part of the scan line or a structure protruding from the scan line, and one of the source drains 140 and 150 may be a part of the data line or by data The structure is formed by protruding lines. In addition, a single transistor structure 100 can optionally have multiple channel regions 112 without being limited to having a single channel region 112.

In summary, the transistor device of the embodiment of the present invention has dual gates directly in contact with each other, and the expansion areas of the two gates are different. Therefore, the transistor device of the embodiment of the present invention can use the contour of one of the gates to define the channel region to form a self-aligned channel region. At the same time, the other gate covers part of the lightly doped region of the semiconductor layer to help suppress leakage current that may be generated in the off state. In addition, in the transistor device of the embodiment of the present invention, at least a portion of the lightly doped region does not overlap the gate, which helps to suppress the thermoelectron effect.

Although the present invention has been disclosed as above with examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to the scope defined in the appended patent application.

10: substrate 100: Transistor device 110: Semiconductor layer 112: Passage area 114A, 114B: lightly doped region 116A, 116B: source-drain region 120: first gate 120S: Side wall 120T: top surface 130: second gate 140, 150: source drain 160: first gate insulating layer 162A, 162B: first source drain opening 170: second gate insulating layer 170W: side wall 172A, 172B: second source drain opening 174: Gate opening B114A: The first junction C114A: The second junction d, y130: distance LDD1: overlapping part LDD2: Non-overlapping parts TD: thickness direction W120, W174: width WLDD1, WLDD2: extension length

Claims (19)

A transistor device is arranged on a substrate. The transistor device comprises: a semiconductor layer, which is arranged on the substrate and has a channel region, two lightly doped regions and two source drain regions, wherein each of the two lightly doped regions One has a first junction adjacent to the channel region and a second junction adjacent to one of the two source drain regions; a first gate extends the channel region across the semiconductor layer, wherein the first The boundary of the gate is aligned with the first junction; the second gate is stacked on the first gate and contacts the first gate, wherein the second gate overlaps the two lightly doped regions in the thickness direction; And two source drains, respectively contacting the two source drain regions of the semiconductor layer, wherein the closer to the two source drains, the greater the distance between the second gate and the semiconductor layer. The transistor device as described in item 1 of the scope of the patent application further includes a first gate insulating layer disposed on the substrate and located between the semiconductor layer and the first gate. The transistor device as described in item 2 of the patent application scope further includes a second gate insulating layer, the second gate insulating layer is disposed on the substrate, and the first gate insulating layer is located between the second gate insulating layer and the Between substrates. The transistor device as described in item 3 of the patent application range, wherein both the first gate insulating layer and the second gate insulating layer are located between the second gate electrode and the semiconductor layer. The transistor device of claim 3, wherein the first gate insulating layer has a first source drain opening, the second gate insulating layer has a second source drain opening, and the first source drain opening Communicating with the second source drain opening to expose one of the two source drain regions, and one of the two source drains extends in the first source drain opening and the second source drain opening to Contact one of the two source drain regions. The transistor device of claim 3, wherein the second gate insulating layer has a gate opening, the gate opening exposes the first gate, and the second gate extends in the gate opening To contact the first gate. A transistor device as described in item 6 of the patent application range, wherein the width of the gate opening extends beyond the width of the first gate. The transistor device as described in item 7 of the patent application range, wherein the second gate contacts the top surface and the side wall of the first gate in the gate opening. The transistor device as described in item 6 of the patent application range, wherein the width of the gate opening is smaller than the width of the first gate. The transistor device as described in item 6 of the patent application range, wherein the side wall of the second gate insulating layer forming the gate opening is an inclined side wall. The transistor device as described in item 6 of the patent application range, wherein the farther away from the first gate insulating layer, the larger the width of the gate opening of the second gate insulating layer. The transistor device as described in item 1 of the patent application range, wherein the second gate electrode and the two source drain electrodes are composed of the same film layer. The transistor device as described in item 1 of the patent application range, wherein each of the two source drains is separated from the second gate by a distance greater than 2 microns. The transistor device as described in item 1 of the patent application scope, wherein the second gate shields the first junction. The transistor device according to item 1 of the patent application scope, wherein the two lightly doped regions each include an overlapping portion overlapping the second gate and a non-overlapping portion not overlapping the second gate. The transistor device according to item 15 of the patent application scope, wherein the extension length of the overlapping portion extending from the first boundary to the non-overlapping portion is greater than 0.3 μm. The transistor device according to item 15 of the patent application scope, wherein the extension length of the non-overlapping portion extending from the overlapping portion to the second junction is greater than 0.3 μm. The transistor device as described in item 1 of the patent application range, wherein the doping concentration of the two lightly doped regions is higher than that of the channel region. The transistor device as described in item 1 of the patent application range, wherein the doping concentration of the two source drain regions is higher than that of the two lightly doped regions.

Images