TWI897312B - Power semiconductor device and manufacturing method of the same - Google Patents

Abstract

A power semiconductor device includes a drain metal ,a substrate located on the drain metal, an epitaxy layer located on the substrate, a gate structure, a source/drain doped region, a shielding region, a gate oxide layer, and a source metal located on the epitaxy layer. The epitaxy layer has a first conductive type. The gate structure is located in the epitaxy layer. The gate structure is asymmetrical along a lateral direction. The gate structure includes a first gate and a second gate, and the second gate is located above the first gate. The source/drain doped region is located in the epitaxy layer adjacent to a first side of the second gate. The shielding region is located in the epitaxy layer, at least surrounds the first gate, and has a second conductive type. The gate oxide layer is located between the gate structure and the epitaxy layer.

Description

Power semiconductor device and manufacturing method thereof

The present disclosure relates to a power semiconductor device, and more particularly to a power semiconductor device having a trench gate structure.

With advances in semiconductor technology, the applications of metal oxide semiconductor field-effect transistors (MOS FETs) are becoming increasingly widespread. Power semiconductors can be used as switches in electronic components. They are used in high-voltage and high-current device designs. The switching speed and on-resistance of power semiconductors are closely related to the design of their gate structures.

One technical aspect of the present disclosure is a power semiconductor device.

In one embodiment of the present disclosure, a power semiconductor device includes a drain metal, a base layer located on the drain metal, an epitaxial layer located on the base layer, a gate structure, a source/drain doped region, a shielding region, a gate oxide layer, and a source metal located on the epitaxial layer. The epitaxial layer has a first conductivity type. The gate structure is located in the epitaxial layer. The gate structure is laterally asymmetric. The gate structure includes a first gate and a second gate, and the second gate is located above the first gate. The source/drain doped region is located in the epitaxial layer adjacent to a first side of the second gate. The shielding region is located in the epitaxial layer and at least surrounds the first gate and has the second conductivity type. The gate oxide layer is located between the gate structure and the epitaxial layer.

Another technical aspect of the present disclosure is a method for manufacturing a semiconductor device.

In one embodiment of the present disclosure, a method for fabricating a power semiconductor device includes forming an epitaxial layer on a substrate layer, wherein the epitaxial layer has a first conductivity type; forming a first trench in the epitaxial layer, wherein the first trench has trench sidewalls; arranging the trench sidewalls to form a shielding region, wherein the shielding region has a second conductivity type and surrounds at least a lower portion of the trench sidewalls; forming a source/drain doped region in the epitaxial layer adjacent to an upper portion of the trench sidewalls; forming a second trench such that the second trench is laterally asymmetric; forming a gate oxide layer in the first trench and the second trench; and forming a gate structure in the first trench and the second trench.

In the above-mentioned embodiment, the semiconductor device with a trench gate structure makes the channel region vertical to increase the current density. The direction and angle of the channel region can be determined by the sidewalls of the trench that accommodates the second gate. By setting a shielding region, the strong electric field in the vertical power semiconductor device can be shielded. By setting gate oxide layers with different thicknesses and setting a split gate, the breakdown voltage can be increased. The present disclosure can integrate the steps of forming a channel region with a specific direction and angle, a gate oxide layer with different thicknesses, and a split gate to optimize the process of power semiconductor devices. The doping concentration and area size of the shielding region can be varied to adjust the on-resistance and breakdown voltage.

The following drawings illustrate various embodiments of the present invention. For the sake of clarity, many practical details are described in the following description. However, it should be understood that these practical details should not be used to limit the present invention.

FIG1 is a cross-sectional view of a power semiconductor device 100 according to an embodiment of the present disclosure. The power semiconductor device 100 includes a drain metal 110, a base layer 120, an epitaxial layer 130, a gate structure 140, a source/drain doped region 150, a shielding region 160, a gate oxide layer 170, and a source metal 180.

The base layer 120 is located on the drain metal 110, such as a silicon carbide (SiC) substrate. The epitaxial layer 130 is located on the base layer 120 and has a first conductivity type (N-type). The gate structure 140 is located in the epitaxial layer 130. For example, the power semiconductor device 100 in this embodiment is an N-type metal oxide semiconductor field effect transistor (MOSFET). The base layer 120 is an N-type heavily doped substrate (N+). The doping concentration of the epitaxial layer 130 is lower than the doping concentration of the base layer 120 (N-). The epitaxial layer 130 can serve as a drift region between the source S and the drain D.

The gate structure 140 is asymmetric in the lateral direction D1. It includes a first gate 142 and a second gate 144, with the second gate 144 positioned above the first gate 142. The first and second gates 142, 144 are separated from each other, forming a split gate. The second gate 144 serves as a gate poly, while the first gate 142 serves as a shielding electrode and is electrically connected to the source metal 180. The second width W2 of the second gate 144 is greater than the first width W1 of the first gate 142. A first center position C1 of the first gate 142 in the transverse direction D1 is offset from a second center position C2 of the second gate 144 in the transverse direction D1 .

The source/drain doped region 150 is located in the epitaxial layer 130 adjacent to the first side 1442 of the second gate 144. The source/drain doped region 150 includes a source region 152 having a first conductivity type (N+) and a well region 154 having a second conductivity type (P). The source region 152, the well region 154, and the second gate 144 form a channel region 156. In other words, the power semiconductor device 100 is a semiconductor device having a single-sided trench gate structure.

Shielding region 160 is located in epitaxial layer 130 and surrounds at least first gate 142. It has a second conductivity type (P+). Shielding region 160 includes a first shielding region 162, a second shielding region 164, and a third shielding region 166, which are connected to each other. Shielding region 160 is formed through a placement step. First shielding region 162 is formed in epitaxial layer 130 adjacent to first side 1422 of first gate 142, and second shielding region 164 is formed in epitaxial layer 130 adjacent to second side 1424 of first gate 142. First shielding region 162 is located below channel region 156. Third shielding region 166 is formed in epitaxial layer 130 at the bottom of first gate 142. In this embodiment, the second shielding region 164 extends into the epitaxial layer 130 adjacent to the second side 1444 of the second gate 144 , but the disclosure is not limited thereto.

A gate oxide layer 170 is located between the gate structure 140 and the epitaxial layer 130. A source metal 180 is located on the epitaxial layer 130. The gate oxide layer 170 includes a first gate oxide layer 172 and a second gate oxide layer 174. The first gate oxide layer 172 is located between the first shielding region 162, the second shielding region 164, the third shielding region 166, and the first gate 142, and between the epitaxial layer 130 adjacent to the second side 1444 of the second gate 144 and the second gate 144. The second gate oxide layer 174 is located between the source/drain doped region 150 and the first side 1442 of the second gate 144. A second thickness T2 of the second gate oxide layer 174 is less than a first thickness T1 of the first gate oxide layer 172.

Since the gate structure 140 is a trench structure, the channel region 156 is oriented vertically rather than horizontally, which increases the density of the gate structure 140 and improves the current density. By providing the shielding region 160, the strong electric field in the vertical power semiconductor device can be shielded.

The shielding area 160 may include a plurality of first shielding areas 162. The length and spacing of the first shielding areas 162 may be set according to actual needs to adjust the on-resistance and breakdown voltage of the power semiconductor device 100.

As shown in FIG. 1 , the first side 1442 of the second gate 144 is relatively protruding. Therefore, the direction and angle of the channel region 156 are determined by the trench sidewall 190 that accommodates the second gate 144. The trench sidewall 190 includes a first sidewall 192, a second sidewall 194, and a third sidewall 196. The first sidewall 192 is adjacent to the first side 1422 of the first gate 142. The third sidewall 196 is adjacent to the first side 1442 of the second gate 144. The second sidewall 194 is adjacent to both the second side 1424 of the first gate 142 and the second side 1444 of the second gate 144. The third sidewall 196 is opposite the second sidewall 194. The first sidewall 192 and the second sidewall 194 are opposite each other. A curved sidewall 198 is defined between the first sidewall 192 and the third sidewall 196. The first sidewall 192 corresponds to the lower portion of the trench sidewall 190, while the third sidewall 196 corresponds to the upper portion of the trench sidewall 190. The second sidewall 194 covers both the upper and lower portions of the trench sidewall 190. The slopes of the second sidewall 194 are substantially the same.

The shielding area 160 surrounds at least the lower portion of the trench sidewall 190. In this embodiment, the second shielding area 164 extends to the upper portion of the trench sidewall 190 and is adjacent to the second sidewall 194. The first shielding area 162 is adjacent to the third sidewall 196.

A first distance L1 between the first sidewall 192 and the second sidewall 194 in the transverse direction D1 is less than a second distance L2 between the third sidewall 196 and the second sidewall 194 in the transverse direction D1. The first gate 142 is accommodated in the first trench TR1, and the second gate 144 is accommodated in the second trench TR2. The first distance L1 is equal to the average width of the first trench TR1 that accommodates the first gate 142, and the second distance L2 is equal to the average width of the second trench TR2 that accommodates the second gate 144.

The vertical projection of the second gate 144 formed in the second trench TR2 on the base layer 120 overlaps with the vertical projection of the first shielding region 162 on the base layer 120. The second trench TR2 is formed by etching the first trench TR1, which will be described in detail later.

In other embodiments, the doping concentration of one of the first shielding region 162, the second shielding region 164, and the third shielding region 166 is higher. In other embodiments, the outer sides of the first shielding region 162 and the second shielding region 164 further include doped regions of the first conductivity type (N-type) (not shown), arranged corresponding to the first shielding region 162 and the second shielding region 164. The length, spacing, and interleaving distance of the doped regions of the first conductivity type (N-type) with respect to the first shielding region 162 and the second shielding region 164 can be set according to actual needs to adjust the on-resistance and breakdown voltage of the power semiconductor device 100.

Figures 2 to 6 are cross-sectional views of intermediate steps in the manufacturing method of the power semiconductor device 100 of Figure 1. The component connection relationships, materials, and functions that have been described will not be repeated and are therefore described first.

Referring to FIG. 2 , the manufacturing method of the power semiconductor device 100 begins by providing an epitaxial layer 130 on a substrate layer 120. Next, a first trench TR1 is formed in the epitaxial layer 130. The steps of forming the first trench TR1 may include patterning a photoresist layer (not shown), etching a mask layer 200 through the photoresist layer, removing the photoresist layer, and finally etching the epitaxial layer 130. The first trench TR1 is formed by the patterning of the mask layer 200. The material of the mask layer 200 is, for example, tetraethoxysilane (TEOS). Next, the first trench TR1 is laid out to form a first shielding region 162, a second shielding region 164, and a third shielding region 166 having a second conductivity type (P-type). The manufacturing method of the power semiconductor device 100 continues with forming the source/drain doped region 150 on the epitaxial layer 130 adjacent to the upper portion of the trench sidewall 190 .

The manufacturing method of the power semiconductor device 100 continues by forming a first gate oxide layer 172 in the first trench TR1. The first gate oxide layer 172 has a first thickness T1. The first gate oxide layer 172 covers the first sidewall 192, the second sidewall 194, and the bottom of the first trench TR1. In one embodiment, the first gate oxide layer 172 is formed by thermal oxidation in an environment of 1000 to 1600 degrees Celsius. In another embodiment, the first gate oxide layer 172 is formed by atomic layer deposition (ALD) of silicon dioxide.

3 , the method for manufacturing the power semiconductor device 100 continues by filling the first trench TR1 (see FIG. 2 ) with a polysilicon material 140M and covering the first gate oxide layer 172 and the mask layer 200. The polysilicon material 140M is formed by a low pressure chemical vapor deposition (LPCVD) process.

The manufacturing method of the power semiconductor device 100 continues by forming another mask layer 300 on the polysilicon material 140M and patterning the mask layer 300 using the photoresist layer 400. The polysilicon material 140M is then patterned using the mask layer 300. The mask layer 300 is made of the same material as the mask layer 200.

4 , the manufacturing method of the power semiconductor device 100 continues with forming an extension structure 146 that electrically connects the polysilicon material 140M to the source metal 180. The photoresist layer 400 is then removed.

Referring to FIG. 5 , the method for manufacturing the power semiconductor device 100 continues by etching the polysilicon material 140M (see FIG. 3 ) to form a first gate 142. This step is equivalent to forming the first gate 142 in the first gate oxide layer 172. The method for manufacturing the power semiconductor device 100 continues by forming a patterned mask layer 200 through the photoresist layer 500. The photoresist layer 500 has a tilt angle θ, so the mask layer 200 after etching also has a tilt angle θ. For example, the tilt angle θ is approximately 15 degrees relative to the vertical direction, but the present disclosure is not limited thereto. The photoresist layer 500 and the mask layer 200 can determine the shallow trench region R where the second trench TR2 is subsequently formed.

Referring to FIG. 6 , the manufacturing method of the power semiconductor device 100 continues with forming a second trench TR2, which is asymmetrical in the lateral direction D1. Forming the second trench TR2 includes removing the epitaxial layer 130 located above the first sidewall 192 of the trench sidewall 190 in the shallow trench region R shown in FIG. 5 to form a third sidewall 196. This step also removes a portion of the epitaxial layer 130 located above the first shielding region 162.

Referring to FIG. 1 , the method for manufacturing the power semiconductor device 100 continues by forming a second gate oxide layer 174 in the second trench TR2 and removing the photoresist layer 500. The second gate oxide layer 174 is located above the first gate 142 and on the third sidewall 196. The portion of the second gate oxide layer 174 located on the third sidewall 196 has a second thickness T2, which is less than the first thickness T1. By providing gate oxide layers 170 with different thicknesses, the breakdown voltage can be increased.

The manufacturing method of the power semiconductor device 100 continues by forming a second gate 144 in the second trench TR2. This step may include first forming polysilicon material using a low-pressure chemical vapor deposition (LPCVD) process, and then removing the portion outside the second trench TR2 using an etching or chemical mechanical polishing process. The direction and angle of the channel region 156 are determined by the third sidewall 196.

The above steps are equivalent to forming the gate oxide layer 170 in the first trench TR1 and the second trench TR2 and forming the gate structure 140 in the first trench TR1 and the second trench TR2. Finally, a source metal 180 is formed on the epitaxial layer 130 and the gate structure 140.

In summary, a semiconductor device with a trench gate structure makes the channel region vertical, thereby increasing the current density. The direction and angle of the channel region can be determined by the sidewalls of the trench that accommodates the second gate. By providing a shielding region, the strong electric field in the vertical power semiconductor device can be shielded. By providing gate oxide layers with different thicknesses and a split gate, the breakdown voltage can be increased. The present disclosure can integrate the steps of forming a channel region with a specific angle, gate oxide layers with different thicknesses, and a split gate to optimize the process of high-power semiconductor devices. The doping concentration and area size of the shielding region can be varied to adjust the on-resistance and breakdown voltage.

Although the present invention has been disclosed in the form of embodiments as described above, it is not intended to limit the present invention. Anyone skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the attached patent application.

100: Power semiconductor device 110: Drain metal 120: Substrate layer 130: Epitaxial layer 140: Gate structure 140M: Polysilicon material 142: First gate 144: Second gate 1422, 1442: First side 1424, 1444: Second side 146: Extension structure 150: Source/drain doped region 152: Source region 154: Well region 156: Channel region 160: Shielding region 162: First shielding region 164: Second shielding region 166: Third shielding region 170: Gate oxide layer 172: First gate oxide layer 174: Second gate oxide layer 180: Source metal 190: Trench sidewalls 192: First sidewalls 194: Second sidewalls 196: Third sidewalls 198: Curved sidewalls 200, 300: Mask layer 400, 500: Photoresist layer W1: First width W2: Second width C1: First center position C2: Second center position T1: First thickness T2: Second thickness D1: Lateral direction TR1: First trench TR2: Second trench L1: First distance L2: Second distance θ: Tilt angle R: Shallow trench region

Figure 1 is a cross-sectional view of a power semiconductor device according to one embodiment of the present disclosure. Figures 2 through 6 are cross-sectional views of intermediate steps in the method for manufacturing the power semiconductor device of Figure 1.

100: Power semiconductor devices

110: Drain Metal

120: Basal layer

130: Epitaxial layer

140: Gate structure

142: First Gate

144: Second Gate

1422,1442: First side

1424,1444: Second side

150: Source/drain doped region

152: Source region

154: Well Area

156: Channel Area

160: Sheltered Area

162: First Shelter Area

164: Second Shelter Area

166: Third Shelter Area

170: Gate oxide layer

172: First gate oxide layer

174: Second gate oxide layer

180: Source Metal

190: Groove sidewall

192: First side wall

194: Second side wall

196: Third side wall

198: Curved sidewall

W1: First Width

W2: Second Width

C1: First center position

C2: Second center position

T1: First thickness

T2: Second thickness

D1: Horizontal

TR1: First Groove

TR2: Second Groove

L1: First distance

L2: Second distance

Claims (10)

A power semiconductor device includes: a drain metal; a base layer located on the drain metal; an epitaxial layer located on the base layer and having a first conductivity type; a trench sidewall including a first sidewall, a second sidewall, a third sidewall, and a curved sidewall, wherein the first sidewall is opposite to the second sidewall, the third sidewall is opposite to the second sidewall, the curved sidewall is located between the first sidewall and the third sidewall, and the third sidewall has a tilt angle to control the distribution of a channel region; and a gate structure located in the epitaxial layer, wherein the gate structure is asymmetric in a transverse direction. The gate structure includes a first gate and a second gate, wherein the second gate is located above the first gate, the first gate is located between the first sidewall and the second sidewall, and the second gate is located between the third sidewall and the second sidewall; a source/drain doped region is located adjacent to the second gate. a shielding region located in the epitaxial layer and surrounding at least the first gate, the first sidewall and the second sidewall and having a second conductivity type; a gate oxide layer located between the gate structure and the epitaxial layer; and a source metal located on the epitaxial layer. The power semiconductor device as claimed in claim 1, wherein the first gate and the second gate are separated from each other, and the first gate is electrically connected to the source metal. The power semiconductor device as described in any one of claims 1-2, wherein a first center position of the first gate in the horizontal direction is offset from a second center position of the second gate in the horizontal direction. The power semiconductor device as described in any of claims 1-2 further includes: a first gate oxide layer located between the shielding region and the first gate and between the epitaxial layer and the second gate located on a second side adjacent to the second gate, wherein the first side is opposite to the second side; and a second gate oxide layer located between the source/drain doped region and the first side of the second gate. The power semiconductor device of claim 4, wherein a second thickness of the second gate oxide layer is smaller than a first thickness of the first gate oxide layer. A method for manufacturing a power semiconductor device includes: forming an epitaxial layer on a substrate layer, wherein the epitaxial layer has a first conductivity type; forming a first trench in the epitaxial layer, wherein the first trench has a trench sidewall, wherein the trench sidewall includes a first sidewall and a second sidewall; arranging the trench sidewall to form a shielding region, wherein the shielding region has a second conductivity type and surrounds at least a lower portion of the trench sidewall; forming a source/drain doped region adjacent to an upper portion of the trench sidewall; The invention relates to a method for forming a first epitaxial layer in a first trench and a second trench so that the second trench is asymmetric in a lateral direction, comprising: removing the epitaxial layer of a first sidewall located on the upper portion of the trench sidewall through a mask layer having a tilt angle to form a third sidewall and a curved sidewall located between the first sidewall and the third sidewall, wherein the third sidewall is used to determine the distribution of a channel region; forming a gate oxide layer in the first trench and the second trench; and forming a gate structure in the first trench and the second trench. The method for manufacturing a power semiconductor device as described in claim 6, wherein forming the second trench so that the second trench is asymmetric in the lateral direction further includes: making a first distance from the first sidewall to the second sidewall smaller than a second distance from the third sidewall to the second sidewall, the third sidewall being opposite to the second sidewall, and the third sidewall being connected to the first sidewall. The method for manufacturing a power semiconductor device as described in claim 6, wherein forming the gate oxide layer in the first trench and the second trench includes: forming a first gate oxide layer in the first trench; and after forming the second trench, forming a second gate oxide layer in the third sidewall of the second trench. The method for manufacturing a power semiconductor device as described in claim 8, wherein forming the gate oxide layer in the first trench and the second trench further includes: making a second thickness of the second gate oxide layer smaller than a first thickness of the first gate oxide layer. A method for manufacturing a power semiconductor device as described in claim 8, wherein forming the gate structure in the first trench and the second trench includes: forming a first gate in the first gate oxide layer after forming the first gate oxide layer in the first trench; and forming a second gate after forming the second gate oxide layer in the third sidewall of the second trench.