TW202009902A - Semiconductor substrate and driving method - Google Patents

Abstract

A semiconductor substrate includes a data line, a scan line, a capacitance control line, a first transistor, a pixel electrode, a second transistor, a storage capacitor and a third transistor. A first terminal of the first transistor is electrically connected to the data line. A control terminal of the first transistor is electrically connected to the scan line. The pixel electrode is electrically connected to a second terminal of the first transistor. A first terminal of the second transistor is electrically connected to the second terminal of the first transistor. The storage capacitor is electrically connected to a second terminal of the second transistor. A first terminal of the third transistor is electrically connected to the capacitance control line. A control terminal of the third transistor is electrically connected to the scan line, and a second terminal of the third transistor is electrically connected to a control terminal of the second transistor. In addition, a driving method is also been proposed.

Description

Semiconductor substrate and driving method

The invention relates to a semiconductor substrate and a driving method.

With the development of display technology, display panels have been widely used in daily life. Taking the application of mobile electronic devices (such as mobile phones, watches, tablet computers, notebook computers, etc.) as an example, one of the important characteristics of the display panel is power consumption. If the power consumption of the display panel is low, that is, the display panel saves power, it helps to extend the use time of the mobile electronic device.

In the conventional technology, in order to reduce the power consumption of the display panel, the update frequency of the display image can be adjusted down, for example: 30 Hz or 15 Hz. However, when the update frequency is low, the pixel leakage of the pixel structure of the display panel is high, and flicker occurs in a specific grayscale image. To improve the flicker problem, the storage capacitor of the pixel structure of the display panel can be increased. However, when the storage capacitance increases, the charging rate of the pixel structure may be insufficient, which affects the display quality. In addition, the increase in storage capacitance will also make the display panel consume more power.

The invention provides a semiconductor substrate, which can realize a display panel with good display quality and power saving.

The present invention provides a driving method. Using this driving method to drive a semiconductor substrate of a display panel can reduce the power consumption of the display panel and take into account the display quality.

The semiconductor substrate of the present invention includes a base, a data line, a scanning line, a capacitance control line, a first transistor, a pixel electrode, a second transistor, a storage capacitor, and a third transistor. The data line, the scanning line and the capacitance control line are arranged on the substrate. The first end of the first transistor is electrically connected to the data line. The control terminal of the first transistor is electrically connected to the scan line. The pixel electrode is electrically connected to the second end of the first transistor. The first end of the second transistor is electrically connected to the second end of the first transistor. The storage capacitor is electrically connected to the second end of the second transistor. The first end of the third transistor is electrically connected to the capacitor control line. The control terminal of the third transistor is electrically connected to the scan line. The second terminal of the third transistor is electrically connected to the control terminal of the second transistor.

In an embodiment of the invention, a vertical projection of the second transistor on the substrate is located between a vertical projection of the first transistor on the substrate and a vertical projection of the third transistor on the substrate.

In an embodiment of the invention, a vertical projection of the second transistor on the substrate is between a vertical projection of the scan line on the substrate and a vertical projection of the storage capacitor on the substrate.

In an embodiment of the present invention, the above-mentioned data line extends in the first direction, the scan line extends in the second direction, the control end of the second transistor extends in the third direction, and the third direction and the first direction And the second direction is staggered.

In an embodiment of the invention, the second direction and the third direction have an angle θ, and 0 ^o <θ<60 ^o .

In an embodiment of the invention, the above-mentioned second transistor includes a semiconductor pattern extending in the fourth direction, and the third direction is interlaced with the first direction, the second direction, and the fourth direction.

In an embodiment of the present invention, the second direction and the fourth direction have an angle Φ, and 0 ^o <Φ<60 ^o .

In an embodiment of the present invention, the third direction and the fourth direction have an angle α, and 0 ^o <α≦90 ^o .

In an embodiment of the invention, the above-mentioned storage capacitor includes an insulating layer and a conductive pattern. The insulating layer is disposed on the second end of the second transistor. The pixel electrode is provided on the insulating layer. The conductive pattern is disposed on the insulating layer. The conductive pattern is separated from the pixel electrode. The conductive pattern is electrically connected to the second end of the second transistor through the contact window of the insulating layer, wherein the conductive pattern overlaps the second end of the second transistor.

In an embodiment of the invention, the above-mentioned semiconductor substrate further includes a common electrode, which is disposed on the base. The common electrode overlaps the pixel electrode to form a display dielectric capacitor. The capacitance value of the storage capacitor is greater than half the capacitance value of the display dielectric capacitor.

，第二電晶體的半導體圖案具有通道寬長度

，而

。In an embodiment of the invention, the semiconductor pattern of the first transistor mentioned above has a channel width-to-length ratio

, The semiconductor pattern of the second transistor has a wide channel length

,and

.

，而

。In an embodiment of the invention, a semiconductor pattern of the above third transistor has a channel width to length ratio

,and

.

The driving method of the present invention is used to drive a semiconductor substrate. The semiconductor substrate includes a plurality of pixel structures, each of the plurality of pixel structures includes a data line, a scanning line, a capacitance control line, a first transistor, a pixel electrode, a second transistor, and a storage capacitor, wherein the first transistor The first end of the first transistor is electrically connected to the data line, the control end of the first transistor is electrically connected to the scan line, the second end of the first transistor is electrically connected to the pixel electrode, and the first end of the second transistor is electrically connected Is electrically connected to the second end of the first transistor, the control end of the second transistor is electrically connected to the capacitor control line, and the second end of the second transistor is electrically connected to the storage capacitor. The above driving method includes: determining whether to turn on or off at least one second transistor of at least one of the plurality of pixel structures according to at least one data signal of at least one data line of at least one of the plurality of pixel structures.

In an embodiment of the invention, the above-mentioned at least one data signal of at least one data line of at least one of the plurality of pixel structures determines the opening of at least one second transistor of at least one of the plurality of pixel structures Or the step of turning off includes: judging when the gray level value of at least one data signal of at least one data line of at least one of the plurality of pixel structures is between a first preset value and a second preset value, At least one second transistor of at least one of the pixel structures is turned on, wherein the first preset value is smaller than the second preset value.

In an embodiment of the invention, the above-mentioned at least one data signal of at least one data line of at least one of the plurality of pixel structures determines the opening of at least one second transistor of at least one of the plurality of pixel structures Or the step of turning off includes: judging that when the gray level value of at least one data signal of at least one data line of at least one of the plurality of pixel structures is less than the first preset value, enabling at least one of the plurality of pixel structures At least one second transistor is turned off.

In an embodiment of the invention, the above-mentioned at least one data signal of at least one data line of at least one of the plurality of pixel structures determines the opening of at least one second transistor of at least one of the plurality of pixel structures Or the step of turning off includes: judging that when the gray level value of at least one data signal of at least one data line of at least one of the plurality of pixel structures is greater than the second preset value, enabling at least one of the plurality of pixel structures At least one second transistor is turned off.

In an embodiment of the present invention, the above-mentioned multiple pixel structures are used to display multiple images, and the driving method further includes: determining multiple first pixels of the multiple pixel structures according to multiple characteristics of the multiple images Turn on or off the two transistors.

In an embodiment of the invention, the above-mentioned plurality of images include a first image and a second image, and the plurality of pixel structures include a plurality of first pixel structures for displaying the first image and A plurality of second pixel structures displaying the second image, and the steps of turning on or off the plurality of second transistors of the plurality of pixel structures are determined according to the characteristics of the plurality of images of the plurality of pixel structures Including: judging when the first image includes a gray screen and white text interspersed in the gray screen, turning off the plurality of second transistors of the plurality of first pixel structures; and judging when the second image includes a full gray During the picture, the second transistors of the second pixel structure are turned on.

In an embodiment of the present invention, the step of determining whether to turn on or off the plurality of second transistors of the plurality of pixel structures according to the plurality of characteristics of the plurality of images of the plurality of pixel structures includes: The multiple update frequencies of the image determine whether the multiple second transistors of multiple pixel structures are turned on or off.

In an embodiment of the invention, the above-mentioned plurality of images include a first image and a second image, and the plurality of pixel structures include a plurality of first pixel structures for displaying the first image and Display a plurality of second pixel structures of the second image, and determine whether to turn on or turn off the plurality of second transistors of the plurality of pixel structures according to the plurality of update frequencies of the plurality of images of the plurality of pixel structures The steps include: judging when the update frequency of the first image is equal to or lower than the first preset frequency, turning on the plurality of second transistors of the plurality of first pixel structures; and judging when the second image is updated When the frequency is equal to or higher than the second preset frequency, the second transistors of the second pixel structure are turned off, wherein the first preset frequency is higher than the second preset frequency.

In an embodiment of the present invention, each of the plurality of data signals of the plurality of data lines of the plurality of pixel structures is between a high data potential Vdh and a low data potential Vdl, and there are as many pixel structures as possible Each of the plurality of scanning signals of one scanning line is between a high scanning potential Vgh and a low scanning potential Vgl, each of the plurality of control signals of a plurality of capacitive control lines of a plurality of pixel structures is between a high control potential Vch and a low control potential Vcl, Vdh<Vch<Vgh, and Vgl<Vcl<Vdl.

Based on the above, in an embodiment of the present invention, whether to turn on the second transistor to charge the storage capacitor can be determined according to the grayscale value to be displayed and/or the update frequency of the image to be displayed. In this way, the display panel using the semiconductor substrate according to an embodiment of the present invention can improve the flicker problem and achieve the power saving effect.

In order to make the above-mentioned features and advantages of the present invention more obvious and understandable, the embodiments are specifically described below in conjunction with the accompanying drawings for detailed description as follows.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Throughout the specification, the same reference numerals denote the same elements. It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected" to another element, it can be directly on or connected to the other element, or Intermediate elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected" may refer to physical and/or electrical connections. Furthermore, "electrical connection" or "coupling" can mean that there are other components between the two components.

As used herein, "about", "approximately", or "substantially" includes the stated value and the average value within the acceptable deviation range of the specific value determined by those of ordinary skill in the art, taking into account the measurements and A certain amount of measurement-related errors (ie, limitations of the measurement system). For example, "about" may mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%. In addition, "about", "approximately" or "substantially" used in this article can select a more acceptable range of deviation or standard deviation according to optical properties, etching properties or other properties, instead of applying one standard deviation to all properties .

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which this invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings in the context of the relevant technology and the present invention, and will not be interpreted as idealized or excessive Formal meaning unless explicitly defined as such in this article.

Exemplary embodiments are described herein with reference to cross-sectional views that are schematic diagrams of idealized embodiments. Therefore, it is possible to anticipate a change in the shape of the graph as a result of, for example, manufacturing techniques and/or tolerances. Therefore, the embodiments described herein should not be construed as being limited to the specific shape of the area as shown herein, but include deviations in shapes caused by manufacturing, for example. For example, an area shown or described as flat may generally have rough and/or non-linear characteristics. In addition, the acute angle shown may be round. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the precise shapes of the regions, and are not intended to limit the scope of the claims.

Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element symbols are used in the drawings and description to denote the same or similar parts.

FIG. 1 is a schematic diagram of a pixel structure PX according to the first embodiment of the invention. Referring to FIG. 1, the pixel structure PX includes a data line DL, a scanning line GL, a capacitance control line CL, a first transistor T1, a second transistor T2, a display dielectric capacitor Clc, and a storage capacitor Cst. The first transistor T1 has a first terminal T1a, a control terminal T1c, and a second terminal T1b. The second transistor T2 has a first terminal T2a, a control terminal T2c, and a second terminal T2b. The first terminal T1a of the first transistor T1 is electrically connected to the data line DL. The control terminal T1c of the first transistor T1 is electrically connected to the scanning line GL. The second terminal T1b of the first transistor T1 is electrically connected to an electrode Alc1 of the display dielectric capacitor Clc. The other electrode Alc2 of the display dielectric capacitor Clc is electrically connected to a reference potential, where the reference potential may be a ground potential, a fixed potential or an adjustable potential. The first terminal T2a of the second transistor T2 is electrically connected to the second terminal T1b of the first transistor T1. The control terminal T2c of the second transistor T2 is electrically connected to the capacitance control line CL. The second terminal T2b of the second transistor T2 is electrically connected to an electrode Ast1 of the storage capacitor Cst. The other electrode Ast2 of the storage capacitor Cst is electrically connected to a reference potential, where the reference potential may be a ground potential, a fixed potential, or an adjustable potential. In this embodiment, the pixel structure PX further includes a third transistor T3. The first terminal T3a of the third transistor T3 is electrically connected to the capacitance control line CL. The control terminal T3c of the third transistor T3 is electrically connected to the scanning line GL. The second terminal T3b of the third transistor T3 is electrically connected to the control terminal T2c of the second transistor T2.

2 is a schematic top view of the semiconductor substrate according to the first embodiment of the invention. 2, the semiconductor substrate 100 includes a base 110 and a plurality of pixel structures PX disposed on the base 110. The plurality of data lines DL of the partial pixel structures PX1, PX2, and PX3 of the semiconductor substrate 100 may be connected to each other. A plurality of capacitance control lines CL of the partial pixel structures PX1, PX2, and PX3 of the semiconductor substrate 100 may be connected to each other. The scan lines GL1, GL2, and GL3 of the partial pixel structures PX1, PX2, and PX3 of the semiconductor substrate 100 can be separated from each other and arranged in sequence.

FIG. 3 shows scan signals VGL1, scan signals VGL2, and scan signals of scan line GL1, scan line GL2, scan line GL3, data line DL, and capacitance control line CL of FIG. 2 at respective time intervals t1, t2, and t3 VGL3, data signal VDL and control signal VCL.

4 is a relationship curve S1 of the root mean square voltage value (V) of the data signal VDL of the pixel structure PX and the brightness (cd/m ² ) of the pixel structure PX according to the first embodiment of the present invention. 5 is the normalized change rate of the root mean square voltage value (V) of the data signal VDL of the pixel structure PX and the brightness of the pixel structure PX to the root mean square voltage value of the data signal VDL according to the first embodiment of the invention的 Relation curve S2. Differentiating the relationship curve S1 of FIG. 4 can obtain the relationship curve S2 of FIG. 5.

In this embodiment, the second transistor T2 can be turned on or off according to the data signal VDL of the data line DL of each pixel structure PX, and then control whether to charge the storage capacitor Cst. The following is an example with reference to FIGS. 2 to 5.

2 and 3, in this embodiment, in the first time interval t1, the scanning signal VGL1 of the scanning line GL1 of the pixel structure PX1 has a high scanning potential Vgh, and the data of the data line DL of the pixel structure PX1 The signal VDL is switched from the gray level value L0 to the gray level value L128. The root mean square voltage value of the data signal VDL corresponding to the gray level value L128 is VL128 (marked in FIG. 4). Determine that when the gray level value L128 is between the first preset value and the second preset value, the control signal VCL of the capacitor control line CL of the pixel structure PX1 has a high control potential Vch, where the first preset value is less than The second preset value. At this time, the first transistor T1, the second transistor T2, and the third transistor T3 of the pixel structure PX1 are all turned on, and the storage capacitor Cst and the display medium capacitor Clc of the pixel structure PX1 are both charged. In this way, even when the pixel structure PX1 is used to display an image, the pixel structure PX1 has a leakage current which accounts for the storage capacitance Cst and the display medium capacitance Clc of the pixel structure PX1 originally stored The proportion of the total charge amount is low, therefore, the leakage amount does not cause the voltage on the display medium capacitance Clc to drop excessively. In this way, even if the pixel structure PX1 operates at the gray scale value L128, and the brightness of the pixel structure PX1 is sensitive to the voltage change near the root mean square voltage value VL128 (marked in FIG. 4) (or, the relationship curve S1 is at the average The tangent slope at the square root voltage value VL128 is large), and the flicker of the display panel using the pixel structure PX1 is still slight, which meets the product specifications.

In short, when the gray level value L128 of the pixel structure PX1 is between the first preset value and the second preset value, the second transistor T2 of the pixel structure PX1 can be turned on to protect the storage capacitor Cst is charged. Thereby, the influence of the leakage current of the pixel structure PX1 on the brightness of the pixel structure PX1 can be reduced, and the flicker problem of the display panel using the pixel structure PX1 can be improved. The following illustrates an example of how to select the first preset value and the second preset value in conjunction with FIGS. 4 and 5.

4 and 5, the relationship curve S2 has a maximum normalized rate of change of 100%, while the relationship curve S2 has the maximum normalized rate of change at the rms voltage value VL20 and the rms voltage value VL192, respectively 10% of 100%. In this embodiment, the first preset value and the second preset value may be the gray scale value L20 and the gray scale value L192 corresponding to the root mean square voltage value VL20 and the root mean square voltage value VL192, respectively. However, the invention is not limited to this. In other embodiments, the first preset value and the second preset value can also be set in other ways.

2 and 3 again, in the second time interval t2 following the first time interval t1, the scan signal VGL2 of the scan line GL2 of the pixel structure PX2 has a high scan potential Vgh, and the data line DL of the pixel structure PX2 The data signal VDL is switched from the gray level value L128 to the gray level value L255. The root mean square voltage value of the data signal VDL corresponding to the gray scale value L255 is VL255 (marked in FIG. 4). It is determined that when the gray scale value L255 is greater than the second preset value, or when the gray scale value L255 is less than the first preset value, the control signal VCL of the capacitor control line CL of the pixel structure PX2 has a low control potential Vcl. At this time, the first transistor T1 and the third transistor T3 of the pixel structure PX2 are turned on, the second transistor T2 of the pixel structure PX2 is turned off, the display medium capacitance Clc of the pixel structure PX2 is charged, and the pixel The storage capacitor Cst of the structure PX2 will not be charged. In this way, even when the pixel structure PX2 is used to display an image, the pixel structure PX2 has a leakage current, and the leakage current accounts for the amount of charge originally stored in the display medium capacitance Clc of the pixel structure PX2 Is high, because the brightness of the pixel structure PX2 is insensitive to voltage changes around the rms voltage value VL255 (or the slope of the tangent of the relationship curve S1 at the rms voltage value VL255 is small), so the leakage It does not cause the brightness of the pixel structure PX2 to change excessively. That is, when the gray scale value L255 is greater than the second preset value or less than the first preset value, even if the second transistor T2 is turned off without charging the storage capacitor Cst, the display panel using the pixel structure PX2 flickers (flick ) The degree is still slight and meets product specifications. In addition, since the storage capacitor Cst of the pixel structure PX2 can not be charged, the display panel adopting the pixel structure PX2 can achieve the effect of power saving when the flickering degree meets the specification value.

2 and 3 again, in this embodiment, in the third time interval t3 following the second time interval t2, the scan signal VGL1 of the scan line GL3 of the pixel structure PX3 has a high scan potential Vgh, pixels The data signal VDL of the data line DL of the structure PX3 is switched from the gray scale value L255 to the gray scale value L128. The root mean square voltage value of the data signal VDL corresponding to the gray level value L128 is VL128 (marked in FIG. 4). It is determined that when the gray level value L128 is between the first preset value and the second preset value, the control signal VCL of the capacitor control line CL of the pixel structure PX3 has a high control potential Vch. At this time, the first transistor T1, the second transistor T2, and the third transistor T3 of the pixel structure PX3 are all turned on, and the storage capacitor Cst and the display medium capacitor Clc of the pixel structure PX3 are both charged. In this way, even when the pixel structure PX3 is used to display an image, the pixel structure PX3 has a leakage current which accounts for the storage capacitance Cst and the display medium capacitance Clc of the pixel structure PX3 originally stored The proportion of the total charge amount is low, therefore, the leakage amount does not cause the voltage on the display medium capacitance Clc to drop excessively. In this way, even if the pixel structure PX3 operates at the gray scale value L128, and the brightness of the pixel structure PX3 is very sensitive to the voltage change near the rms voltage value VL128 (or, the relationship curve S1 is at the rms voltage value VL128 (The slope of the tangent line is large), the display panel using the pixel structure PX3 still has a slight flicker, which meets the product specifications.

In addition, in this embodiment, the multiple data signals VDL of the data line DL of the pixel structure PX are between a high data potential Vdh (such as but not limited to: gray level value L255) and a low data potential Vdl (such as but not Limited to: gray level value L0), each of the plurality of scanning signals VGL1, VGL2, VGL3 of the scanning line GL of the pixel structure PX is between the high scanning potential Vgh and the low scanning potential Vgl, and the capacitance control line CL of the pixel structure PX The plurality of control signals VCL are between a high control potential Vch and a low control potential Vcl, where Vdh<Vch<Vgh and Vgl<Vcl<Vdl.

6 is a schematic diagram of a display panel according to a first embodiment of the invention. Referring to FIG. 6, the display panel 10 includes a semiconductor substrate 100 (not shown) having the aforementioned pixel structure PX, a counter substrate (not shown) relative to the semiconductor substrate 100, and the semiconductor substrate 100 and the counter substrate Display medium between (not shown; for example, but not limited to: liquid crystal). The display panel 10 has a plurality of display areas Ron and Roff. In this embodiment, the plurality of second transistors of the plurality of pixel structures PX respectively located in the plurality of display regions Ron and Roff may be determined according to the characteristics of the image displayed by each of the plurality of display regions Ron and Roff T2 is turned on or off. In this embodiment, the opening or closing of the second transistor T2 of each pixel structure PX can be determined by the scanning signal VGL of the scanning line GL of each pixel structure PX and the control signal VCL of the capacitance control line CL; In this embodiment, it can be determined whether the second transistor T2 of each pixel structure PX is turned on, and the display region Ron where the second transistor T2 is turned on and the display region Roff where the second transistor T2 is turned off can be located in the same row And/or different lines, depending on actual needs.

7 is a schematic diagram of a pixel structure PX' according to a second embodiment of the invention. Referring to FIG. 1, the pixel structure PX' includes a data line DL, a scanning line GL, a capacitance control line CL, a first transistor T1, a second transistor T2, a display dielectric capacitor Clc, and a storage capacitor Cst. The first transistor T1 has a first terminal T1a, a control terminal T1c, and a second terminal T1b. The second transistor T2 has a first terminal T2a, a control terminal T2c, and a second terminal T2b. The first terminal T1a of the first transistor T1 is electrically connected to the data line DL. The control terminal T1c of the first transistor T1 is electrically connected to the scanning line GL. The second terminal T1b of the first transistor T1 is electrically connected to an electrode Alc1 of the display dielectric capacitor Clc. The other electrode Alc2 of the display dielectric capacitor Clc is electrically connected to a reference potential, where the reference potential may be a ground potential, a fixed potential or an adjustable potential. The first terminal T2a of the second transistor T2 is electrically connected to the second terminal T1b of the first transistor T1. The control terminal T2c of the second transistor T2 is electrically connected to the capacitance control line CL. The second terminal T2b of the second transistor T2 is electrically connected to an electrode Ast1 of the storage capacitor Cst. The other electrode Ast2 of the storage capacitor Cst is electrically connected to a reference potential, where the reference potential may be a ground potential, a fixed potential, or an adjustable potential.

The difference between the pixel structure PX′ of FIG. 7 and the pixel structure PX of FIG. 1 is that the pixel structure PX′ of FIG. 7 may not include the third transistor T3 of FIG. The control terminal T2c of the two transistor T2 can be directly electrically connected to the capacitance control line CL.

8 is a schematic top view of a semiconductor substrate according to a second embodiment of the invention. Referring to FIG. 8, the semiconductor substrate 100' includes a base 110 and a plurality of pixel structures PX' disposed on the base 110. The plurality of scan lines GL of the partial pixel structures PX'1 and PX'2 of the semiconductor substrate 100' may be connected to each other. The plurality of data lines DL1 and DL2 of the partial pixel structures PX'1 and PX'2 of the semiconductor substrate 100' can be separated from each other and arranged in sequence. The plurality of capacitance control lines CL1 and CL2 of the partial pixel structures PX'1 and PX'2 of the semiconductor substrate 100' can be separated from each other and arranged in sequence.

9 shows the scan signal VGL, the data signal VDL1, the data signal VDL2, and the control signal that the scan line GL, the data line DL1, the data line DL2, the data control line CL1, and the capacitor control line CL2 of FIG. 8 respectively have in the time interval t1 VCL1, and control signal VCL2.

Please refer to FIG. 8 and FIG. 9, in this embodiment, during the time interval t1, the scanning signal VGL of the scanning line GL of the pixel structure PX'1 has a high scanning potential Vgh, and the data line DL1 of the pixel structure PX'1 The data signal VDL1 is switched from the gray level value L0 to the gray level value L128. The root mean square voltage value of the data signal VDL1 corresponding to the gray scale value L128 is VL128. It is determined that when the gray level value L128 is between the first preset value and the second preset value, the control signal VCL1 of the capacitor control line CL1 of the pixel structure PX'1 has a high control potential Vch. At this time, both the first transistor T1 and the second transistor T2 of the pixel structure PX'1 are turned on, and both the storage capacitor Cst and the display dielectric capacitor Clc of the pixel structure PX'1 are charged. In this way, even when the pixel structure PX'1 is used to display an image, the pixel structure PX'1 has a leakage current, which accounts for the storage capacitance Cst of the pixel structure PX'1 and the display The proportion of the total charge amount originally stored in the dielectric capacitor Clc is low. Therefore, the leakage current does not cause the voltage on the display dielectric capacitor Clc to drop excessively. In this way, even if the pixel structure PX'1 operates at the gray scale value L128, and the brightness of the pixel structure PX'1 is very sensitive to the voltage change near the root mean square voltage value VL128, the display panel using the pixel structure PX'1 The flick of 10' (shown in Figure 10) is still slight and meets the product specifications.

Referring again to FIGS. 8 and 9, at the time interval t1, the scanning signal VGL of the scanning line GL of the pixel structure PX'2 has a high scanning potential Vgh, and the data signal VDL2 of the data line DL2 of the pixel structure PX'2 is The gray scale value L0 is switched to the gray scale value L255. The root mean square voltage value of the data signal VDL2 corresponding to the gray scale value L255 is VL255. It is determined that when the gray scale value L255 is greater than the second preset value, or when the gray scale value L255 is less than the first preset value, the control signal VCL2 of the capacitor control line CL2 of the pixel structure PX'2 has a low control potential Vcl . At this time, the first transistor T1 of the pixel structure PX'2 is turned on, the second transistor T2 of the pixel structure PX'2 is turned off, the display medium capacitance Clc of the pixel structure PX'2 is charged, and the pixel The storage capacitor Cst of the structure PX'2 will not be charged. In this way, even when the pixel structure PX'2 is used to display an image, the pixel structure PX'2 has a leakage amount, and the leakage amount accounts for the amount of charge originally stored in the display dielectric capacitor Clc When the ratio is high, since the brightness of the pixel structure PX'2 is not sensitive to the voltage change near the root mean square voltage value VL255, the leakage current does not cause the brightness of the pixel structure PX'2 to change excessively. That is, when the gray scale value L255 is greater than the second preset value or less than the first preset value, even if the second transistor T2 is turned off without charging the storage capacitor Cst, the display panel 10' using the pixel structure PX'2 The flicker is still slight and meets product specifications. In addition, since the storage capacitor Cst of the pixel structure PX'2 may not be charged, the display panel 10' can achieve the effect of power saving when the degree of flicker meets the specification value.

10 is a schematic diagram of a display panel according to a second embodiment of the invention. 10, the display panel 10 ′ includes a semiconductor substrate 100 ′ (not shown) having the aforementioned pixel structure PX′, a counter substrate (not shown) opposite to the semiconductor substrate 100 ′, and a semiconductor substrate 100 'Display medium between the opposite substrate (not shown; for example, but not limited to: liquid crystal). The display panel 10' has a plurality of display areas Ron, Roff. In this embodiment, for the characteristics of the image displayed by each of the plurality of display areas Ron and Roff, the plurality of second powers of the plurality of pixel structures PX′ located in the plurality of display areas Ron and Roff, respectively, may be determined The crystal T2 is turned on or off. The plurality of second transistors T2 in the display area Ron are turned on, and the plurality of second transistors T2 in the display area Roff are turned off. In this embodiment, the opening or closing of the plurality of second transistors T2 of the plurality of pixel structures PX′ in the same column is determined by the control signal VCL of the same capacitor control line CL, and the second transistor T2 is turned on The display area Ron and the display area Roff where the second transistor T2 is turned off may be located in different columns, but the invention is not limited thereto.

11 is a schematic diagram of a pixel structure PX-1 according to a third embodiment of the invention. The pixel structure PX-1 of FIG. 11 is similar to the pixel structure PX of FIG. 1, the difference between the two is that: in the embodiment of FIG. 1, the capacitance control line CL and the scanning line GL are interleaved; in the embodiment of FIG. 11 , The capacitance control line CL is parallel to the scanning line GL. Thereby, the capacitor control line CL and the scanning line GL can be electrically connected to the integrated gate driver circuit (GOA; not shown) on at least one side of the display panel 10' The number of pads (not shown) that are bonded by the chip (not shown). In addition, the pixel structure PX-1 of this embodiment can be driven by driving the aforementioned pixel structure PX, which will not be repeated here.

Fig. 12 is a schematic diagram of a pixel structure PX'-1 according to the fourth embodiment of the present invention. The pixel structure PX'-1 of FIG. 12 is similar to the pixel structure PX' of FIG. 7, the difference between the two is that: in the embodiment of FIG. 7, the capacitance control line CL and the scanning line GL are interleaved; the implementation in FIG. 12 In the example, the capacitance control line CL is parallel to the scanning line GL. The pixel structure PX'-1 can be driven by driving the pixel structure PX', which will not be repeated here.

13 is a schematic diagram of a semiconductor substrate 100A according to a fifth embodiment of the invention. Referring to FIG. 13, the semiconductor substrate 100A includes a plurality of pixel groups G arranged in an array. In addition to the aforementioned pixel structure PX, each pixel group G also includes at least one pixel structure PX2, where the pixel structure PX is different from the pixel structure PX2. Specifically, the difference between the pixel structure PX2 and the aforementioned pixel structure PX is that the pixel structure PX2 does not include the third transistor T3 of the pixel structure PX and the capacitance control line CL of the pixel structure PX, and the pixel structure PX2 The control terminal T2c of the second transistor T2 is electrically connected to the second terminal T3b of the third transistor T3 of the pixel structure PX of the same pixel group G. In this embodiment, the pixel structure PX, the pixel structure PX2 and the pixel structure PX2 of the same pixel group G are used to display red, green and blue, respectively, but the invention is not limited thereto.

14 is a schematic diagram of a semiconductor substrate 100B according to a sixth embodiment of the invention. Referring to FIG. 14, the semiconductor substrate 100B includes a plurality of pixel structures PX and a plurality of pixel structures PX2, wherein each pixel structure PX2 differs from the pixel structure PX in that the pixel structure PX2 does not include the pixel structure PX The capacitance control line CL of the third transistor T3 and the pixel structure PX. The multiple pixel structures PX and the multiple pixel structures PX2 are arranged in multiple lines. The scanning line GL of the pixel structure PX of each row is electrically connected to the scanning line GL of the pixel structure PX2 of the row. In particular, the plurality of control terminals T2c of the plurality of second transistors T2 of all pixel structures PX2 in the same row are electrically connected to the second end T3b of the third transistor T3 of the pixel structure PX of the row.

15 is an electronic device using a semiconductor substrate according to any embodiment of the present invention. Referring to FIG. 15, the electronic device 1 includes a display panel having a semiconductor substrate 100. The electronic device 1 determines whether to turn on or off the plurality of second transistors T2 of the plurality of pixel structures PX according to the plurality of characteristics of the plurality of images P1 and P2 of the plurality of pixel structures PX. For example, when the electronic device 1 is in the first application scenario, the display panel of the electronic device 1 displays the static images P1 and P2, where the update frequency of the static images P1 and P2 is low, such as but not limited to: 5 Hz. The static image includes a first image P1 and a second image P2, which are located in the display area Roff and the display area Ron, respectively. The plurality of first pixel structures PX in the display area Roff of the display panel of the electronic device 1 are used to display the first image P1. The second pixel structure PX of the display area Ron of the display panel of the electronic device 1 is used to display the second image P2. It is determined that when the first image P1 includes a gray screen and white text interspersed in the gray screen, the plurality of second transistors T2 of the plurality of first pixel structures PX in the display area Roff are turned off. At this time, it is not necessary to charge the storage capacitors Cst of the plurality of first pixel structures PX of the display area Roff, and the electronic device 1 can save power; in addition, since it is not necessary to charge the plurality of first pixels of the display area Roff The plurality of storage capacitors Cst of the structure PX are charged, and the charging rate of the first pixel structure PX is high. When the charging rate of the first pixel structure PX is high enough, there will be no problem of insufficient brightness due to the low charging rate at the edges of the white text. On the other hand, it is determined that when the second image P2 includes a full-gray image, the plurality of second transistors T2 of the plurality of second pixel structures PX in the display area Ron are turned on to improve the flicker problem.

16 is an electronic device using a semiconductor substrate according to any embodiment of the present invention. Referring to FIG. 16, the electronic device 1 includes a display panel having a semiconductor substrate 100. The electronic device 1 determines whether to turn on or off the plurality of second transistors T2 of the plurality of pixel structures PX according to the plurality of characteristics of the plurality of images P3, P4, P5 of the plurality of pixel structures PX. For example, when the electronic device 1 is in the second application scenario, the display panel of the electronic device 1 displays the images P3, P4, and P5 including the static images P3, P5, and the dynamic image P4, where the static images P3, P5 are updated The frequency (eg, but not limited to: 5 Hz) is low, and the update frequency of the dynamic image P4 (eg, but not limited to: 60 Hz) is high. The still image P3, the moving image P4, and the still image P5 are located in the display area Ron, the display area Roff, and the display area Ron, respectively. The electronic device 1 can determine whether to turn on or off the plurality of second transistors T2 of the plurality of pixel structures PX according to the plurality of update frequencies of the plurality of images P3, P4, P5. Specifically, the plurality of first pixel structures PX in the upper display area Ron of FIG. 16 and the plurality of first pixel structures PX in the lower display area Ron of FIG. 16 are used to display the first image P3 and the One image P5. Judging that when the update frequency of the first images P3, P5 is equal to or lower than the first preset frequency (for example, but not limited to: 5 Hz), the plurality of second pixels of the plurality of first pixel structures PX located in the display area Ron The transistor T2 is turned on to improve the flicker problem. Judging that when the update frequency of the second image P4 is equal to or higher than the second preset frequency (for example, but not limited to: 60 Hz), the plurality of second transistors T2 of the plurality of second pixel structures PX in the display area Ron Off to save power and take into account the improvement of the flicker problem.

17 is an electronic device using the semiconductor substrate according to any embodiment of the present invention. Referring to FIG. 17, the electronic device 1 includes a display panel having a semiconductor substrate 100. The electronic device 1 determines whether to turn on or off the plurality of second transistors T2 of the plurality of pixel structures PX according to the characteristics of the image P6 of the plurality of pixel structures PX. For example, when the electronic device 1 is in the third application scenario, the image P6 of the display panel of the electronic device 1 is a static image with white text on a black background. The plurality of pixel structures PX in the display area Roff of the display panel of the electronic device 1 are used to display the image P6. At this time, the second transistor T2 of all the pixel structures PX can be turned off without charging the storage capacitors Cst of the plurality of pixel structures PX of the display area Roff, and the electronic device 1 can save power. At the same time, the display panel of the electronic device 1 will not cause the problems of flicker and insufficient charging rate.

FIG. 18 shows a pixel structure PX according to an embodiment of the present invention. The pixel structure PX depicted in FIG. 18 is the actual layout of the pixel structure PX in FIG. 1. FIG. 19 is a schematic cross-sectional view of the semiconductor substrate 100 corresponding to the line I-І' of FIG. 18. FIG. 20 is a schematic cross-sectional view of the semiconductor substrate 100 corresponding to the П-П' line in FIG. 18. 21 is a schematic cross-sectional view of the semiconductor substrate 100 corresponding to the Ш-Ш' line in FIG. 18. It should be noted that FIG. 18 omits the light shielding layer 120 of FIGS. 19 to 21.

18 to 21, the semiconductor substrate 100 includes a base 110 and a pixel structure PX disposed on the base 110. The substrate 110 is mainly used to carry the pixel structure PX, and its material can be glass, quartz, organic polymer, or opaque/reflective materials (for example: conductive materials, wafers, ceramics, or other applicable Materials), or other applicable materials.

In this embodiment, the semiconductor substrate 100 may selectively include the light shielding layer 120. The light shielding layer 120 is disposed on the substrate 110. For example, in this embodiment, the material of the light shielding layer 120 may be a metal material, an alloy, a nitride of a metal material, an oxide of a metal material, an oxynitride of a metal material, or a combination thereof. However, the present invention is not limited to this. According to other embodiments, the material of the light shielding layer 120 may also be other conductive materials that can block light, non-conductive materials that can block light, or a combination thereof.

In this embodiment, the semiconductor substrate 100 may optionally include insulating layers 132 and 134 disposed on the light shielding layer 120. For example, in this embodiment, the materials of the insulating layers 132 and 134 may be inorganic materials (eg, silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials), organic materials, or the above Of the combination.

The semiconductor substrate 100 includes a semiconductor layer. The semiconductor layer includes a plurality of semiconductor patterns T1d, T2d, and T3d of the first transistor T1, the second transistor T2, and the third transistor T3. In this embodiment, the semiconductor patterns T1d, T2d, and T3d can be selectively disposed on the insulating layer 134. The semiconductor pattern T1d of the first transistor T1 and the semiconductor pattern T2d of the second transistor T2 may be selectively directly connected. The semiconductor pattern T3d of the third transistor T3 is separated from the semiconductor pattern T1d of the first transistor T1 and the semiconductor pattern T2d of the second transistor T2. For example, in this embodiment, the semiconductor pattern T1d of the first transistor T1 may be substantially inverted U-shaped, the semiconductor pattern T2d of the second transistor T2 may be substantially U-shaped, and the third transistor T3 The semiconductor pattern T3d may be substantially inverted L-shaped, wherein the T-shaped semiconductor pattern T2d is generally located between the inverted U-shaped semiconductor pattern T1d and the inverted L-shaped semiconductor pattern T3d, but the present invention does not Limited.

In this embodiment, the light shielding layer 120 may shield (or may overlap) the plurality of semiconductor patterns T1d, T2d, and T3d of the first transistor T1, the second transistor T2, and the third transistor T3 to prevent and /Or reduce the generation of light leakage. However, the present invention is not limited to this, and according to other embodiments, the arrangement of the light shielding layer 120 may also be omitted.

In this embodiment, the semiconductor patterns T1d, T2d, and T3d may have a single-layer or multi-layer structure. For example, in this embodiment, the material of the semiconductor patterns T1d, T2d, T3d may include polysilicon. However, the present invention is not limited to this. According to other embodiments, the materials of the semiconductor patterns T1d, T2d, T3d may also include amorphous silicon, microcrystalline silicon, single crystal silicon, organic semiconductor materials, oxide semiconductor materials (for example: indium zinc Oxide, indium gallium zinc oxide, or other suitable materials, or a combination of the above), or other suitable materials, or containing dopants in the above materials, or a combination of the above.

It is worth noting that in this embodiment, the data line DL extends in the first direction D1, the scan line GL extends in the second direction D2, and at least a portion of the semiconductor pattern T2d of the second transistor T2 is The fourth direction D4 in which the first direction D1 and the second direction D2 intersect extends. The semiconductor pattern T2d extending in the fourth direction D4 helps to set the second transistor T2 as a switch of the storage capacitor Cst in a limited area.

In this embodiment, the semiconductor substrate 100 further includes an insulating layer 140 disposed on the semiconductor patterns T1d, T2d, and T3d. For example, in this embodiment, the material of the insulating layer 140 may be an inorganic material (for example: silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two materials), an organic material, or a combination thereof .

In this embodiment, the semiconductor substrate 100 further includes a first metal layer. The first metal layer may selectively include the scan line GL, the control terminal T1c of the first transistor T1, the control terminal T2c of the second transistor T2, the control terminal T3c of the third transistor T3, and the common electrode 190. The control terminal T1c of the first transistor T1, the control terminal T2c of the second transistor T2, and the control terminal T3c of the third transistor T3 are respectively connected to the semiconductor pattern T1d of the first transistor T1 and the semiconductor pattern T2d of the second transistor T2 The semiconductor pattern T3d of the third transistor T3 overlaps.

The control terminal T1c of the first transistor T1 is electrically connected to the scanning line GL. For example, in this embodiment, the control terminal T1c of the first transistor T1 may be two places where the scan line GL crosses the semiconductor pattern T1d; that is, in this embodiment, the first transistor T1 may It is a double-gate transistor, but the invention is not limited to this. The control terminal T3c of the third transistor T3 is electrically connected to the scanning line GL. For example, in this embodiment, the control terminal T3c of the third transistor T3 may be a place where the scanning line GL crosses the semiconductor pattern T3d; that is, in this embodiment, the third transistor T3 may It is a single gate transistor, but the invention is not limited to this.

The control terminal T2c of the second transistor T2 is separated from the scanning line GL. For example, the control terminal T2c of the second transistor T2 may be a strip-shaped conductive pattern located beside the scan line GL, but the invention is not limited thereto. It is worth noting that, in this embodiment, the control terminal T2c of the second transistor T2 extends in the third direction D3, where the third direction D3 intersects the first direction D1, the second direction D2, and the fourth direction D4. That is, the control terminal T2c of the second transistor T2 crosses the semiconductor pattern T2d of the second transistor T2 and is not parallel to the data line DL and the scanning line GL. This helps to set the second transistor T2 as a switch of the storage capacitor Cst in a limited area.

In this embodiment, the extending direction of the scanning line GL (ie, the second direction D2) and the extending direction of the control terminal T2c of the second transistor T2 (ie, the third direction D3) have an angle θ. Preferably, 0 ^o <θ<60 ^o , but the invention is not limited to this. The extending direction of the scanning line GL (ie, the second direction D2) and the extending direction of the semiconductor pattern T2d of the second transistor T2 (ie, the fourth direction D4) have an angle Φ. Preferably, 0 ^o <Φ<60 ^o , but the invention is not limited to this. The extending direction of the control terminal T2c of the second transistor T2 (ie, the third direction D3) and the extending direction of the semiconductor pattern T2d of the second transistor T2 (ie, the fourth direction D4) have an angle α. Preferably, 0 ^o <α≦90 ^o , but the invention is not limited to this.

The common electrode 190 has a reference potential, which may be a ground potential, a fixed potential, or a variable potential. The common electrode 190 may be at least a part of the electrode Ast2 (marked in FIG. 1) of the storage capacitor Cst. The common electrode 190 is separated from the scan line GL and the control terminal T2c of the second transistor T2. For example, in this embodiment, the control terminal T2c of the second transistor T2 may be located between the scan line GL and the common electrode 190. In other words, a vertical projection of a portion of the second transistor T2 (for example: the control terminal T2c) on the substrate 110 is located on a portion of a vertical projection of the scan line GL on the substrate 110 and the storage capacitor Cst (for example: the common electrode 190 ) Between a vertical projection on the substrate 110.

In this embodiment, the materials of the scanning line GL, the control terminal T1c of the first transistor T1, the control terminal T2c of the second transistor T2, the control terminal T3c of the third transistor T3 and the common electrode 190 are metal as an example . However, the present invention is not limited to this. According to other embodiments, the scanning line GL, the control terminal T1c of the first transistor T1, the control terminal T2c of the second transistor T2, the control terminal T3c of the third transistor T3, and the common electrode 190 The material can also be other conductive materials. For example: alloys, nitrides of metal materials, oxides of metal materials, oxynitrides of metal materials, or stacked layers of metal materials and other conductive materials.

In this embodiment, the semiconductor substrate 100 further includes an insulating layer 150 disposed on the scanning line GL, the control terminal T1c of the first transistor T1, the control terminal T2c of the second transistor T2, and the control terminal T3c of the third transistor T3 And on the common electrode 190. For example, in this embodiment, the material of the insulating layer 150 may be an inorganic material (eg, silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials), an organic material, or a combination thereof .

In this embodiment, the semiconductor substrate 100 further includes a second metal layer, which is disposed on the insulating layer 150. In this embodiment, the second conductive layer may selectively include the data line DL, the capacitance control line CL, the first end T1a and the second end T1b of the first transistor T1, and the first end T2a of the second transistor T2 And the second end T2b and the first end T3a and the second end T3b of the third transistor T3.

The data lines DL and the scanning lines GL are interleaved. The data line DL extends in the first direction D1, and the scan line GL extends in the second direction D2, where the first direction D1 and the second direction D2 are staggered. For example, in this embodiment, the first direction D1 and the second direction D2 can be selectively perpendicular, but the invention is not limited thereto. In this embodiment, the capacitance control line CL can be selectively disposed in parallel with the data line DL, but the invention is not limited to this. According to other embodiments, the capacitance control line CL may also be provided in other ways, for example, the capacitance control line CL may also be provided in parallel with the scanning line GL.

The first end T1a of the first transistor T1 is electrically connected to the data line DL. For example, in this embodiment, the first end T1a of the first transistor T1 may be a place where the data line DL overlaps the semiconductor pattern T1d, but the invention is not limited thereto. The first end T1a and the second end T1b of the first transistor T1 are electrically connected to two different places of the semiconductor pattern T1c of the first transistor T1, respectively. Specifically, in this embodiment, the first end T1a of the first transistor T1 can be electrically connected to the semiconductor pattern T1d of the first transistor T1 through the contact windows 142, 152 of the insulating layers 140, 150. The second end T1b of the crystal T1 may be electrically connected to the semiconductor pattern T1d of the first transistor T1 through the contact windows 144, 154 of the insulating layers 140, 150.

The first end T2a of the second transistor T2 and the second end T1b of the first transistor T1 are electrically connected. For example, in this embodiment, the first end T2a of the second transistor T2 and the second end T1b of the first transistor T1 may be two parts of the same first island-like pattern. The first end T2a and the second end T2b of the second transistor T2 are electrically connected to two different regions of the semiconductor pattern T2d. For example, in this embodiment, the first end T2a of the second transistor T2 may be electrically connected to the semiconductor pattern T2d of the second transistor T2 through the contact windows 144, 154 of the insulating layers 140, 150. The second end T2b of the crystal T2 may be electrically connected to the semiconductor pattern T2d of the second transistor T2 through the contact windows 149, 159 of the insulating layers 140, 150.

The second terminal T2b of the second transistor T2 is electrically connected to the storage capacitor Cst. For example, in this embodiment, the second metal layer of the semiconductor substrate 100 further includes a conductive pattern 155 that overlaps with the common electrode 190 of the first metal layer. The conductive pattern 155 of the second metal layer may be at least a part of the electrode Ast1 (marked in FIG. 1) of the storage capacitor Cst. The second terminal T2b of the second transistor T2 is connected to the conductive pattern 155 of the storage capacitor Cst. In this embodiment, the second end T2b of the second transistor T2 and the conductive pattern 155 of the storage capacitor Cst may be two parts of the same second island-shaped pattern, but the invention is not limited thereto.

The first terminal T3a of the third transistor T3 is electrically connected to the capacitance control line CL. For example, in this embodiment, the first end T3a of the third transistor T3 may be a portion where the capacitance control line CL overlaps the semiconductor pattern T3d. The second terminal T3b of the third transistor T3 is electrically connected to the control terminal T2c of the second transistor T2. For example, in this embodiment, the second terminal T3b of the third transistor T3 may be electrically connected to the control terminal T2c of the second transistor T2 through the contact window 157 of the insulating layer 150. The first end T3a and the second end T3b of the third transistor T3 are electrically connected to different two regions of the semiconductor pattern T3c, respectively. For example, the first end T3a of the third transistor T3 can be electrically connected to the semiconductor pattern T3d through the contact windows 146, 156 of the insulating layers 140, 150, and the second end T3b of the third transistor T3 can pass through the insulating layer 140 The contact windows 148, 158 of 150 are electrically connected to the semiconductor pattern T3d.

It is worth noting that in this embodiment, a vertical projection of the second transistor T2 on the substrate 110 is a vertical projection of the first transistor T1 on the substrate 110 and a third projection of the third transistor T3 on the substrate 110 Between vertical projections. In more detail, the vertical projection of the control terminal T2c of the second transistor T2 on the substrate 110 is located on the vertical projection of the second terminal T1b of the first transistor T1 on the substrate 110 and the second terminal T3b of the third transistor T3 Between the vertical projections on the substrate 110.

In this embodiment, the semiconductor substrate 100 further includes insulating layers 162, 164, which are disposed on the data line DL, the capacitance control line CL, the first terminal T1a and the second terminal T1b of the first transistor T1, and the second transistor T2. The first end T2a and the second end T2b, the first end T3a and the second end T3b of the third transistor T3, and the conductive pattern 155 are formed. For example, in this embodiment, the materials of the insulating layers 162 and 164 may be inorganic materials (for example: silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials), organic materials, or the above Of the combination.

In this embodiment, the semiconductor substrate 100 further includes a first transparent conductive layer, which is disposed on the insulating layer 164. The first transparent conductive layer includes a common electrode 180. A part of the common electrode 180 of the first transparent conductive layer overlaps with the common electrode 190 of the first metal layer and is electrically connected to each other. For example, the common electrode 180 of the first transparent conductive layer may be electrically connected to the common electrode 190 of the first metal layer through the contact windows 162c, 164c, 153 of the insulating layers 162, 164, 150. The common electrode 180 and the common electrode 190 that are electrically connected to each other can be regarded as an electrode Ast2 (marked in FIG. 1) of the storage capacitor Cst. In this embodiment, the material of the first transparent conductive layer may include metal oxides, such as indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium germanium zinc oxide, or other suitable Oxide, or a stacked layer of at least two of the above, but the invention is not limited thereto.

In this embodiment, the semiconductor substrate 100 further includes an insulating layer 170, which is disposed on the common electrode 180. For example, in this embodiment, the material of the insulating layer 170 may be an inorganic material (eg, silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials), an organic material, or a combination thereof .

In this embodiment, the semiconductor substrate 100 further includes a second transparent conductive layer, which is disposed on the insulating layer 170. The second transparent conductive layer includes pixel electrodes 172. The pixel electrode 172 is electrically connected to the second end T2b of the second transistor T2. Specifically, in this embodiment, the pixel electrode 172 may be electrically connected to the second end T2b of the second transistor T2 through the contact windows 162a, 164a, 170a of the insulating layers 162, 164, 170. The pixel electrode 172 overlaps with the common electrode 180. The voltage difference between the pixel electrode 172 and the common electrode 180 is used to drive a display medium (for example, but not limited to: liquid crystal). The pixel electrode 172, the common electrode 180, and the display medium (not shown) may form a display medium capacitance Clc. In other words, the pixel electrode 172 and the common electrode 180 may be the two electrodes Alc1 and Alc2 of the display dielectric capacitor Clc, respectively.

In this embodiment, the second transparent conductive layer further includes conductive patterns 174. The conductive pattern 174 is separated from the pixel electrode 172. The conductive patterns 174 overlap and are electrically connected to the second end T2b of the second transistor T2. The conductive pattern 174 also overlaps the conductive pattern 155 of the second metal layer. In this embodiment, the conductive pattern 174 may be electrically connected to the second end T2b of the second transistor T2 and the conductive pattern 155 of the second metal layer through the contact windows 162b, 164b, 170b of the insulating layers 162, 164, 170. The conductive pattern 174 of the second transparent conductive layer and the conductive pattern 155 of the second metal layer electrically connected to each other can be regarded as another electrode Ast1 of the storage capacitor Cst (marked in FIG. 1 ). In summary, in this embodiment, the storage capacitor Cst may include common electrodes 180, 190 electrically connected to each other, conductive patterns 174, 155 electrically connected to each other, and sandwiched between the common electrodes 180, 190 and the conductive pattern 174, The insulating layer 150, 162, 164, 170 between 155.

In this embodiment, in order to enable the storage function of the storage capacitor Cst to significantly improve the aforementioned flicker problem, it is preferable that the storage capacitor Cst has a capacitance value greater than half of the display dielectric capacitor Clc, but the invention does not This is the limit.

，第二電晶體T2的半導體圖案T2d具有通道寬長度

，

，但本發明不以此為限。第三電晶體T3所需的充電量很小，第三電晶體T3的設計以防止漏電為佳。舉例而言，在本實施例中，第三電晶體的一半導體圖案Td3具有一通道寬長比

，而

，但本發明不以此為限。In addition, in this embodiment, the capacitance value of the storage capacitor Cst is greater than the display medium capacitance Clc, so the second transistor T2 used to charge the storage capacitor Cst has a better charging capability than the first transistor T2 used to charge the display medium capacitance Clc The charging ability of the transistor T1 is better. In other words, the on current (Ion) of the second transistor T2 is preferably greater than the on current of the first transistor T1. For example, in this embodiment, the semiconductor pattern T1d of the first transistor T1 has a channel width-to-length ratio

, The semiconductor pattern T2d of the second transistor T2 has a channel width length

,

, But the invention is not limited to this. The amount of charge required for the third transistor T3 is very small, and the design of the third transistor T3 is better to prevent leakage. For example, in this embodiment, a semiconductor pattern Td3 of the third transistor has a channel width-to-length ratio

,and

, But the invention is not limited to this.

In summary, in an embodiment of the present invention, whether to turn on the second transistor to charge the storage capacitor can be determined according to the gray level value to be displayed and/or the update frequency of the image to be displayed. In this way, the display panel using the semiconductor substrate according to an embodiment of the present invention can improve the flicker problem and achieve the power saving effect.

Although the present invention has been disclosed as above with examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to the scope defined in the appended patent application.

10, 10’‧‧‧ display panel 100, 100A, 100B ‧‧‧ semiconductor substrate 110‧‧‧ base 120‧‧‧ shading layer 132, 134, 140, 150, 162, 164, 170 142, 144, 146, 148, 149, 152, 153, 154, 156, 157, 158, 159, 162a, 162b, 162c, 164a, 164b, 164c, 170a, 170b 155, 174‧‧‧ conductive pattern 172‧‧‧ pixel electrode 180, 190‧‧‧ common electrode Ast1, Ast2, Acl1, Acl2 Clc‧‧‧display dielectric capacitance Cst‧‧‧storage capacitor CL, CL1, CL2‧‧‧Capacitance control line DL, DL1, DL2 ‧‧‧ data cable D1, D2, D3, D4 ‧‧‧ direction GL, GL1, GL2, GL3 ‧‧‧ scanning line L0, L20, L192, L128, L255 P1, P2, P3, P4, P5, P6 PX, PX1～PX3, PX’1, PX’2, PX’, PX-1, PX’-1 pixel structure Ron, Roff‧‧‧ display area S1, S2‧‧‧curve T1‧‧‧ First transistor T1a, T2a, T3a ‧‧‧ first end T1b, T2b, T3b ‧‧‧ second end T1c, T2c, T3c ‧‧‧ control terminal T1d, T2d, T3d ‧‧‧ semiconductor pattern T2‧‧‧second transistor T3‧‧‧third transistor t1, t2, t3 ‧‧‧ time interval VCL‧‧‧Control signal VDL, VDL1, VDL2 ‧‧‧ data signal VGL, VGL1, VGL2, VGL3 ‧‧‧ scanning signal Vch‧‧‧High control potential Vcl‧‧‧low control potential Vdh‧‧‧High data potential Vdl‧‧‧Low data potential Vgh‧‧‧High scan potential Vgl‧‧‧low scan potential VL20, VL128, VL192, VL255 ‧‧‧ root mean square voltage value Ι-І’, П-П’, Ш-Ш’ cut line θ, Φ, α ‧‧‧ included angle

FIG. 1 is a schematic diagram of a pixel structure PX according to the first embodiment of the invention. 2 is a schematic top view of the semiconductor substrate according to the first embodiment of the invention. FIG. 3 shows scan signals VGL1, scan signals VGL2, and scan signals of scan line GL1, scan line GL2, scan line GL3, data line DL, and data control line CL of FIG. 2 at respective time intervals t1, t2, and t3 VGL3, data signal VDL and control signal VCL. 4 is a relationship curve S1 of the root mean square voltage value (V) of the data signal VDL of the pixel structure PX and the brightness (cd/m ² ) of the pixel structure PX according to the first embodiment of the present invention. 5 is the normalized change rate of the root mean square voltage value (V) of the data signal VDL of the pixel structure PX and the brightness of the pixel structure PX to the root mean square voltage value of the data signal VDL according to the first embodiment of the invention的 Relation curve S2. 6 is a schematic diagram of a display panel according to a first embodiment of the invention. 7 is a schematic diagram of a pixel structure PX' according to a second embodiment of the invention. 8 is a schematic top view of a semiconductor substrate according to a second embodiment of the invention. 9 shows the scan signal VGL, the data signal VDL1, the data signal VDL2, and the control signal of the scan line GL, the data line DL1, the data line DL2, the data line DL2, the capacitor control line CL1, and the capacitor control line CL2 of FIG. 8 respectively at a time interval t1 VCL1, and control signal VCL2. 10 is a schematic diagram of a display panel according to a second embodiment of the invention. FIG. 11 is a schematic diagram of a pixel structure PX-1 according to a third embodiment of the invention. 12 is a schematic diagram of a pixel structure PX'-1 according to the fourth embodiment of the present invention. 13 is a schematic diagram of a semiconductor substrate 100A according to a fifth embodiment of the invention. 14 is a schematic diagram of a semiconductor substrate 100B according to a sixth embodiment of the invention. 15 is an electronic device using a semiconductor substrate according to any embodiment of the present invention. 16 is an electronic device using a semiconductor substrate according to any embodiment of the present invention. 17 is an electronic device using the semiconductor substrate according to any embodiment of the present invention. FIG. 18 shows a pixel structure PX according to an embodiment of the present invention. FIG. 19 is a schematic cross-sectional view of the semiconductor substrate 100 corresponding to the line Ι-І' of FIG. 18. 20 is a schematic cross-sectional view of the semiconductor substrate 100 corresponding to the cross-sectional line П-П' of FIG. 18. FIG. 21 is a schematic cross-sectional view of the semiconductor substrate 100 corresponding to the line Ш-Ш' of FIG. 18.

155, 174‧‧‧ conductive pattern

172‧‧‧ pixel electrode

180, 190‧‧‧ common electrode

CL‧‧‧capacitor control line

DL‧‧‧Data cable

D1, D2, D3, D4 ‧‧‧ direction

GL‧‧‧scan line

PX‧‧‧ pixel structure

T1‧‧‧ First transistor

T1a, T2a, T3a ‧‧‧ first end

T1b, T2b, T3b ‧‧‧ second end

T1c, T2c, T3c ‧‧‧ control terminal

T1d, T2d, T3d ‧‧‧ semiconductor pattern

T2‧‧‧second transistor

T3‧‧‧third transistor

I-I’, II-II’, III-III’ cut line

θ, Φ, α ‧‧‧ included angle

Claims (21)

A semiconductor substrate, including: A base A data line, a scanning line and a capacitor control line are arranged on the substrate; A first transistor, wherein a first terminal of the first transistor is electrically connected to the data line, and a control terminal of the first transistor is electrically connected to the scan line; A pixel electrode electrically connected to a second end of the first transistor; A second transistor, wherein a first end of the second transistor is electrically connected to the second end of the first transistor; A storage capacitor electrically connected to a second end of the second transistor; and A third transistor, wherein a first terminal of the third transistor is electrically connected to the capacitor control line, a control terminal of the third transistor is electrically connected to the scan line, and the third transistor A second terminal is electrically connected to a control terminal of the second transistor. The semiconductor substrate as described in item 1 of the patent application range, wherein a vertical projection of the second transistor on the substrate is located on a vertical projection of the first transistor on the substrate and the third transistor on the substrate Between a vertical projection on the. The semiconductor substrate according to item 1 of the patent application scope, wherein a vertical projection of the second transistor on the substrate is a vertical projection of the scan line on the substrate and a vertical projection of the storage capacitor on the substrate Between projections. The semiconductor substrate according to item 1 of the patent application scope, wherein the data line extends in a first direction, the scan line extends in a second direction, and the control end of the second transistor is in a third direction Extend, and the third direction intersects the first direction and the second direction. The semiconductor substrate as described in item 4 of the patent application range, wherein the second direction and the third direction have an angle θ, and 0 ^o <θ<60 ^o . The semiconductor substrate as described in item 4 of the patent application scope, wherein the second transistor includes a semiconductor pattern extending in a fourth direction, and the third direction and the first direction, the second direction, and the first Staggered in four directions. The semiconductor substrate as described in item 6 of the patent application range, wherein the second direction and the fourth direction have an angle Φ, and 0 ^o <Φ<60 ^o . The semiconductor substrate as described in item 6 of the patent application range, wherein the third direction and the fourth direction have an angle α, and 0 ^o <α≤90 ^o . The semiconductor substrate according to item 1 of the patent application scope, wherein the storage capacitor includes: An insulating layer disposed on the second end of the second transistor, wherein the pixel electrode is disposed on the insulating layer; and A conductive pattern, disposed on the insulating layer, separated from the pixel electrode, and electrically connected to the second end of the second transistor through a contact window of the insulating layer, wherein the conductive pattern and the second The second ends of the transistors overlap. The semiconductor substrate as described in item 1 of the patent application scope further includes: A common electrode disposed on the substrate, wherein the common electrode overlaps the pixel electrode to form a display medium capacitor; The capacitance value of the storage capacitor is greater than half the capacitance value of the display medium capacitance. The semiconductor substrate as described in item 1 of the patent application range, wherein a semiconductor pattern of the first transistor has a channel width-to-length ratio

, A semiconductor pattern of the second transistor has a wide channel length

,and

. The semiconductor substrate as described in item 11 of the patent application range, wherein a semiconductor pattern of the third transistor has a channel width-to-length ratio

,and

. A driving method for driving a semiconductor substrate, wherein the semiconductor substrate includes a plurality of pixel structures, each of the pixel structures includes a data line, a scanning line, a capacitance control line, a first transistor, A pixel electrode, a second transistor, and a storage capacitor, a first terminal of the first transistor is electrically connected to the data line, and a control terminal of the first transistor is electrically connected to the scan line, A second end of the first transistor is electrically connected to the pixel electrode, a first end of the second transistor is electrically connected to the second end of the first transistor, the second transistor A control terminal is electrically connected to the capacitor control line, a second terminal of the second transistor is electrically connected to the storage capacitor, and the driving method includes: According to at least one data signal of at least one data line of at least one of the pixel structures, it is determined whether at least one second transistor of the at least one of the pixel structures is turned on or off. The driving method according to item 13 of the patent application scope, wherein the at least one of the at least one of the pixel structures is determined according to the at least one data signal of the at least one data line of the at least one of the pixel structures The step of turning on or turning off the at least one second transistor includes: Determine when the gray level value of the at least one data signal of the at least one data line of the at least one of the pixel structures is between a first preset value and a second preset value The at least one second transistor of the at least one of the pixel structures is turned on, wherein the first preset value is smaller than the second preset value. The driving method according to item 13 of the patent application scope, wherein the at least one of the at least one of the pixel structures is determined according to the at least one data signal of the at least one data line of the at least one of the pixel structures The step of turning on or turning off the at least one second transistor includes: Judging that when the gray level value of the at least one data signal of the at least one data line of the at least one of the pixel structures is less than a first predetermined value, the At least one second transistor is turned off. The driving method according to item 13 of the patent application scope, wherein the at least one of the at least one of the pixel structures is determined according to the at least one data signal of the at least one data line of the at least one of the pixel structures The step of turning on or turning off the at least one second transistor includes: Judging that when the gray level value of the at least one data signal of the at least one data line of the at least one of the pixel structures is greater than a second preset value, the At least one second transistor is turned off. The driving method as described in item 13 of the patent application, wherein the pixel structures are used to display multiple images, and the driving method further includes: According to the characteristics of the images, the second transistors of the pixel structures are turned on or off. The driving method as described in item 17 of the patent application scope, wherein the images include a first image and a second image, and the pixel structures include a plurality of first images for displaying the first image A pixel structure and a plurality of second pixel structures for displaying the second image, and according to the characteristics of the images of the pixel structures, the second power of the pixel structures are determined The steps to turn the crystal on or off include: Judging that when the first image includes a gray frame and a white text interspersed in the gray frame, the second transistors of the first pixel structure are turned off; and It is determined that when the second image includes a full-gray image, the second transistors of the second pixel structure are turned on. The driving method as described in Item 17 of the patent application range, wherein the step of determining whether to turn on or off the second transistors of the pixel structures according to the characteristics of the images of the pixel structures includes : According to the multiple update frequencies of the images, it is determined whether the second transistors of the pixel structures are turned on or off. The driving method according to item 19 of the patent application scope, wherein the images include a first image and a second image, and the pixel structures include a plurality of first images for displaying the first image A pixel structure and a plurality of second pixel structures for displaying the second image, and according to the update frequencies of the images of the pixel structures, the plurality of second structures of the pixel structures are determined The steps to turn the transistor on or off include: Judging that when an update frequency of the first image is equal to or lower than the first preset frequency, the second transistors of the first pixel structures are turned on; and Judging that when an update frequency of the second image is equal to or higher than a second preset frequency, the second transistors of the second pixel structures are turned off, wherein the first preset frequency is higher than the The second preset frequency. The driving method as described in item 13 of the patent application range, wherein each of the plurality of data signals of the plurality of data lines of the pixel structure is between a high data potential Vdh and a low data potential Vdl, the pixels Each of the multiple scan signals of the multiple scan lines of the structure is between a high scan potential Vgh and a low scan potential Vgl, and each of the multiple control signals of the multiple capacitor control lines of the pixel structures is between one High control potential Vch and a low control potential Vcl, Vdh<Vch<Vgh, and Vgl<Vcl<Vdl.

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