TWI679626B - Display device - Google Patents

Abstract

A display device includes a substrate, a first data line, a scan line, a first sub-pixel, a passivation layer, and a common electrode. The first sub-pixel includes a first main driving element, a first sub-driving element, a first capacitor electrode, and a first pixel electrode. The first main driving element includes a first main gate, a first main channel layer, a first main source, and a first main drain. The first auxiliary driving element includes a first auxiliary gate, a first auxiliary channel layer, a first auxiliary source, and a first auxiliary drain. The first capacitor electrode is electrically connected to the first main drain and the first secondary source. The first pixel electrode is electrically connected to the first secondary drain electrode. A first main capacitor is provided between the common electrode and the first capacitor electrode. A first auxiliary capacitor is provided between the common electrode and the first pixel electrode.

Description

Display device

The present invention relates to a display device, and more particularly to a display device with a common electrode overlapping a capacitor electrode and a pixel electrode.

In recent years, with the continuous advancement of display technology, viewers' requirements for the resolution of display devices have become higher and higher. In order to improve the resolution of the display device, the size of each sub-pixel in the display device must be reduced. However, small-sized sub-pixels usually have relatively small storage capacitors, which are prone to problems such as large feed-through voltage or crosstalk, and sometimes even leakage.

Reducing the frame rate can reduce the power consumption of the display device, thereby increasing the usage time of the display device. However, if the storage capacitor in the display device is too small or the display device leaks electricity, it is easy to reduce the number of frames due to insufficient storage capacitor capacity to maintain the voltage. Therefore, in order to increase the use time of a high-resolution display device, there is an urgent need to improve the problem of leakage of small-sized sub-pixels.

The invention provides a display device, which can improve the problem of leakage.

An embodiment of the present invention provides a display device including a substrate, a first data line, a scan line, a first sub-pixel, a passivation layer, and a common electrode. The first data line and the scan line are located on the substrate. The first sub-pixel is located on the substrate. The first sub-pixel includes a first main driving element, a first sub-driving element, a first capacitor electrode, and a first pixel electrode. The first main driving element includes a first main gate, a first main channel layer, a first main source, and a first main drain. The first main gate is electrically connected to the scan line. The first main channel layer overlaps the first main gate. The first main source and the first main drain are electrically connected to the first main channel layer. The first main source is electrically connected to the first data line. The first auxiliary driving element includes a first auxiliary gate, a first auxiliary channel layer, a first auxiliary source, and a first auxiliary drain. The first auxiliary gate is electrically connected to the scanning line. The first secondary channel layer overlaps the first secondary gate. The first secondary source and the first secondary drain are electrically connected to the first secondary channel layer. The first main drain is electrically connected to the first secondary source. The first capacitor electrode is electrically connected to the first main drain and the first secondary source. The first pixel electrode is electrically connected to the first secondary drain electrode. The passivation layer is located on the first main source, the first main drain, the first sub-source, and the first sub-drain. The first capacitor electrode and the first pixel electrode are located on the passivation layer. The common electrode overlaps the first capacitor electrode and the first pixel electrode. A first main capacitor is provided between the common electrode and the first capacitor electrode. A first auxiliary capacitor is provided between the common electrode and the first pixel electrode. The materials of the first capacitor electrode, the first pixel electrode, and the common electrode include a transparent conductive material.

Based on the above, the first sub-source of the first sub-driving element is electrically connected to the first capacitor electrode, and the first sub-drain is electrically connected to the first pixel electrode, whereby the common electrode and the first capacitor electrode The first main capacitor can reduce the first secondary drain and the first The voltage difference between the sub-sources improves the leakage problem, so that the voltage on the first pixel electrode can be maintained even if the voltage is not applied to the scan line (ie, the first main driving element and the first sub driving element are turned off). a period of time. In this way, the energy consumption can be reduced by reducing the number of frames of the display device.

In order to make the above features and advantages of the present invention more comprehensible, embodiments are hereinafter described in detail with reference to the accompanying drawings.

10, 20, 30, 40‧‧‧ display devices

AA‧‧‧Display Area

BM‧‧‧ Black Matrix

CE1‧‧‧first capacitor electrode

CE2‧‧‧Second capacitor electrode

CE3‧‧‧Third capacitor electrode

CF‧‧‧ color conversion element

CM‧‧‧Common electrode

DD‧‧‧Source driving circuit

DL‧‧‧Data Line

DL1‧‧‧The first data line

DL2‧‧‧Second Data Line

DL3‧‧‧Third Data Line

I1‧‧‧first dielectric material layer

I2‧‧‧Second dielectric material layer

N‧‧‧ direction

M‧‧‧Display media layer

MCH1‧‧‧The first main channel layer

MCH2‧‧‧Second main channel layer

MCH3‧‧‧ Third main channel layer

MD1‧‧‧First main drain

MD2‧‧‧Second main drain

MD3‧‧‧ third main drain

MG1‧‧‧First main gate

MG2‧‧‧Second main gate

MG3‧‧‧Third main gate

MS1‧‧‧first main source

MS2‧‧‧Second main source

MS3‧‧‧ Third Primary Source

GD‧‧‧Gate driving circuit

GI‧‧‧Gate insulation

O‧‧‧ opening

PE1‧‧‧first pixel electrode

PE2‧‧‧second pixel electrode

PE3‧‧‧third pixel electrode

PV‧‧‧ passivation layer

PX1‧‧‧Second Sub Pixel

PX2‧‧‧The first sub pixel

PX3‧‧‧ Third Sub Pixel

SB1‧‧‧ substrate

SB2‧‧‧ Opposite substrate

SCH1‧‧‧The first secondary channel layer

SCH2‧‧‧Secondary secondary channel layer

SCH3‧‧‧ third sub-channel level

SD1‧‧‧ First Drain

SD2‧‧‧Second secondary drain

SD3‧‧‧ Third Drain

SG1‧‧‧First secondary gate

SG2‧‧‧Secondary secondary gate

SG3‧‧‧Third secondary gate

SL‧‧‧scan line

SS1‧‧‧First secondary source

SS2‧‧‧Second secondary source

SS3‧‧‧ Third Secondary Source

TH1‧‧‧First through hole

TH2‧‧‧Second through hole

TH3‧‧‧Third through hole

TH4‧‧‧Fourth through hole

TH5‧‧‧Fifth through hole

TH6‧‧‧Sixth through hole

U‧‧‧ Insulation

FIG. 1A is a schematic top view of a display device according to an embodiment of the invention.

Fig. 1B is a schematic cross-sectional view taken along the line aa 'of Fig. 1A.

Fig. 1C is a schematic cross-sectional view taken along the line bb 'of Fig. 1A.

FIG. 2 is a schematic top view of a display device according to an embodiment of the invention.

3A is a schematic top view of a display device according to an embodiment of the invention.

Fig. 3B is a schematic cross-sectional view taken along the line aa 'in Fig. 3A.

Fig. 3C is a schematic cross-sectional view taken along the line bb 'of Fig. 3A.

FIG. 4 is a schematic top view of a display device according to an embodiment of the invention.

FIG. 1A is a schematic top view of a display device according to an embodiment of the invention. Fig. 1B is a schematic cross-sectional view taken along the line aa 'of Fig. 1A. Fig. 1C is a schematic cross-sectional view taken along the line bb 'of Fig. 1A. For convenience of explanation, FIG. 1A omits some components in the display device.

The display device 10 includes a substrate SB1, a first data line DL1, a scan line SL, a first main gate MG1, a first subgate SG1, a first main channel layer MCH1, a first subchannel layer SCH1, and a gate insulating layer GI A first main source MS1, a first main drain MD1, a first sub-source SS1, a first sub-drain SD1, a passivation layer PV, a first capacitor electrode CE1, a first pixel electrode PE1, and a common electrode CM. In this embodiment, the display device 10 further includes a second data line DL2, a third data line DL3, a second main gate MG2, a second sub-gate SG2, a second main channel layer MCH2, and a second sub-channel layer SCH2. , Second main source MS2, second main drain MD2, second secondary source SS2, second secondary drain SD2, second capacitor electrode CE2, second pixel electrode PE2, third main gate electrode MG3, first Three secondary gates SG3, third primary channel layer MCH3, third secondary channel layer SCH3, third primary source MS3, third primary drain MD3, third secondary source SS3, third secondary drain SD3, third The capacitor electrode CE3, the third pixel electrode PE3, the insulating layer U, the first dielectric material layer I1, the display medium layer M, the counter substrate SB2, the black matrix BM, and the color conversion element CF.

In this embodiment, three sub-pixels of the display device 10 are used as an example for description, in which the first sub-pixel PX1, the second sub-pixel PX2, and the third sub-pixel The element PX3 is located on the substrate SB1. The first sub-pixel PX1 includes a first main driving element MT1, a first sub-driving element ST1, a first capacitor electrode CE1, and a first pixel electrode PE1, and the second sub-pixel PX2 includes a second main driving element MT2, a second The sub driving element ST2, the second capacitor electrode CE2, and the second pixel electrode PE2, and the third sub pixel PX3 includes a third main driving element MT3, a third sub driving element ST3, a third capacitor electrode CE3, and a third pixel Electrode PE3.

The first main gate MG1, the first main channel layer MCH1, the first main source MS1, and the first main drain MD1 constitute a first main driving element MT1. The first sub-gate SG1, the first sub-channel layer SCH1, the first sub-source SS1, and the first sub-drain SD1 constitute a first sub-driving element ST1. The second main gate MG2, the second main channel layer MCH2, the second main source MS2, and the second main drain MD2 constitute a second main driving element MT2. The second sub-gate SG2, the second sub-channel layer SCH2, the second sub-source SS2, and the second sub-drain SD2 constitute a second sub-driving element ST2. The third main gate MG3, the third main channel layer MCH3, the third main source MS3, and the third main drain MD3 constitute a third main driving element MT3. The third sub-gate SG3, the third sub-channel layer SCH3, the third sub-source SS3, and the third sub-drain SD3 constitute a third sub-driving element ST3.

First main driving element MT1, first sub driving element ST1, second main driving element MT2, second sub driving element ST2, third main driving element MT3, third sub driving element ST3, first data line DL1, second The data line DL2, the third data line DL3, and the scan line SL are located on the substrate SB1.

The first main gate MG1 and the first sub-gate SG1 are electrically connected to the scan line SL. The first main channel layer MCH1 and the first sub-channel layer SCH1 overlap the first main gate MG1 and the first sub-gate SG1 in the direction N of the vertical substrate SB1, respectively. The gate insulating layer GI is located between the first main gate MG1 and the first main channel layer MCH1 and between the first sub-gate SG1 and the first sub-channel layer SCH1. The first main source MS1 and the first main drain MD1 are electrically connected to the first main channel layer MCH1. The first main source MS1 is electrically connected to the first data line DL1. The first secondary source SS1 and the first secondary drain SD1 are electrically connected to the first secondary channel layer SCH1. The first main drain MD1 is electrically connected to the first sub-source SD1. In this embodiment, the first main drain MD1 and the first sub-source SD1 are substantially integrally integrated.

The second main gate MG2 and the second sub-gate SG2 are electrically connected to the scan line SL. The second main channel layer MCH2 and the second sub-channel layer SCH2 overlap the second main gate MG2 and the second sub-gate SG2 in the direction N of the vertical substrate SB1, respectively. The gate insulating layer GI is located between the second main gate MG2 and the second main channel layer MCH2 and between the second sub-gate SG2 and the second sub-channel layer SCH2. The second main source MS2 and the second main drain MD2 are electrically connected to the second main channel layer MCH2. The second main source MS2 is electrically connected to the second data line DL2. The second secondary source SS2 and the second secondary drain SD2 are electrically connected to the second secondary channel layer SCH2. The second main drain MD2 is electrically connected to the second sub-source SD2. In this embodiment, the second main drain MD2 and the second sub-source SD2 are substantially integrally integrated.

The third main gate MG3 and the third sub-gate SG3 are electrically connected to the scanning line SL. The third main channel layer MCH3 and the third sub-channel layer SCH3 overlap the third main gate MG3 and the third sub-gate SG3 in the direction N of the vertical substrate SB1, respectively. The gate insulating layer GI is located between the third main gate MG3 and the third main channel layer MCH3, and between the third sub-gate SG3 and the third sub-channel layer SCH3. The third main source MS3 and the third main drain MD3 are electrically connected to the third main channel layer MCH3. The third main source MS3 is electrically connected to the third data line DL3. The third secondary source SS3 and the third secondary drain SD3 are electrically connected to the third secondary channel layer SCH3. The third main drain MD3 is electrically connected to the third sub-source SD3. In this embodiment, the third main drain MD3 and the third sub-source SD3 are substantially integrally integrated.

The first main channel layer MCH1, the first sub channel layer SCH1, the second main channel layer MCH2, the second sub channel layer SCH2, the third main channel layer MCH3, and the third sub channel layer SCH3 are each a single-layer or multi-layer structure, Materials include, for example, amorphous silicon, polycrystalline silicon, microcrystalline silicon, single crystal silicon, organic semiconductor materials, oxide semiconductor materials (such as indium zinc oxide, indium gallium zinc oxide, or other suitable materials or combinations thereof) or other Suitable materials may contain dopants in the above materials or a combination thereof.

First data line DL1, second data line DL2, third data line DL3, scan line SL, first main gate MG1, first sub-gate SG1, second main-gate MG2, second sub-gate SG2, Third main gate MG1, third sub-gate SG3, first main source MS1, first main drain MD1, first sub-source SS1, first sub-drain SD1, second main source MS2, first Two main drain MD2, second secondary source SS2, second secondary drain The electrode SD2, the third main source MS3, the third main drain MD3, the third sub-source SS3, and the third sub-drain SD3 each have a single-layer or multi-layer structure, and materials thereof include, for example, chromium, gold, silver, copper, Metals such as tin, lead, thorium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, alloys of the metals, oxides of the metals, nitrides of the metals, combinations of the materials, or other conductive materials.

In this embodiment, the main driving element and the auxiliary driving element are exemplified by a bottom gate thin film transistor, but the present invention is not limited thereto. In other embodiments, the main driving element and the auxiliary driving element are top-gate thin-film transistors, double-gate thin-film transistors, or other types of thin-film transistors. In other embodiments, each main driving element is not limited to a single thin film transistor, and each main driving element may be formed by connecting more than two thin film transistors in series. Similarly, each auxiliary driving element is not limited to a single thin film transistor, and each auxiliary driving element may be formed by connecting more than two thin film transistors in series.

The passivation layer PV is located at the first main source MS1, the first main drain MD1, the first sub-source SS1, the first sub-drain SD1, the second main source MS2, the second main drain MD2, and the second sub-source SS2, second secondary drain SD2, third main source MS3, third main drain MD3, third secondary source SS3, and third secondary drain SD3.

The insulating layer U is located on the passivation layer PV. The insulating layer U is, for example, an organic insulating layer, but the invention is not limited thereto.

The common electrode CM is located on the insulating layer U. The common electrode CM has a plurality of openings O, and the openings O correspond to the first main drain MD1, the first sub-source SS1, and the first sub-source The positions of the drain SD1, the second main drain MD2, the second secondary source SS2, the second secondary drain SD2, the third main drain MD3, the third secondary source SS3, and the third secondary drain SD3 are set.

The first dielectric material layer I1 is located on the common electrode CM. The first capacitor electrode CE1, the first pixel electrode PE1, the second capacitor electrode CE2, the second pixel electrode PE2, the third capacitor electrode CE3, and the third pixel electrode PE3 are located on the passivation layer PV. In this embodiment, between the first capacitor electrode CE1, the first pixel electrode PE1, the second capacitor electrode CE2, the second pixel electrode PE2, the third capacitor electrode CE3, and the third pixel electrode PE3 and the passivation layer PV An insulating layer U, a first dielectric material layer I1, and a common electrode CM are also sandwiched. In this embodiment, the first capacitor electrode CE1, the first pixel electrode PE1, the second capacitor electrode CE2, the second pixel electrode PE2, the third capacitor electrode CE3, and the third pixel electrode PE3 belong to the same film layer. It can be said that it is formed in the same mask process, thereby reducing the influence of process deviation on optical properties. In this embodiment, the materials of the first capacitor electrode CE1, the first pixel electrode PE1, the second capacitor electrode CE2, the second pixel electrode PE2, the third capacitor electrode CE3, the third pixel electrode PE3, and the common electrode CM Include transparent conductive materials, for example, indium tin oxide, indium zinc oxide, or other metal oxides or a combination of the foregoing materials.

In this embodiment, the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 are located on one side of the scanning line SL, part of the first capacitor electrode CE1, part of the second capacitor electrode CE2, and part of Third capacitor electrode CE3 On the other side of the scan line SL.

The first capacitor electrode CE1 is electrically connected to the first main drain MD1 and the first sub-source SS1. For example, the first capacitor electrode CE1 is electrically connected to the first main drain MD1 and the first sub-source SS1 through the first through hole TH1. The first pixel electrode PE1 is electrically connected to the first secondary drain electrode SD1. For example, the first pixel electrode PE1 is electrically connected to the first secondary drain electrode SD1 through the second through hole TH2.

The second capacitor electrode CE2 is electrically connected to the second main drain MD2 and the second sub-source SS2. For example, the second capacitor electrode CE2 is electrically connected to the second main drain electrode MD2 and the second sub-source electrode SS2 through the third through hole TH3. The second pixel electrode PE2 is electrically connected to the second secondary drain electrode SD2. For example, the second pixel electrode PE2 is electrically connected to the second secondary drain electrode SD2 through the fourth through hole TH4.

The third capacitor electrode CE3 is electrically connected to the third main drain MD3 and the third sub-source SS3. For example, the third capacitor electrode CE3 is electrically connected to the third main drain MD3 and the third sub-source SS3 through the fifth through hole TH5. The third pixel electrode PE3 is electrically connected to the third secondary drain electrode SD3. For example, the third pixel electrode PE3 is electrically connected to the third auxiliary drain electrode SD3 through the sixth through hole TH6.

In this embodiment, the first through hole TH1, the second through hole TH2, the third through hole TH3, the fourth through hole TH4, the fifth through hole TH5, and the sixth through hole TH6 penetrate the passivation layer PV, the insulating layer U, and First dielectric material layer I1. The first through hole TH1, the second through hole TH2, the third through hole TH3, the fourth through hole TH4, the fifth through hole TH5, and the sixth through hole TH6 are provided corresponding to the multiple openings O of the common electrode CM. In this implementation In the formula, the first through hole TH1 and the second through hole TH2 are juxtaposed along the extending direction of the scanning line SL, the third through hole TH3 and the fourth through hole TH4 are juxtaposed along the extending direction of the scanning line SL, and the fifth through hole TH5 and The sixth through hole TH6 is juxtaposed along the extending direction of the scanning line SL, thereby reducing the influence of the aforementioned through hole on the aperture ratio.

In this embodiment, the common electrode CM overlaps the first capacitor electrode CE1, the first pixel electrode PE1, the second capacitor electrode CE2, the second pixel electrode PE2, and the third capacitor electrode CE3 in the direction N of the vertical substrate SB1. And a third pixel electrode PE3. There is a first main capacitor between the common electrode CM and the first capacitor electrode CE1, and the capacitance value is M1. There is a first sub-capacitance between the common electrode CM and the first pixel electrode PE1, and the capacitance value is S1. There is a second main capacitor between the common electrode CM and the second capacitor electrode CE2, and the capacitance value is M2. There is a second auxiliary capacitor between the common electrode CM and the second pixel electrode PE2, and the capacitance value is S2. There is a third main capacitor between the common electrode CM and the third capacitor electrode CE3, and the capacitance value is M3. There is a third auxiliary capacitor between the common electrode CM and the third pixel electrode PE3, and the capacitance value is S3. In this embodiment, S1 = S2 = S3.

By setting the first main capacitor, the second main capacitor, and the third main capacitor, the ability to maintain the voltage on the pixel electrode can be increased. For example, the first main capacitor between the common electrode CM and the first capacitor electrode CE1 can reduce the voltage difference between the first sub-drain SD1 and the first sub-source SS1 and improve the leakage problem, so that even if the scan is stopped, A voltage is applied to the line SL (that is, the first main driving element MT1 and the first sub driving element ST1 are turned off), and the voltage on the first pixel electrode PE1 can be maintained for a period of time. Therefore, the energy consumption can be reduced by reducing the number of frames of the display device 10.

In some embodiments, in order to simultaneously take into account the pixel's anti-leakage effect, charging effect, and optical properties, S1, M1, S2, M2, S3, and M3 satisfy the following relationship: S1 of 10% <S1 of M1 ≦ 60% of S1, 10% of S2 <M2 ≦ 60% of S2, and 10% of S3 <M3 ≦ 60% of S3.

The opposing substrate SB2 is provided facing the substrate SB1. The black matrix BM and the color conversion element CF are located on a substrate SB1. The black matrix BM and the color conversion element CF are provided on the counter substrate SB2. A display medium layer M is interposed between the opposing substrate SB2 and the substrate SB1. The display medium layer M includes, for example, liquid crystal molecules.

In this embodiment, the black matrix BM overlaps the scan line SL, the first capacitor electrode CE1, the first data line DL1, the first main driving element MT1, the first sub driving element ST1, the first Two capacitor electrodes CE2, second data line DL2, second main driving element MT2, second sub driving element ST2, third capacitor electrode CE3, third data line DL3, third main driving element MT3, and third sub driving element ST3 .

In this embodiment, part of the first capacitor electrode CE1, part of the second capacitor electrode CE2, and part of the third capacitor electrode CE3 are parallel to the scan line SL, and the first capacitor electrode CE1, the second capacitor electrode CE2, and the third capacitor electrode CE3 is disposed adjacent to the scan line SL. Therefore, the area of the black matrix BM does not need to be large to cover the first capacitor electrode CE1, the second capacitor electrode CE2, the third capacitor electrode CE3, and the scan line SL, thereby reducing the pair of capacitor electrodes. The effect of pixel aperture ratio. in In this embodiment, part of the first capacitor electrode CE1, part of the second capacitor electrode CE2, and part of the third capacitor electrode CE3 parallel to the scan line SL do not overlap the scan line SL in the direction N of the vertical substrate SB1. Not limited to this. In other embodiments, part of the first capacitor electrode CE1, part of the second capacitor electrode CE2, and part of the third capacitor electrode CE3 parallel to the scan line SL may overlap the scan line SL in the direction N of the vertical substrate SB1, thereby, It can further reduce the influence of the capacitor electrode on the aperture ratio. In this embodiment, the positions of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 correspond to the openings of the black matrix BM.

The color conversion layer CF includes a plurality of different colors, for example, including a red color conversion layer, a green color conversion layer, and a blue color conversion layer. In this embodiment, the first sub-pixel PX1, the second sub-pixel PX2, and the third sub-pixel PX3 correspond to a red color conversion layer, a green color conversion layer, and a blue color conversion layer, respectively. In other words, the first sub-pixel PX1 is a red sub-pixel, the second sub-pixel PX2 is a green sub-pixel, and the third sub-pixel PX3 is a blue sub-pixel.

In this embodiment, by adjusting the capacitance value MM1 of the first main capacitor, the capacitance value M2 of the second main capacitor, and the capacitance value M3 of the third main capacitor, the child pixels of different colors have better optical properties. For example, the capacitance value M1 is not equal to the capacitance value M2 and the capacitance value M3, and the capacitance value M2 is not equal to the capacitance value M3. In this embodiment, in the first main capacitor, the second main capacitor, and the third main capacitor, the materials of the dielectric layer (the first dielectric material layer I1) between the two electrodes (the capacitor electrode and the common electrode) are the same. , The first capacitor electrode CE1, the second capacitor electrode CE2, and the third capacitor can be adjusted by adjusting The area of the capacitor electrode CE3, or openings of different sizes are provided on the first capacitor electrode CE1, the second capacitor electrode CE2, and the third capacitor electrode CE3 to adjust the capacitance value M1, the capacitance value M2, and the capacitance value M3. For example, the ratio of the capacitance value M1, the capacitance value M2, and the capacitance value M3 is equal to the area ratio of the first capacitance electrode CE1, the second capacitance electrode CE2, and the third capacitance electrode CE3, but the invention is not limited thereto.

In some embodiments, since the third sub-pixel PX3 (blue sub-pixel) has a lower brightness and less flicker, the capacitance value M3 of the third main capacitor is adjusted to be smaller than the first main capacitor. The capacitance value M1 and the capacitance value M2 of the second main capacitor can make the third sub-pixel PX3 have a better charging rate. For example, S1, M1, S2, M2, S3, and M3 can satisfy the following relations: S1 of 12% <M1 ≦ 50% of S1, 12% of S2 <M2 ≦ 50% of S2, and 10% of S3 <M3 <40% of S3.

In some implementations, since the second sub-pixel PX2 (green sub-pixel) has a higher brightness and more significant flicker, the capacitance value M2 of the second main capacitor is adjusted to be larger than the capacitance of the first main capacitor. The value M1 and the capacitance value M3 of the third main capacitor are used to improve the flicker problem of the second sub-pixel PX2. For example, S1, M1, S2, M2, S3, and M3 can satisfy the following relationships: 10% S1 <M1 ≦ 50% S1, 12% S2 <M2 ≦ 60% S2, and 10% S3 <M3 ≦ 50% of S3.

FIG. 2 is a schematic top view of a display device according to an embodiment of the invention. It must be noted here that the embodiment of FIG. 2 follows FIGS. 1A to 1C. The component numbers and parts of the embodiments are the same, and the same or similar symbols are used to indicate the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, and details are not described herein.

The main difference between the display device 20 in FIG. 2 and the display device 10 in FIG. 1A is that the display device 20 has a first capacitive electrode CE1, a first pixel electrode PE1, a second capacitive electrode CE2, a second pixel electrode PE2, and a third The capacitor electrode CE3 and the third pixel electrode PE3 are both located on the same side of the scan line.

In this embodiment, the first main capacitor and the first sub-capacitor are juxtaposed along the extension direction of the scan line SL, the second main capacitor and the second sub-capacitor are juxtaposed along the extension direction of the scan line SL, and the third main capacitor and the first The three pairs of capacitors are juxtaposed along the extending direction of the scanning line SL.

In the display device 20, the capacitance value of the first main capacitor M1, the capacitance value of the first sub capacitor S1, the capacitance value of the second main capacitor M2, the capacitance value of the second sub capacitor S2, and the capacitance value of the third main capacitor M3 And the space in which the capacitance value S3 of the third auxiliary capacitor can be adjusted is larger than that of the display device 10. For the rest, please refer to the foregoing embodiments, and details are not described herein.

3A is a schematic top view of a display device according to an embodiment of the invention. Fig. 3B is a schematic cross-sectional view taken along the line aa 'in Fig. 3A. Fig. 3C is a schematic cross-sectional view taken along the line bb 'of Fig. 3A. It must be noted here that the embodiment of FIGS. 3A to 3C follows the component numbers and parts of the embodiments of FIGS. 1A to 1C, and the same or similar reference numerals are used to indicate the same or similar components, and are omitted. A description of the same technical content. For the description of the omitted parts, reference may be made to the foregoing embodiments, and details are not described herein.

The main difference between the display device 30 of FIGS. 3A to 3C and the display device 10 of FIGS. 1A to 1C is that the display device 30 further includes a second dielectric material layer I2.

Referring to FIGS. 3A to 3C, the first capacitor electrode CE1, the second capacitor electrode CE2, and the third capacitor electrode CE3 are located on the insulation layer U. The first dielectric material layer I1 is located on the first capacitor electrode CE1, the second capacitor electrode CE2, and the third capacitor electrode CE3. The common electrode CM is located on the first dielectric material layer I1. The second dielectric material layer I2 is located on the common electrode CM. The first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 are located on the second dielectric material layer I2.

The first capacitor electrode CE1, the second capacitor electrode CE2, and the third capacitor electrode CE3 belong to the same film layer, and it can be said that they are formed in the same mask process. In this embodiment, the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 belong to another film layer, which can also be said to be formed in another photomask process.

In this embodiment, the first capacitor electrode CE1 overlaps the common electrode CM and the first pixel electrode PE1 in the direction N of the vertical substrate SB1, and the second capacitor electrode CE2 overlaps the common electrode CM in the direction N of the vertical substrate SB1. And the second pixel electrode PE2 and the third capacitor electrode CE3 overlap the common electrode CM and the third pixel electrode PE3 in the direction N of the vertical substrate SB1. Thereby, the display device 30 has the advantage of a high aperture ratio. In this embodiment, the first capacitive electrode CE1, the first The two capacitor electrodes CE2 and the third capacitor electrode CE3 do not easily affect the installation space of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3. The capacitance of the first main capacitor M1, the capacitance of the second main capacitor M2, and the capacitance of the third main capacitor M3 are increased by increasing the area of the first capacitor electrode CE1, the second capacitor electrode CE2, and the third capacitor electrode CE3. Therefore, the leakage problem of the display device 30 is improved.

In this embodiment, the capacitance value M1 of the first main capacitor and the capacitance value S1 of the first sub capacitor can be adjusted by adjusting the materials and / or thicknesses of the first dielectric material layer I1 and the second dielectric material layer I2. , The capacitance value M2 of the second main capacitor, the capacitance value S2 of the second auxiliary capacitor, the capacitance value M3 of the third main capacitor, and the capacitance value S3 of the third auxiliary capacitor. The materials and / or thicknesses of the first dielectric material layer I1 and the second dielectric material layer I2 are the same or different from each other. For the rest, please refer to the foregoing embodiments, and details are not described herein.

FIG. 4 is a schematic top view of a display device according to an embodiment of the invention. It must be noted here that the embodiment of FIG. 4 follows the component numbers and parts of the embodiments of FIG. 1A to FIG. 1C. The same or similar reference numerals are used to indicate the same or similar components, and the same technical content is omitted. Instructions. For the description of the omitted parts, reference may be made to the foregoing embodiments, and details are not described herein.

The main difference between the display device 40 of FIG. 4 and the display device 10 of FIGS. 1A to 1C is that the display device 40 further includes a gate driving circuit GD and a source driving circuit DD.

The gate driving circuit GD is electrically connected to the scan line SL. Source drive circuit DD The data lines DL are electrically connected (for example, the first data line DL1, the second data line DL2, and the third data line DL3 in FIG. 1A).

In this embodiment, the first sub-pixel PX1 is closer to the gate driving circuit GD than the second sub-pixel PX2. In other words, the first main driving element and the first sub driving element of the first sub pixel PX1 are closer to the gate driving circuit GD than the second main driving element and the second sub driving element of the second sub pixel PX2. The loss of the control signal on the scanning line SL when it reaches the first sub-pixel PX1 is smaller than the loss when it reaches the second sub-pixel PX2. Generally speaking, in the conventional technology, since the setting position is different from the gate driving circuit GD, the severity of the flicker problem in the first sub-pixel PX1 is different from the severity of the flicker problem in the second sub-pixel PX2. For example, the flicker problem of the second sub-pixel PX2 may be smaller than the flicker problem of the first sub-pixel PX1.

In this embodiment, even if the second sub-pixel PX2 is closer to the center of the display area AA, the capacitance value M1 of the first main capacitor is greater than the capacitance value M2 of the second main capacitor, thereby improving the screen difference of the display device 40. The problem of uneven position brightness.

Although in the present embodiment, the display device 40 is based on the bipolar gate driving as an example, the invention is not limited thereto. In other embodiments, the display device may be driven by a unilateral gate.

In summary, in the display device of the present invention, the sub-source of the sub-driving element is electrically connected to the capacitor electrode, and the sub-drain is electrically connected to the pixel electrode, so that the main between the common electrode and the capacitor electrode is Capacitance can reduce the electricity between the secondary drain and secondary source The voltage difference improves the leakage problem, so that the voltage on the pixel electrode can be maintained for a period of time even if the voltage is not applied to the scan line (ie, the main driving element and the sub driving element are turned off). In this way, the energy consumption can be reduced by reducing the number of frames of the display device.

Although the present invention has been disclosed as above in the embodiments, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some modifications and retouches without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application.

Claims (18)

A display device includes: a substrate; a first data line and a scan line on the substrate; a first sub-pixel on the substrate, wherein the first sub-pixel includes a first main driving element A first auxiliary driving element, a first capacitor electrode and a first pixel electrode, wherein the first main driving element includes: a first main gate electrode electrically connected to the scanning line; a first main channel Layer, which overlaps the first main gate electrode; and a first main source electrode and a first main drain electrode, which are electrically connected to the first main channel layer, wherein the first main source electrode is electrically connected to the first data Line; the first auxiliary driving element includes: a first auxiliary gate electrode electrically connected to the scanning line; a first auxiliary channel layer overlapping the first auxiliary gate electrode; a first auxiliary source electrode and a first auxiliary gate electrode A pair of drain electrodes is electrically connected to the first secondary channel layer, wherein the first main drain electrode is electrically connected to the first secondary source electrode, and the first capacitor electrode is electrically connected to the first main drain electrode and the first A secondary source electrode, and the first pixel electrode is electrically connected to the first secondary drain electrode; a passivation layer is located on the first source electrode; A main source electrode, the first main drain electrode, the first auxiliary source electrode, and the first auxiliary drain electrode, wherein the first capacitor electrode and the first pixel electrode are located on the passivation layer; and a common electrode is overlapped There is a first main capacitor between the common electrode and the first pixel electrode, and a first pair of capacitors between the common electrode and the first pixel electrode, and a first pair between the common electrode and the first pixel electrode. A capacitor, and the material of the first capacitor electrode, the first pixel electrode, and the common electrode includes a transparent conductive material. The display device according to item 1 of the scope of patent application, wherein part of the first capacitor electrode is parallel to the scan line. The display device according to item 1 of the application, wherein the first capacitor electrode and the first pixel electrode are located on the same side of the scan line. The display device according to item 1 of the scope of patent application, wherein the first capacitor electrode and the first pixel electrode are located on different sides of the scan line. The display device according to item 1 of the scope of patent application, wherein a capacitance value of the first main capacitor is M1, and a capacitance value of the first sub capacitor is S1, and S1 of 10% <M1 ≦ 60% of S1. The display device according to item 1 of the scope of patent application, further comprising: a second data line and a third data line on the substrate; a second sub-pixel and a third sub-pixel on the substrate The second sub-pixel includes: a second main driving element and a second sub driving element, wherein a second main source of the second main driving element is electrically connected to the second data line, and the A second main drain of the second main driving element is electrically connected to the second auxiliary driving element and a second auxiliary source; a second capacitor electrode is electrically connected to the second main drain and the second auxiliary source. A second pixel electrode electrically connected to the second secondary drain electrode, wherein a second main capacitor is provided between the common electrode and the second capacitor electrode, and a common pixel electrode is provided between the common electrode and the second pixel electrode; A second sub-capacitor; the third sub-pixel includes: a third main driving element and a third sub-driving element, wherein a third main source of the third main driving element is electrically connected to the third data line And a third main drain of the third main driving element is electrically connected to the third A secondary driving element is a third secondary source; a third capacitor electrode is electrically connected to the third main drain and the third secondary source; and a third pixel electrode is electrically connected to the third secondary drain. Wherein a third main capacitor is provided between the common electrode and the third capacitor electrode, a third auxiliary capacitor is provided between the common electrode and the third pixel electrode, and a capacitance value of the first main capacitor is M1, The capacitance value of the second main capacitor is M2, the capacitance value of the third main capacitor is M3, and M1 is not equal to M2 and M3. The display device according to item 6 of the scope of patent application, wherein the first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a blue For sub-pixels, the capacitance value of the first auxiliary capacitor is S1, the capacitance value of the second auxiliary capacitor is S2, and the capacitance value of the third auxiliary capacitor is S3, where S1 of 12% <M1 ≦ 50% of S1, 12% of S2 <M2 ≦ 50% of S2, and 10% of S3 <M3 <40% of S3. The display device according to item 7 of the scope of patent application, wherein M3 is smaller than M1 and M2. The display device according to item 6 of the scope of patent application, wherein the first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a blue For sub-pixels, the capacitance value of the first auxiliary capacitor is S1, the capacitance value of the second auxiliary capacitor is S2, and the capacitance value of the third auxiliary capacitor is S3, where 10% of S1 <M1 ≦ 50% of S1, 12% S2 <M2 ≦ 60% S2, and 10% S3 <M3 ≦ 50% S3. The display device according to item 9 of the scope of patent application, wherein M2 is larger than M1 and M3. The display device according to item 6 of the scope of patent application, wherein the capacitance value of the first auxiliary capacitor is S1, the capacitance value of the second auxiliary capacitor is S2, the capacitance value of the third auxiliary capacitor is S3, and S1 = S2 = S3. The display device according to item 6 of the scope of patent application, further comprising: a gate driving circuit electrically connected to the scanning line, wherein the first main driving element is closer to the gate than the second main driving element. Driving circuit, and M1 is larger than M2. The display device according to item 1 of the scope of patent application, wherein the first capacitor electrode and the first pixel electrode belong to different film layers. The display device according to item 13 of the scope of patent application, further comprising: a first dielectric material layer on the first capacitor electrode, and the common electrode on the first dielectric material layer; a second dielectric material; An electrical material layer is located on the common electrode, and the first pixel electrode is located on the second dielectric material layer. The display device according to item 13 of the application, wherein the first capacitor electrode overlaps the first pixel electrode in a direction perpendicular to the substrate. The display device according to item 1 of the scope of patent application, wherein the first capacitor electrode and the first pixel electrode belong to the same film layer. The display device according to item 16 of the scope of patent application, further comprising: a black matrix located on the substrate, wherein the black matrix overlaps the scan line and the first capacitor electrode in a direction perpendicular to the substrate. The display device according to item 1 of the patent application scope, wherein the first capacitor electrode is electrically connected to the first main drain electrode and the first sub-source electrode through a first through hole, and the first pixel electrode passes through a A second through hole is electrically connected to the first auxiliary drain, wherein the first through hole and the second through hole penetrate the passivation layer, and the first through hole and the second through hole extend along the scanning line. Tied.