TW202009898A - Display device - Google Patents

Abstract

A display device includes a substrate, a first data line, a scan line, a first sub-pixel, a first passivation layer, and a first common electrode. The first sub-pixel includes a first main-driving element, a first sub-driving element, a first capacitance electrode, and a first pixel electrode. The first main-driving element includes a first main-gate, a first main-channel layer, a first main-drain, and a first main-source. The first sub-driving element includes a first sub-gate, a first sub-channel layer, a first sub-drain, and a first sub-source. The first capacitance electrode is electrically connected with the first main drain and the first sub source. The first pixel electrode is electrically connected with the first sub drain. The common electrode and the first capacitance electrode have a first main capacitance therebetween. The common electrode and the first pixel electrode have a first sub capacitance therebetween.

Description

Display device

The present invention relates to a display device, and particularly to a display device in which a common electrode overlaps a capacitor electrode and a pixel electrode.

In recent years, with the continuous advancement of display technology, viewers' requirements on the resolution of display devices have become higher and higher. In order to improve the resolution of the display device, the size of each sub-pixel in the display device must be reduced. However, small-sized sub-pixels usually have relatively small storage capacitors, which is prone to problems of high feed-through voltage or crosstalk, and sometimes even leakage.

Reducing the frame rate can reduce the power consumption of the display device, thereby increasing the use time of the display device. However, if the storage capacitor in the display device is too small or the display device leaks, it is easy to reduce the number of frames due to the insufficient capacity of the storage capacitor to maintain the voltage. Therefore, in order to increase the use time of high-resolution display devices, there is an urgent need to improve the leakage of small-sized sub-pixels.

The invention provides a display device which can improve the problem of electric leakage.

An embodiment of the present invention provides a display device including a substrate, a first data line, a scan line, a first sub-pixel, a passivation layer, and a common electrode. The first data line and the scan line are located on the substrate. The first sub-pixel is located on the substrate. The first sub-pixel includes a first main driving element, a first sub-driving element, a first capacitor electrode, and a first pixel electrode. The first main driving element includes a first main gate, a first main channel layer, a first main source and a first main drain. The first main gate is electrically connected to the scan line. The first main channel layer overlaps the first main gate. The first main source and the first main drain are electrically connected to the first main channel layer. The first main source is electrically connected to the first data line. The first sub-driving element includes a first sub-gate, a first sub-channel layer, a first sub-source and a first sub-drain. The first sub-gate is electrically connected to the scan line. The first sub-channel layer overlaps the first sub-gate. The first sub-source and the first sub-drain are electrically connected to the first sub-channel layer. The first main drain is electrically connected to the first secondary source. The first capacitor electrode is electrically connected to the first main drain and the first sub-source. The first pixel electrode is electrically connected to the first secondary drain. The passivation layer is located on the first main source, the first main drain, the first sub-source, and the first sub-drain. The first capacitor electrode and the first pixel electrode are located on the passivation layer. The common electrode overlaps the first capacitor electrode and the first pixel electrode. There is a first main capacitor between the common electrode and the first capacitor electrode. There is a first secondary capacitor between the common electrode and the first pixel electrode. The materials of the first capacitor electrode, the first pixel electrode and the common electrode include transparent conductive materials.

Based on the above, the first sub-source of the first sub-driving element is electrically connected to the first capacitor electrode, and the first sub-drain is electrically connected to the first pixel electrode, thereby between the common electrode and the first capacitor electrode The first main capacitor can reduce the voltage difference between the first sub-drain and the first sub-source to improve the problem of leakage, so that even if the application of voltage to the scan line is stopped (that is, the first main driving element and the first sub-drive are turned off Component), the voltage on the first pixel electrode can still be maintained for a period of time. In this way, energy consumption can be reduced by reducing the number of frames of the display device.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the embodiments are specifically described below and described in detail in conjunction with the accompanying drawings.

FIG. 1A is a schematic top view of a display device according to an embodiment of the invention. Fig. 1B is a schematic cross-sectional view taken along line aa' of Fig. 1A. Fig. 1C is a schematic cross-sectional view taken along line bb' of Fig. 1A. For convenience of description, FIG. 1A omits some components in the display device.

The display device 10 includes a substrate SB1, a first data line DL1, a scan line SL, a first main gate MG1, a first sub-gate SG1, a first main channel layer MCH1, a first sub-channel layer SCH1, and a gate insulating layer GI , A first main source MS1, a first main drain MD1, a first sub-source SS1, a first sub-drain SD1, a passivation layer PV, a first capacitor electrode CE1, a first pixel electrode PE1 and a common electrode CM. In this embodiment, the display device 10 further includes a second data line DL2, a third data line DL3, a second main gate MG2, a second sub-gate SG2, a second main channel layer MCH2, and a second sub-channel layer SCH2 , The second main source MS2, the second main drain MD2, the second sub-source SS2, the second sub-drain SD2, the second capacitor electrode CE2, the second pixel electrode PE2, the third main gate MG3, the first Three sub-gates SG3, third main channel layer MCH3, third sub-channel layer SCH3, third main source MS3, third main drain MD3, third sub-source SS3, third sub-drain SD3, third The capacitor electrode CE3, the third pixel electrode PE3, the insulating layer U, the first dielectric material layer I1, the display medium layer M, the counter substrate SB2, the black matrix BM, and the color conversion element CF.

In this embodiment, three sub-pixels of the display device 10 are taken as an example for description, wherein the first sub-pixel PX1, the second sub-pixel PX2, and the third sub-pixel PX3 are located on the substrate SB1. The first sub-pixel PX1 includes a first main driving element MT1, a first sub-driving element ST1, a first capacitor electrode CE1 and a first pixel electrode PE1, and the second sub-pixel PX2 includes a second main driving element MT2 and a second The sub-driving element ST2, the second capacitor electrode CE2 and the second pixel electrode PE2, and the third sub-pixel PX3 includes a third main driving element MT3, a third sub-driving element ST3, a third capacitor electrode CE3 and a third pixel Electrode PE3.

The first main gate MG1, the first main channel layer MCH1, the first main source MS1, and the first main drain MD1 constitute a first main driving element MT1. The first sub-gate SG1, the first sub-channel layer SCH1, the first sub-source SS1, and the first sub-drain SD1 constitute a first sub-drive element ST1. The second main gate MG2, the second main channel layer MCH2, the second main source MS2, and the second main drain MD2 constitute a second main driving element MT2. The second sub-gate SG2, the second sub-channel layer SCH2, the second sub-source SS2, and the second sub-drain SD2 constitute a second sub-driving element ST2. The third main gate MG3, the third main channel layer MCH3, the third main source MS3, and the third main drain MD3 constitute a third main driving element MT3. The third sub-gate SG3, the third sub-channel layer SCH3, the third sub-source SS3, and the third sub-drain SD3 constitute a third sub-drive element ST3.

First main driving element MT1, first sub driving element ST1, second main driving element MT2, second sub driving element ST2, third main driving element MT3, third sub driving element ST3, first data line DL1, second The data line DL2, the third data line DL3, and the scan line SL are located on the substrate SB1.

The first main gate MG1 and the first sub-gate SG1 are electrically connected to the scan line SL. The first main channel layer MCH1 and the first sub-channel layer SCH1 overlap the first main gate MG1 and the first sub-gate SG1 in the direction N perpendicular to the substrate SB1, respectively. The gate insulating layer GI is located between the first main gate MG1 and the first main channel layer MCH1 and between the first sub-gate SG1 and the first sub-channel layer SCH1. The first main source MS1 and the first main drain MD1 are electrically connected to the first main channel layer MCH1. The first main source MS1 is electrically connected to the first data line DL1. The first sub-source SS1 and the first sub-drain SD1 are electrically connected to the first sub-channel layer SCH1. The first main drain MD1 is electrically connected to the first sub-source SD1. In the present embodiment, the first main drain electrode MD1 and the first sub-source electrode SD1 are substantially integrated.

The second main gate MG2 and the second sub-gate SG2 are electrically connected to the scan line SL. The second main channel layer MCH2 and the second sub-channel layer SCH2 overlap the second main gate MG2 and the second sub-gate SG2 in the direction N perpendicular to the substrate SB1, respectively. The gate insulating layer GI is located between the second main gate MG2 and the second main channel layer MCH2 and between the second sub gate SG2 and the second sub channel layer SCH2. The second main source MS2 and the second main drain MD2 are electrically connected to the second main channel layer MCH2. The second main source MS2 is electrically connected to the second data line DL2. The second sub-source SS2 and the second sub-drain SD2 are electrically connected to the second sub-channel layer SCH2. The second main drain MD2 is electrically connected to the second sub-source SD2. In this embodiment, the second main drain electrode MD2 and the second sub-source electrode SD2 are substantially integrated.

The third main gate MG3 and the third sub-gate SG3 are electrically connected to the scan line SL. The third main channel layer MCH3 and the third sub-channel layer SCH3 overlap the third main gate MG3 and the third sub-gate SG3 in the direction N perpendicular to the substrate SB1, respectively. The gate insulating layer GI is located between the third main gate MG3 and the third main channel layer MCH3 and between the third sub gate SG3 and the third sub channel layer SCH3. The third main source MS3 and the third main drain MD3 are electrically connected to the third main channel layer MCH3. The third main source MS3 is electrically connected to the third data line DL3. The third sub-source SS3 and the third sub-drain SD3 are electrically connected to the third sub-channel layer SCH3. The third main drain MD3 is electrically connected to the third sub-source SD3. In this embodiment, the third main drain MD3 and the third sub-source SD3 are substantially connected together.

The first main channel layer MCH1, the first sub-channel layer SCH1, the second main channel layer MCH2 and the second sub-channel layer SCH2, the third main channel layer MCH3 and the third sub-channel layer SCH3 each have a single-layer or multi-layer structure, which Materials include, for example, amorphous silicon, polycrystalline silicon, microcrystalline silicon, single crystal silicon, organic semiconductor materials, oxide semiconductor materials (for example: indium zinc oxide, indium gallium zinc oxide or other suitable materials or a combination of the above) or other Suitable materials may contain dopants in the above materials or a combination thereof.

The first data line DL1, the second data line DL2, the third data line DL3, the scan line SL, the first main gate MG1, the first sub-gate SG1, the second main gate MG2, the second sub-gate SG2, The third main gate MG1, the third sub-gate SG3, the first main source MS1, the first main drain MD1, the first sub-source SS1, the first sub-drain SD1, the second main source MS2, the first The second main drain MD2, the second sub-source SS2, the second sub-drain SD2, the third main source MS3, the third main drain MD3, the third sub-source SS3, and the third sub-drain SD3 are each single Layer or multi-layer structure, its materials include chromium, gold, silver, copper, tin, lead, hafnium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc and other metals, alloys of the above metals, oxides of the above metals, The above-mentioned metal nitride or the above-mentioned material combination or other conductive material.

In this embodiment, the main driving element and the sub driving element are exemplified by bottom gate thin film transistors, but the present invention is not limited thereto. In other embodiments, the main driving element and the sub-driving element are top gate thin film transistors, double gate thin film transistors, or other types of thin film transistors. In other embodiments, each main driving element is not limited to a single thin film transistor, and each main driving element may be formed by connecting more than two thin film transistors in series. Similarly, each sub-driving element is not limited to a single thin film transistor, and each sub-driving element may be formed by connecting more than two thin film transistors in series.

The passivation layer PV is located in the first main source MS1, the first main drain MD1, the first sub-source SS1, the first sub-drain SD1, the second main source MS2, the second main drain MD2, the second sub-source The electrode SS2, the second sub-drain SD2, the third main-source MS3, the third main-drain MD3, the third sub-source SS3, and the third sub-drain SD3.

The insulating layer U is located on the passivation layer PV. The insulating layer U is, for example, an organic insulating layer, but the invention is not limited thereto.

The common electrode CM is located on the insulating layer U. The common electrode CM has a plurality of openings O corresponding to the first main drain MD1, the first sub-source SS1, the first sub-drain SD1, the second main drain MD2, the second sub-source SS2, and the second sub The positions of the drain electrode SD2, the third main drain electrode MD3, the third sub-source electrode SS3, and the third sub-drain electrode SD3 are set.

The first dielectric material layer I1 is located on the common electrode CM. The first capacitor electrode CE1, the first pixel electrode PE1, the second capacitor electrode CE2, the second pixel electrode PE2, the third capacitor electrode CE3, and the third pixel electrode PE3 are located on the passivation layer PV. In this embodiment, between the first capacitor electrode CE1, the first pixel electrode PE1, the second capacitor electrode CE2, the second pixel electrode PE2, the third capacitor electrode CE3, the third pixel electrode PE3 and the passivation layer PV The insulating layer U, the first dielectric material layer I1, and the common electrode CM are also sandwiched. In this embodiment, the first capacitor electrode CE1, the first pixel electrode PE1, the second capacitor electrode CE2, the second pixel electrode PE2, the third capacitor electrode CE3 and the third pixel electrode PE3 belong to the same film layer, and It can be said that it is formed in the same reticle process, thereby reducing the influence of process deviation on the optical properties. In this embodiment, materials of the first capacitor electrode CE1, the first pixel electrode PE1, the second capacitor electrode CE2, the second pixel electrode PE2, the third capacitor electrode CE3, the third pixel electrode PE3, and the common electrode CM Include transparent conductive materials, for example, indium tin oxide, indium zinc oxide or other metal oxides or a combination of the above materials.

In this embodiment, the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 are located on one side of the scan line SL, and part of the first capacitor electrode CE1, part of the second capacitor electrode CE2, and part The third capacitor electrode CE3 is located on the other side of the scan line SL.

The first capacitor electrode CE1 is electrically connected to the first main drain MD1 and the first sub-source SS1. For example, the first capacitor electrode CE1 is electrically connected to the first main drain MD1 and the first sub-source SS1 through the first through hole TH1. The first pixel electrode PE1 is electrically connected to the first secondary drain electrode SD1. For example, the first pixel electrode PE1 is electrically connected to the first sub-drain electrode SD1 through the second through hole TH2.

The second capacitor electrode CE2 is electrically connected to the second main drain MD2 and the second sub-source SS2. For example, the second capacitor electrode CE2 is electrically connected to the second main drain MD2 and the second sub-source SS2 through the third through hole TH3. The second pixel electrode PE2 is electrically connected to the second sub-drain electrode SD2. For example, the second pixel electrode PE2 is electrically connected to the second sub-drain electrode SD2 through the fourth through hole TH4.

The third capacitor electrode CE3 is electrically connected to the third main drain MD3 and the third sub-source SS3. For example, the third capacitor electrode CE3 is electrically connected to the third main drain MD3 and the third sub-source SS3 through the fifth through hole TH5. The third pixel electrode PE3 is electrically connected to the third sub-drain electrode SD3. For example, the third pixel electrode PE3 is electrically connected to the third sub-drain electrode SD3 through the sixth through hole TH6.

In this embodiment, the first through hole TH1, the second through hole TH2, the third through hole TH3, the fourth through hole TH4, the fifth through hole TH5, and the sixth through hole TH6 penetrate the passivation layer PV, the insulating layer U, and The first dielectric material layer I1. The first through hole TH1, the second through hole TH2, the third through hole TH3, the fourth through hole TH4, the fifth through hole TH5, and the sixth through hole TH6 are provided corresponding to the plurality of openings O of the common electrode CM. In this embodiment, the first through hole TH1 and the second through hole TH2 are juxtaposed along the extending direction of the scanning line SL, the third through hole TH3 and the fourth through hole TH4 are juxtaposed along the extending direction of the scanning line SL, and the fifth through The hole TH5 and the sixth through hole TH6 are juxtaposed along the extending direction of the scanning line SL, thereby reducing the influence of the through hole on the aperture ratio.

In this embodiment, the common electrode CM overlaps the first capacitor electrode CE1, the first pixel electrode PE1, the second capacitor electrode CE2, the second pixel electrode PE2, and the third capacitor electrode CE3 in the direction N perpendicular to the substrate SB1 And the third pixel electrode PE3. There is a first main capacitance between the common electrode CM and the first capacitance electrode CE1, and the capacitance value is M1. There is a first secondary capacitance between the common electrode CM and the first pixel electrode PE1, and the capacitance value is S1. There is a second main capacitance between the common electrode CM and the second capacitance electrode CE2, and the capacitance value is M2. There is a second sub-capacitance between the common electrode CM and the second pixel electrode PE2, and the capacitance value is S2. There is a third main capacitance between the common electrode CM and the third capacitance electrode CE3, and the capacitance value is M3. There is a third sub-capacitance between the common electrode CM and the third pixel electrode PE3, and the capacitance value is S3. In this embodiment, S1=S2=S3.

By setting the first main capacitor, the second main capacitor, and the third main capacitor, the ability to maintain the voltage on the pixel electrode can be increased. For example, the first main capacitor between the common electrode CM and the first capacitor electrode CE1 can reduce the voltage difference between the first sub-drain SD1 and the first sub-source SS1 to improve the leakage problem, so that even if the scanning is stopped When a voltage is applied to the line SL (that is, the first main driving element MT1 and the first sub-driving element ST1 are turned off), the voltage on the first pixel electrode PE1 can still be maintained for a period of time. Therefore, by reducing the number of frames of the display device 10, energy loss can be reduced.

In some embodiments, in order to take into account the pixel's anti-leakage effect, charging effect and optical properties, S1, M1, S2, M2, S3, M3 satisfy the following relationship: 10% S1 <M1 ≦ 60% S1, 10% S2 <M2 ≦ 60% S2, and 10% S3 <M3 ≦ 60% S3.

The counter substrate SB2 is provided facing the substrate SB1. The black matrix BM and the color conversion element CF are located on the substrate SB1. The black matrix BM and the color conversion element CF are provided on the counter substrate SB2. The display medium layer M is sandwiched between the counter substrate SB2 and the substrate SB1. The display medium layer M includes, for example, liquid crystal molecules.

In this embodiment, the black matrix BM overlaps the scan line SL, the first capacitor electrode CE1, the first data line DL1, the first main driving element MT1, the first sub-driving element ST1, the first in the direction N perpendicular to the substrate SB1 Two capacitor electrodes CE2, a second data line DL2, a second main driving element MT2, a second sub-driving element ST2, a third capacitor electrode CE3, a third data line DL3, a third main driving element MT3 and a third sub-driving element ST3 .

In this embodiment, since part of the first capacitor electrode CE1, part of the second capacitor electrode CE2 and part of the third capacitor electrode CE3 are parallel to the scanning line SL, and the first capacitor electrode CE1, the second capacitor electrode CE2 and the third capacitor electrode CE3 is disposed adjacent to the scan line SL, therefore, the area of the black matrix BM can cover the first capacitor electrode CE1, the second capacitor electrode CE2, the third capacitor electrode CE3, and the scan line SL without a large area, thereby reducing the pair of capacitor electrodes The effect of pixel aperture ratio. In the present embodiment, the partial first capacitive electrode CE1, the partial second capacitive electrode CE2, and the partial third capacitive electrode CE3 that are parallel to the scan line SL do not overlap the scan line SL in the direction N perpendicular to the substrate SB1, but the present invention Not limited to this. In other embodiments, part of the first capacitor electrode CE1, part of the second capacitor electrode CE2 and part of the third capacitor electrode CE3 parallel to the scan line SL may overlap the scan line SL in the direction N perpendicular to the substrate SB1, thereby, The influence of the capacitance electrode on the aperture ratio can be further reduced. In this embodiment, the positions of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 correspond to the openings of the black matrix BM.

The color conversion layer CF includes multiple different colors, for example, a red color conversion layer, a green color conversion layer, and a blue color conversion layer. In this embodiment, the first sub-pixel PX1, the second sub-pixel PX2, and the third sub-pixel PX3 respectively correspond to the red color conversion layer, the green color conversion layer, and the blue color conversion layer. In other words, the first sub-pixel PX1 is a red sub-pixel, the second sub-pixel PX2 is a green sub-pixel, and the third sub-pixel PX3 is a blue sub-pixel.

In this embodiment, by adjusting the capacitance M1 of the first main capacitor, the capacitance M2 of the second main capacitor, and the capacitance M3 of the third main capacitor, the sub-pixels of different colors have better optical properties. For example, the capacitance value M1 is not equal to the capacitance value M2 and the capacitance value M3, and the capacitance value M2 is not equal to the capacitance value M3. In this embodiment, in the first main capacitor, the second main capacitor, and the third main capacitor, the materials of the dielectric layer (first dielectric material layer I1) between the two electrodes (capacitive electrode and common electrode) are the same By adjusting the area of the first capacitor electrode CE1, the second capacitor electrode CE2 and the third capacitor electrode CE3, or by providing openings of different sizes on the first capacitor electrode CE1, the second capacitor electrode CE2 and the third capacitor electrode CE3 To adjust the capacitance value M1, the capacitance value M2, and the capacitance value M3. For example, the ratio of the capacitance value M1, the capacitance value M2, and the capacitance value M3 is equal to the area ratio of the first capacitance electrode CE1, the second capacitance electrode CE2, and the third capacitance electrode CE3, but the invention is not limited thereto.

In some embodiments, since the brightness of the third sub-pixel PX3 (blue sub-pixel) is lower and the flicker is less noticeable, by adjusting the capacitance M3 of the third main capacitor to be smaller than the first main capacitor The capacitance M1 and the capacitance M2 of the second main capacitor enable the third sub-pixel PX3 to have a better charging rate. For example, S1, M1, S2, M2, S3, M3 can satisfy the following relationship: 12% S1 <M1 ≦ 50% S1, 12% S2 <M2 ≦ 50% S2, and 10% S3 ＜ M3 ＜ 40% of S3.

In some embodiments, since the brightness of the second sub-pixel PX2 (green sub-pixel) is higher and the flicker is more significant, the capacitance M2 of the second main capacitor is adjusted to be larger than the capacitance of the first main capacitor Value M1 and the capacitance value M3 of the third main capacitor to improve the flicker problem of the second sub-pixel PX2. For example, S1, M1, S2, M2, S3, M3 can satisfy the following relationship: 10% S1 <M1 ≦ 50% S1, 12% S2 <M2 ≦ 60% S2, and 10% S3 ＜ M3 ≦ 50% of S3.

2 is a schematic top view of a display device according to an embodiment of the invention. It must be noted here that the embodiment of FIG. 2 follows the element numbers and partial contents of the embodiment of FIGS. 1A to 1C, wherein the same or similar reference numerals are used to indicate the same or similar elements, and the same technical content is omitted. Instructions. For the description of the omitted parts, reference may be made to the foregoing embodiment, which will not be repeated here.

The main difference between the display device 20 of FIG. 2 and the display device 10 of FIG. 1A lies in: the first capacitive electrode CE1, the first pixel electrode PE1, the second capacitive electrode CE2, the second pixel electrode PE2, the third The capacitor electrode CE3 and the third pixel electrode PE3 are located on the same side of the scan line.

In this embodiment, the first main capacitor and the first sub-capacitor are juxtaposed along the extending direction of the scanning line SL, the second main capacitor and the second sub-capacitor are juxtaposed along the extending direction of the scanning line SL, and the third main capacitor and the first The three pairs of capacitors are aligned along the extending direction of the scanning line SL.

In the display device 20, the capacitance value M1 of the first main capacitor, the capacitance value S1 of the first subcapacitor, the capacitance value M2 of the second main capacitor, the capacitance value S2 of the second subcapacitor, and the capacitance value M3 of the third main capacitor And the space where the capacitance value S3 of the third sub-capacitor can be adjusted is larger than that of the display device 10. For the rest, please refer to the foregoing embodiments, which will not be repeated here.

3A is a schematic top view of a display device according to an embodiment of the invention. Fig. 3B is a schematic cross-sectional view taken along line aa' of Fig. 3A. Fig. 3C is a schematic cross-sectional view taken along line bb' of Fig. 3A. It must be noted here that the embodiments of FIGS. 3A to 3C continue to use the element numbers and partial contents of the embodiments of FIGS. 1A to 1C, wherein the same or similar reference numbers are used to indicate the same or similar elements, and the same is omitted. Description of technical content. For the description of the omitted parts, reference may be made to the foregoing embodiment, which will not be repeated here.

The main difference between the display device 30 of FIGS. 3A to 3C and the display device 10 of FIGS. 1A to 1C is that the display device 30 further includes a second dielectric material layer I2.

3A to 3C, the first capacitor electrode CE1, the second capacitor electrode CE2 and the third capacitor electrode CE3 are located on the insulating layer U. The first dielectric material layer I1 is located on the first capacitor electrode CE1, the second capacitor electrode CE2, and the third capacitor electrode CE3. The common electrode CM is located on the first dielectric material layer I1. The second dielectric material layer I2 is located on the common electrode CM. The first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 are located on the second dielectric material layer I2.

The first capacitor electrode CE1, the second capacitor electrode CE2 and the third capacitor electrode CE3 belong to the same film layer, which can also be said to be formed in the same photomask manufacturing process. In this embodiment, the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 belong to another film layer, which can also be said to be formed in another mask process.

In this embodiment, the first capacitor electrode CE1 overlaps the common electrode CM and the first pixel electrode PE1 in the direction N perpendicular to the substrate SB1, and the second capacitor electrode CE2 overlaps the common electrode CM in the direction N perpendicular to the substrate SB1 And the second pixel electrode PE2 and the third capacitor electrode CE3 overlap the common electrode CM and the third pixel electrode PE3 in the direction N perpendicular to the substrate SB1. Thereby, the display device 30 has the advantage of high aperture ratio. In this embodiment, the first capacitive electrode CE1, the second capacitive electrode CE2, and the third capacitive electrode CE3 do not easily affect the installation space of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3. By increasing the areas of the first capacitor electrode CE1, the second capacitor electrode CE2, and the third capacitor electrode CE3, the capacitance value M1 of the first main capacitor, the capacitance value M2 of the second main capacitor, and the capacitance value M3 of the third main capacitor are increased Therefore, the leakage problem of the display device 30 is improved.

In this embodiment, the capacitance M1 of the first main capacitor and the capacitance S1 of the first sub-capacitor can be adjusted by adjusting the materials and/or thicknesses of the first dielectric material layer I1 and the second dielectric material layer I2 , The capacitance value M2 of the second main capacitor, the capacitance value S2 of the second sub-capacitor, the capacitance value M3 of the third main capacitor, and the capacitance value S3 of the third sub-capacitor. The materials and/or thicknesses of the first dielectric material layer I1 and the second dielectric material layer I2 are the same or different from each other. For the rest, please refer to the foregoing embodiments, which will not be repeated here.

4 is a schematic top view of a display device according to an embodiment of the invention. It must be noted here that the embodiments of FIGS. 3A to 3C continue to use the element numbers and partial contents of the embodiments of FIGS. 1A to 1C, wherein the same or similar reference numbers are used to indicate the same or similar elements, and the same is omitted. Description of technical content. For the description of the omitted parts, reference may be made to the foregoing embodiment, which will not be repeated here.

The main difference between the display device 40 of FIG. 4 and the display device 10 of FIGS. 1A to 1C is that the display device 40 further includes a gate driving circuit GD and a source driving circuit DD.

The gate drive circuit GD is electrically connected to the scan line SL. The source driving circuit DD is electrically connected to the data line DL (for example, the first data line DL1, the second data line DL2, and the third data line DL3 of FIG. 1A).

In this embodiment, the first sub-pixel PX1 is closer to the gate driving circuit GD than the second sub-pixel PX2. In other words, the first main driving element and the first sub-driving element of the first sub-pixel PX1 are closer to the gate driving circuit GD than the second main driving element and the second sub-driving element of the second sub-pixel PX2 The loss of the control signal on the scan line SL when it reaches the first sub-pixel PX1 is less than the loss when it reaches the second sub-pixel PX2. Generally speaking, in the conventional technology, the severity of the flickering problem of the first sub-pixel PX1 is different from the severity of the flickering problem of the second sub-pixel PX2 due to the difference in the setting position relative to the gate driving circuit GD. For example, the flicker problem of the second sub-pixel PX2 may be smaller than that of the first sub-pixel PX1.

In this embodiment, even if the second sub-pixel PX2 is closer to the center of the display area AA, by making the capacitance value M1 of the first main capacitor larger than the capacitance value M2 of the second main capacitor, thereby improving the picture difference of the display device 40 The problem of uneven position brightness.

Although in this embodiment, the display device 40 is an example of bilateral gate driving, the present invention is not limited to this. In other embodiments, the display device may also be gate unilaterally driven.

In summary, in the display device of the present invention, the sub-source of the sub-driving element is electrically connected to the capacitor electrode, and the sub-drain electrode is electrically connected to the pixel electrode, whereby the main electrode between the common electrode and the capacitor electrode The capacitor can reduce the voltage difference between the sub-drain and the sub-source to improve the leakage problem, so that even if the voltage on the scanning line is stopped (ie, the main driving element and the sub driving element are turned off), the voltage on the pixel electrode can still be maintained for a period of time time. In this way, energy consumption can be reduced by reducing the number of frames of the display device.

Although the present invention has been disclosed as above in the embodiments, it is not intended to limit the present invention. Anyone who has ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to the scope defined in the appended patent application.

10, 20, 30, 40 ‧‧‧ display device AA‧‧‧Display area BM‧‧‧Black Matrix CE1‧‧‧The first capacitor electrode CE2‧‧‧Second capacitor electrode CE3‧‧‧third capacitor electrode CF‧‧‧Color Conversion Element CM‧‧‧Common electrode DD‧‧‧ source drive circuit DL‧‧‧Data cable DL1‧‧‧First data line DL2‧‧‧Second data cable DL3‧‧‧third data line I1‧‧‧First dielectric material layer I2‧‧‧Second dielectric material layer N‧‧‧ direction M‧‧‧ display medium layer MCH1‧‧‧First main channel layer MCH2‧‧‧Second main channel layer MCH3‧‧‧The third main channel layer MD1‧‧‧The first main drain MD2‧‧‧Second main drain MD3‧‧‧The third main drain MG1‧‧‧First main gate MG2‧‧‧Second Main Gate MG3‧‧‧The third main gate MS1‧‧‧The first main source MS2‧‧‧Second main source MS3‧‧‧The third main source GD‧‧‧ gate drive circuit GI‧‧‧Gate insulation O‧‧‧ opening PE1‧‧‧The first pixel electrode PE2‧‧‧Second pixel electrode PE3‧‧‧third pixel electrode PV‧‧‧passivation layer PX1‧‧‧Second sub-pixel PX2‧‧‧The first sub-pixel PX3‧‧‧third pixel SB1‧‧‧ substrate SB2‧‧‧counter substrate SCH1‧‧‧The first secondary channel layer SCH2‧‧‧Secondary channel layer SCH3‧‧‧third secondary channel layer SD1‧‧‧First Vice Drain SD2‧‧‧Second Vice Drain SD3‧‧‧The third vice drain SG1‧‧‧First secondary gate SG2‧‧‧second secondary gate SG3‧‧‧third secondary gate SL‧‧‧scan line SS1‧‧‧First vice source SS2‧‧‧Second secondary source SS3‧‧‧third secondary source TH1‧‧‧First through hole TH2‧‧‧Second through hole TH3‧‧‧th through hole TH4‧‧‧The fourth through hole TH5‧‧‧Fifth through hole TH6‧‧‧Sixth through hole U‧‧‧Insulation

FIG. 1A is a schematic top view of a display device according to an embodiment of the invention. Fig. 1B is a schematic cross-sectional view taken along line aa' of Fig. 1A. Fig. 1C is a schematic cross-sectional view taken along line bb' of Fig. 1A. 2 is a schematic top view of a display device according to an embodiment of the invention. 3A is a schematic top view of a display device according to an embodiment of the invention. Fig. 3B is a schematic cross-sectional view taken along line aa' of Fig. 3A. Fig. 3C is a schematic cross-sectional view taken along line bb' of Fig. 3A. 4 is a schematic top view of a display device according to an embodiment of the invention.

10‧‧‧Display device

BM‧‧‧Black Matrix

CE1‧‧‧The first capacitor electrode

CF‧‧‧Color Conversion Element

CM‧‧‧Common electrode

GI‧‧‧Gate insulation

I1‧‧‧First dielectric material layer

N‧‧‧ direction

M‧‧‧ display medium layer

MCH1‧‧‧First main channel layer

MD1‧‧‧The first main drain

MG1‧‧‧First main gate

MS1‧‧‧The first main source

O‧‧‧ opening

PE1‧‧‧The first pixel electrode

PV‧‧‧passivation layer

SB1‧‧‧ substrate

SB2‧‧‧counter substrate

SCH1‧‧‧The first secondary channel layer

SD1‧‧‧First Vice Drain

SG1‧‧‧First secondary gate

SS1‧‧‧First vice source

TH1‧‧‧First through hole

TH2‧‧‧Second through hole

U‧‧‧Insulation

DL1‧‧‧First data line

Claims (18)

A display device, including: A substrate A first data line and a scanning line are located on the substrate; A first sub-pixel is located on the substrate, wherein the first sub-pixel includes a first main driving element, a first sub-driving element, a first capacitor electrode and a first pixel electrode, wherein The first main driving element includes: A first main gate, electrically connected to the scanning line; A first main channel layer overlapping the first main gate; and A first main source electrode and a first main drain electrode, electrically connected to the first main channel layer, wherein the first main source electrode is electrically connected to the first data line; The first secondary driving element includes: A first sub-gate, electrically connected to the scan line; A first secondary channel layer, overlapping the first secondary gate; A first secondary source electrode and a first secondary drain electrode are electrically connected to the first secondary channel layer, wherein the first primary drain electrode is electrically connected to the first secondary source electrode, and the first capacitor electrode is electrically connected to the A first main drain electrode and the first auxiliary source electrode, and the first pixel electrode is electrically connected to the first auxiliary drain electrode; A passivation layer on the first main source, the first main drain, the first sub-source and the first sub-drain, wherein the first capacitor electrode and the first pixel electrode are on the passivation layer On; and A common electrode overlapping the first capacitor electrode and the first pixel electrode, wherein there is a first main capacitor between the common electrode and the first capacitor electrode, and between the common electrode and the first pixel electrode It has a first secondary capacitor, and the materials of the first capacitor electrode, the first pixel electrode and the common electrode include transparent conductive materials. The display device according to item 1 of the patent application scope, wherein part of the first capacitive electrode is parallel to the scanning line. The display device according to item 1 of the patent application scope, wherein the first capacitor electrode and the first pixel electrode are located on the same side of the scan line. The display device as described in item 1 of the patent application range, wherein the first capacitor electrode and the first pixel electrode are located on different sides of the scan line. The display device as described in item 1 of the patent application range, wherein the capacitance value of the first main capacitor is M1, and the capacitance value of the first sub-capacitor is S1, and S1 of 10% S1 <M1 ≦ 60% S1. The display device as described in item 1 of the patent application scope further includes: A second data line and a third data line are located on the substrate; A second sub-pixel and a third sub-pixel are located on the substrate, wherein the second sub-pixel includes: A second main driving element and a second sub-driving element, wherein a second main source of the second main driving element is electrically connected to the second data line, and a second main drain of the second main driving element The electrode is electrically connected to the second auxiliary driving element and a second auxiliary source electrode; A second capacitor electrode electrically connected to the second main drain electrode and the second sub-source electrode; A second pixel electrode electrically connected to the second sub-drain, wherein there is a second main capacitor between the common electrode and the second capacitor electrode, and there is a between the common electrode and the second pixel electrode Second capacitor The third sub-pixel includes: A third main driving element and a third sub-driving element, wherein a third main source of the third main driving element is electrically connected to the third data line, and a third main drain of the third main driving element A pole is electrically connected to the third sub-driving element a third sub-source; A third capacitor electrode electrically connected to the third main drain electrode and the third sub-source electrode; and A third pixel electrode electrically connected to the third sub-drain, wherein a third main capacitor is provided between the common electrode and the third capacitor electrode, and a common electrode is provided between the common electrode and the second pixel electrode In the third sub-capacitor, the capacitance value of the first main capacitor is M1, the capacitance value of the second main capacitor is M2, and the capacitance value of the third main capacitor is M3, and M1 is not equal to M2 and M3. The display device as described in item 6 of the patent application scope, wherein the first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a blue For sub-pixels, the capacitance value of the first sub-capacitor is S1, the capacitance value of the second sub-capacitor is S2, and the capacitance value of the third sub-capacitor is S3, where 12% of S1 ＜ M1 ≦ 50% of S1, 12% of S2 <M2 ≦ 50% of S2, and 10% of S3 <M3 <40% of S3. The display device as described in item 7 of the patent application scope, wherein M3 is smaller than M1 and M2. The display device as described in item 6 of the patent application scope, wherein the first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a blue For sub-pixels, the capacitance value of the first sub-capacitor is S1, the capacitance value of the second sub-capacitor is S2, and the capacitance value of the third sub-capacitor is S3, where 10% S1 ＜ M1 ≦ 50% S1, 12% of S2 <M2 ≦ 60% of S2, and 10% of S3 <M3 ≦ 50% of S3. The display device as described in item 9 of the patent application scope, wherein M2 is greater than M1 and M3. The display device according to item 6 of the patent application scope, wherein the capacitance value of the first sub-capacitor is S1, the capacitance value of the second sub-capacitor is S2, the capacitance value of the third sub-capacitor is S3, and S1= S2=S3. The display device as described in item 6 of the patent application scope further includes: A gate driving circuit is electrically connected to the scanning line, wherein the first main driving element is closer to the gate driving circuit than the second main driving element, and M1 is greater than M2. The display device as described in item 1 of the patent application scope, wherein the first capacitor electrode and the first pixel electrode belong to different layers The display device as described in item 13 of the patent application scope further includes: A first dielectric material layer on the first capacitor electrode, and the common electrode on the first dielectric material layer; A second dielectric material layer is located on the common electrode, and the first pixel electrode is located on the second dielectric material layer. The display device as recited in item 13 of the patent application range, wherein the first capacitor electrode overlaps the first pixel electrode in a direction perpendicular to the substrate. The display device according to item 1 of the patent application scope, wherein the first capacitor electrode and the first pixel electrode belong to the same film layer. The display device described in Item 16 of the patent application scope further includes: A black matrix is located on the substrate, wherein the black matrix overlaps the scan line and the first capacitor electrode in a direction perpendicular to the substrate. The display device as described in Item 1 of the patent application range, wherein the first capacitor electrode is electrically connected to the first main drain electrode and the first sub-source electrode through a first through hole, and the first pixel electrode passes through a The second through hole is electrically connected to the first sub-drain, wherein the first through hole and the second through hole penetrate the passivation layer, and the first through hole and the second through hole extend along the scan line extending direction Tied.

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