TW202009903A - Display apparatus - Google Patents

Abstract

The present invention provides a display apparatus. The display apparatus includes a plurality of display areas, each of the display areas includes a plurality of display pixels, a control line, and a switch. The switch is coupled between the plurality of display pixels and the control line of corresponding display area, and is controlled by a data update control signal of a gate line in the display area to be turned on or cut off.

Description

Display device

The present invention relates to a display device, and particularly to a display device for updating a display screen in a partition.

Due to the development of large-scale, high-frequency, and high-resolution display devices, the power consumption of displays has increased rapidly. Therefore, the technology of updating the display screen by partitions has been developed to refresh the image data at normal frequencies only for local partitions, while refreshing the video data at reduced frequencies in most other partitions to effectively reduce the power consumption of the display device.

However, the display device of the prior art partition update display screen shares the partition control line with the peer partition. When the partition updates the display screen, the interaction between the partitions is generated. When the display screen is updated by partition, the thin-film transistors (Thin-Film-Transistor, TFT) in each display pixel in different partitions are turned on or off in different states, resulting in different leakage between the partitions phenomenon. The above-mentioned leakage phenomenon will cause different optical performances of the display pixels between different partitions, and cause cross-talk of the entire display screen of the display, which will cause a decrease in display quality.

The present invention provides a display device for updating a display screen by partitions, which can effectively reduce power consumption of the display device and improve display quality.

The display device of the present invention includes a plurality of partitions. Each zone contains multiple display pixels, control lines and switches. The control line is used to transmit zone control signals. The switch is coupled between the plurality of display pixels and the control line, and is controlled by the partition enable signal of the gate line in the partition to be turned on or off.

Based on the above, the present invention proposes a display device for updating a display screen in a partition, by providing a switch in the partition, and determining the data refresh frequency of the partition by turning on or off the switch. Since the switching of the switch is controlled by the gate line of the partition, the influence of other partitions during data refresh can be avoided, and the above-mentioned picture crosstalk between different partitions can be improved to ensure that the display device updates the display screen in the partition It is also possible to maintain good display quality.

In order to make the above-mentioned features and advantages of the present invention more obvious and understandable, the embodiments are specifically described below in conjunction with the accompanying drawings as follows.

Please refer to FIG. 1, which is a schematic diagram of a display device according to a first embodiment of the present invention. The display device 100 has a plurality of partitions Z11 to Z33 arranged in an array, wherein the partitions Z11 to Z31 form a first display line; the partitions Z12 to Z32 form a second display line; and the partitions Z13 to Z33 form a third display line. In this embodiment, each zone Z11~Z33 of the display device 100 is respectively coupled to a plurality of gate lines GL1~GLM and a plurality of data transmission lines SL1~SLN, and the display device 100 is coupled to a plurality of control lines CL1~CL3. Wherein, the control lines CL1~CL3 are respectively arranged adjacent to the data transmission lines SL1~SLN of each partition, and the control lines CL1~CL3 respectively correspond to different display lines. In this embodiment, only nine partitions Z11 to Z33 are taken as an example. In other embodiments of the present invention, the number of partitions is not limited to this, and can be arbitrarily adjusted.

Hereinafter, please refer to FIG. 1 and FIG. 2 simultaneously. FIG. 2 is a schematic diagram of one of a plurality of partitions according to the first embodiment of the present invention. In this embodiment, taking the partition Z11 as an example, the partition Z11 includes a plurality of display pixels PX11~PXMN and a switch SW1. In detail, the display pixels PX11~PX1N are connected to the control terminal of the switch SW1 through the gate line GL1, the display pixels PX1N~PXMN are coupled to the first end of the switch SW1 through the trace CLP, and the second end of the switch SW1 is It is coupled to the control line CL1.

It is worth noting that the control terminal of the switch SW1 is coupled to the gate line GL1 of the zone Z11, and controls the switch SW1 to be turned on or off according to the zone enable signal on the gate line GL1, to divide the zone line control signal of the control line CL1 Import partition Z11.

In terms of the display pixel PX11~PXMN architecture, the display pixel PX1N is used as a vantage point. The display pixel PX1N includes transistors T1, T2 and pixel capacitor CLC. The control terminal of the transistor T1 is coupled to the second terminal of the switch SW1, the first terminal of the transistor T1 is coupled to the second terminal of the transistor T2, and the control terminal of the transistor T2 is coupled to the corresponding gate line GL1, The first end of the transistor T2 is coupled to the corresponding data transmission line SLN, and the pixel capacitor CLC is connected in series between the second end of the transistor T1 and the reference ground.

In terms of operation details, when the operation of updating the display screen of the partition is performed, it is exemplified that the display screen is updated only for the partition Z11. In the data update mode of the partition Z11, the gate lines GL1~GLM corresponding to the partition Z11 perform the gate scanning operation according to the first refresh frequency, and the data materials SL1~SLN corresponding to the partition Z11 also perform the data transmission according to the first refresh frequency During the operation, the control line CL1 provides the partition control signal according to the first refresh frequency, and performs the refresh of the display screen of the partition Z11 by the first refresh frequency. On the other hand, the other partitions Z12 to Z33 other than the partition Z11 work in the data holding mode, and refresh the display screens of the other partitions Z12 to Z33 at a relatively low second refresh frequency. In the embodiment of the present invention, the first refresh frequency may be 60 hertz (Hz), and the second refresh frequency may be 1 Hz.

In detail, when the zone Z11 is in the data update mode, the switch SW1 can be turned on or off according to the zone enable signal on the gate line GL1. When the switch SW1 is turned on according to the zone enable signal on the gate line GL1, the zone control signal on the control line CL1 can be transmitted to the display pixels PX11~PX1N through the turned-on switch SW1, for example, through the trace CLP The control terminal of the transistor T1 in the display pixel PX1N, and by controlling the conduction operation of the transistor T1, the display pixels PX11~PX1N perform the data refresh operation. In the data update mode, the partition control signal on the control line CL1 can perform the data refresh operation of the display pixels PX11~PX1N according to the relatively high first refresh frequency.

In contrast, when the zone Z11 is in the data holding mode, the zone control signal on the control line CL1 operates according to the relatively low second refresh frequency, and when the switch SW1 is activated according to the zone enable signal on the gate line GL1 When turned on, the partition control signal on the control line CL1 can be transmitted to the display pixels PX11~PX1N through the turned-on switch SW1, for example, through the trace CLP to the control terminal of the transistor T1 in the display pixel PX1N, and through the control The conducting operation of the transistor T1 causes the display pixels PX11 to PX1N to perform the data refreshing operation. In the data holding mode, the partition control signal on the control line CL1 can perform the data refresh operation of the display pixels PX11~PX1N according to the relatively low second refresh frequency.

It can be known from the above description that by setting the switch SW1 in each zone Z11~Z33, the zone update display screen can be performed only for one or more of the zones, such as Z11, for refreshing the display screen at the first refresh frequency For other partitions, for example, Z12 to Z33, the display refresh operation is performed at a second refresh frequency lower than the first refresh frequency to reduce power consumption of the display device.

With the setting of the switch SW1 of the partition Z11, even if multiple partitions Z11, Z21, and Z31 on the same line share a control line CL1, when the partition Z11 operates in the data maintenance mode, the switch SW1 receives the The control of the gate line GL1 prevents the zone Z11 from being affected by the refresh operation of the display screen at the first refresh frequency by other zones Z21 or Z31, and still performs the data refresh operation of each display pixel PX11~PXMN at the second refresh frequency. That is, by setting the switch SW1, it is possible to avoid the interaction between the partition Z11 and the other partitions Z21 and Z31 sharing the same control line CL1 due to different refresh frequencies.

The switch SW1 of the display device 100 of the present invention may be constructed by a transistor TSW. The control terminal of the transistor TSW is coupled to the gate line GL1 and used to receive the partition enable signal. The first end of the transistor TSW is coupled to the control line CL1, and the second end of the transistor TSW is coupled to the control end of the transistors (eg, transistor T1) in the plurality of display pixels PX11~PXMN in the zone Z11. The transistor TSW and the transistors T1 and T2 may be the same type of transistor. Therefore, the switch SW1 of the display device 100 of the present invention can be manufactured simultaneously with the matrix substrate in the manufacturing process of the array substrate of the display device without additional process cost or material consumption.

In the display device 100 of the present invention, when one of the zones Z11 to Z33 works in the data update mode, the zone Z11 works at the first refresh frequency (for example, 60 Hz), and the switch SW1 corresponding to the first refresh frequency is turned on Or disconnect. When the other zones Z12 to Z33 in each zone Z11 to Z33 work in the data holding mode, each zone Z12 to Z33 works at the second refresh frequency (for example, 1 Hz). Because the first refresh frequency is greater than the second refresh frequency, only some of the partitions (eg, partition Z11) use the first refresh frequency to perform the refresh operation of the display screen. On the other hand, the other zones Z12 to Z33 perform the refresh operation of the display screen at a lower second refresh frequency to enter the energy-saving power consumption state, so the power consumption can be reduced.

In FIG. 2, the control terminal of the switch SW1 is coupled to the gate line GL1 of the zone Z11, that is, the zone enable signal is provided by the gate line GL1 of the zone Z11, but the invention is not limited thereto. The control terminal of the switch SW1 can be coupled to any gate line of the zone Z11, that is to say, the zone enable signal can be provided by any gate line of the gate lines GL1~GLM in each zone Z11.

FIG. 3 is a schematic diagram for explaining the difference in leakage between different partitions of the display device of the present invention and the prior art partition update display screen. Please refer to FIG. 2 and FIG. 3 synchronously below. Among the partitions Z11 to Z33 of the display device 100, only the partition Z22 operates in the data update mode at the first refresh frequency (eg 60 Hz), and other partitions other than the display area Z22 (For example, Z12 and Z33) work in the data retention mode at the second refresh frequency (for example, 1 Hz). In FIG. 3, the partition Z22 is in the data update mode. When the partition Z22 refreshes the display screen at the first refresh frequency (for example, 60 Hz), the control line CL2, each gate line GL1~GLM and each data connected to the partition Z22 The transmission lines SL1 to SLN all operate corresponding to the first refresh frequency, that is, the pixel capacitors CLC of the display pixels PX11 to PXMN in the partition Z22 are refreshed at the first refresh frequency.

In FIG. 3, the partition Z12 is in the data holding mode. When the partition Z12 refreshes the display screen at the second refresh frequency (for example, 1 Hz), the gate lines GL1~GLM and the data transmission lines SL1~SLN connected in the partition Z12 are The operation corresponds to the second refresh frequency, but since the control line CL2 is shared with the zone Z22 in the data update mode, the control line CL2 corresponds to the first refresh frequency (for example, 60 Hz). Although the partition Z12 and the partition Z22 use the same control line CL2, the control terminal of the switch SW1 is coupled to the gate line GL1 of the partition Z12, so the switch SW1 of the partition Z12 is also turned on or off corresponding to the second refresh frequency open. Therefore, the partition Z12 is separated by the switch SW1 from the influence of the data update operation performed by the partition Z22 according to the first refresh frequency.

In this way, the difference in the optical performance between the displayed images on the partition Z12, the partition Z22, and the partition Z33 can be reduced, and no phenomenon such as crosstalk can occur. Therefore, the display device of the present invention can maintain good display quality when performing the partition update display screen.

In addition, the present embodiment exemplifies that each display pixel PX11 to PXMN includes two electrical bodies T1 and T2, but the present invention is not limited to this. That is, the present invention can also be applied to each display pixel PX11 to PXMN including two or more transistors.

4 is a schematic diagram of the circuit architecture of the first embodiment of the present invention. As shown in FIG. 4, the display device 400 of the partition update display screen of the present invention includes a multiplexer circuit 20, a gate driver 30 and a source driver 40. The output terminal of the multiplexer circuit 20 is coupled to the control lines CL1 to CL3 and the data transmission lines SL1 to SLN. When one of the partitions Z11 to Z33, for example, the partition Z11 operates in the data update mode, the control line CL1 at the output of the corresponding multiplexer circuit 20 operates according to the first refresh frequency. When other partitions, such as Z12 and Z13, operate in the data holding mode, the control lines CL2 and CL3 at the output of the corresponding multiplexer circuit 20 operate according to the second refresh frequency.

In addition, the above embodiment takes a multiplexer circuit 20 as an example. However, the multiplexer circuit 20 can be arbitrarily adjusted according to the number of partitions, or the multiplexer circuit 20 can be incorporated into multiple source drivers 40. Not set independently.

On the other hand, the output terminal of the gate driver 30 is respectively coupled to each gate line GL1~GLM, and when the partition Z11 works in the data update mode, the output terminal of the gate driver 30 corresponding to the partition Z11 works at the first refresh Frequency, when other partitions, such as partition Z21 and Z31 operate in the data holding mode, the output end of the gate driver 30 corresponding to the partition Z21 and Z31 works at the second refresh frequency.

In addition, the output terminals of the source driver 40 are respectively coupled to the data transmission lines SL1 to SLN, and when each zone Z11 works in the data update mode, the output end of the source driver 40 corresponding to the zone Z11 works at the first refresh frequency, When other partitions, such as the partition Z12 and the partition Z13, work in the data holding mode, the output end of the source driver 40 corresponding to the partition Z12 and the partition Z13 works at the second refresh frequency.

The above-mentioned second refresh frequency is the frequency used in the data holding mode. The embodiment takes the example of using 1 Hz for data holding. However, as long as the second refresh frequency is less than the first refresh frequency. For example, if transistor T1 or transistor T2 of each display pixel PX11~PXMN has poor off characteristics and large leakage, consider increasing the frequency used in data retention mode from 1 Hz to 5 Hz or higher to ensure The display quality of the partition update display screen.

5 is a schematic diagram of one of the partitions Z11 of the plurality of partitions Z11 to Z33 in the second embodiment of the present invention. The difference from the embodiment of FIG. 2 is that each of the zones Z11 to Z33 is provided with a switch SW2. In the second embodiment, the same parts as those in the first embodiment are denoted by the same reference numerals and the description is omitted, and the differences from the first embodiment will be described.

As shown in FIG. 5, in the second embodiment of the present invention, two switches, that is, a switch SW1 and a switch SW2, are provided in each zone Z11 to Z33, respectively. The first ends of the switches SW1 and SW2 are respectively coupled to the control line CL1 of the zone Z11. The second ends of the switches SW1 and SW2 are respectively coupled to the control ends of the transistors T1 of the display pixels PX11~PXMN in the zone Z11. The control terminal of SW1 is coupled to the gate line GL1 of the zone Z11, and the control terminal of the switch SW2 is coupled to the gate line GL2 of the zone Z11.

Therefore, in the second embodiment of the present invention, the control terminals of the transistors T1 of the display pixels PX11 to PXMN in the zone Z11 are driven by the two switches SW1 and SW2. When the gate line GL1 and the gate line GL2 of the zone Z11 are connected to turn on the switch SW1 and the switch SW2, the trace CLP in the zone Z11 and the control terminals of the respective transistors T1 of the display pixels PX11 to PXMN will be There can be a longer time to charge or discharge to the voltage level of the control line CL1. When the voltage level of the control terminal of each transistor T1 matches the voltage level of the control line CL1, it can ensure that each transistor T1 operates normally and can update the image data of the pixel capacitor CLC more effectively and completely.

In FIG. 5, the control terminal of the switch SW1 is coupled to the first gate line GL1 of the zone Z11, and the control terminal of the switch SW2 is coupled to the second gate line GL2 of the zone Z11, but the invention is not limited thereto. The control terminals of the switch SW1 and the switch SW2 can be respectively coupled to any two gate lines in the zone Z11.

In the second embodiment of the present invention, the two switches SW1 and SW2 are used to ensure the voltage level of the wiring CLP and the control terminal of each transistor T1, to ensure that each transistor T1 operates normally, and to update each pixel more effectively and completely Image data of capacitor CLC. However, the invention is not limited to this. That is, the voltage level of the control terminal of each transistor T1 of each display pixel PX11~PXMN in the zone Z11 can be made closer to the voltage level of the control line CL1 by more than two switches.

In summary, by adding a switch in each partition to the display device of the partition update display screen of the present invention, it is ensured that there is no interaction effect between the partitions. As long as it is each partition in the data retention mode, each of its internal transistors is in a state corresponding to the second refresh frequency, and the leakage of the pixel capacitor of each display pixel is small. Therefore, there will be no difference in optical performance between the partitions in the data retention mode, that is, no picture crosstalk or other phenomena will occur. Therefore, the display device of the embodiment of the present invention can maintain a good display quality when performing the partition update display screen.

Although the present invention has been disclosed as above with examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to the scope defined in the appended patent application.

20‧‧‧Multiplexer circuit 30‧‧‧Gate driver 40‧‧‧ source driver 100‧‧‧Display device CL1~CL3‧‧‧Control line CLC‧‧‧Pixel Capacitor CLP‧‧‧Trace GL1~GLM‧‧‧Gate line PX11~PXMN‧‧‧Display pixels SL1~SLN‧‧‧Data transmission line SW1, SW2‧‧‧ switch T1, T2, TSW‧‧‧transistor Z11~Z33‧‧‧ Division

FIG. 1 is a schematic diagram of a display device including multiple partitions according to a first embodiment of the present invention. 2 is a schematic diagram of one of a plurality of partitions in the first embodiment of the present invention. FIG. 3 is a schematic diagram showing the difference in leakage current between different partitions of the display device of the present invention and the conventional partition update display screen. 4 is a schematic diagram of the circuit architecture of the first embodiment of the present invention. 5 is a schematic diagram of one of a plurality of partitions in the second embodiment of the present invention.

CL1‧‧‧Control line

CLC‧‧‧Pixel Capacitor

CLP‧‧‧Trace

GL1~GLM‧‧‧Gate line

PX11~PXMN‧‧‧Display pixels

SL1~SLN‧‧‧Data transmission line

SW1‧‧‧switch

T1, T2, TSW‧‧‧transistor

Z11‧‧‧Division

Claims (10)

A display device, including: Multiple zones, corresponding to multiple gate lines, each zone includes: Multiple display pixels; A control line for transmitting a zone control signal; and A switch, coupled between the display pixels and the control line, is controlled by the partition enable signal of the gate line in the partition to be turned on or off. The display device according to item 1 of the patent application scope, wherein the display pixels in each partition are arranged into a plurality of display rows and a plurality of display columns, and the display columns are respectively coupled to a plurality of gate lines, the These display lines are respectively coupled to multiple data transmission lines. The display device as described in item 2 of the patent application scope, wherein each of the display pixels includes: A first transistor whose control terminal is coupled to the second terminal of the switch; A second transistor having a first end coupled to the data transmission line, a first end of the first transistor coupled to a second end of the second transistor, a control terminal of the second transistor coupled to The corresponding gate line; and A pixel capacitor is connected in series between the second end of the first transistor and the reference ground. The display device according to item 2 of the patent application scope, wherein the zone enable signal is provided by one of the gate lines in each zone. The display device according to item 1 of the patent application scope, wherein the switch is a transistor, a first end of the transistor is coupled to the control line, and a second end of the transistor is coupled to the first transistor The control end of the transistor receives the zone enable signal. The display device according to item 1 of the patent application scope, wherein when each of the partitions operates in a data update mode, the corresponding switch is turned on, and each of the partitions operates at a first refresh frequency, when each of the partitions operates In a data holding mode, the corresponding switch is turned off, and each of the partitions operates at a second refresh frequency, where the first refresh frequency is greater than the second refresh frequency. The display device as described in item 6 of the patent application scope further includes: A multiplexer circuit, the multiplexer circuit is coupled to the control line. The display device as described in item 7 of the patent application scope, wherein when each of the partitions works in the data update mode, the corresponding control line of the multiplexer circuit operates according to the first refresh frequency, and when each of the areas When working in the data holding mode, the corresponding control line operates according to the second refresh frequency. The display device as described in item 6 of the patent application range, wherein the first refresh frequency is 60 Hz and the second refresh frequency is 1 Hz. The display device as described in item 1 of the patent application scope further includes: A plurality of gate drivers, respectively coupled to the gate lines, for respectively providing a plurality of gate drive signals; and A plurality of source drivers are respectively coupled to the data transmission lines to provide a plurality of source driving signals.

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