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TWI335625B - Dielectric interface for gruop iii-v semiconductor device - Google Patents

Dielectric interface for gruop iii-v semiconductor device Download PDF

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Publication number
TWI335625B
TWI335625B TW095143047A TW95143047A TWI335625B TW I335625 B TWI335625 B TW I335625B TW 095143047 A TW095143047 A TW 095143047A TW 95143047 A TW95143047 A TW 95143047A TW I335625 B TWI335625 B TW I335625B
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Taiwan
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region
chalcogenide
dielectric
disposed
confinement
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TW095143047A
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TW200735216A (en
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Justin Brask
Suman Datta
Mark Doczy
James M Blackwell
Matthew Metz
Jack Kavalieros
Robert Chau
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Intel Corp
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/60Electrodes characterised by their materials
    • H10D64/66Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/691Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates 
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/015Manufacture or treatment of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/40FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/473High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having confinement of carriers by multiple heterojunctions, e.g. quantum well HEMT
    • H10D30/4732High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having confinement of carriers by multiple heterojunctions, e.g. quantum well HEMT using Group III-V semiconductor material
    • H10D30/4735High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having confinement of carriers by multiple heterojunctions, e.g. quantum well HEMT using Group III-V semiconductor material having delta-doped or planar-doped donor layers
    • H10D64/013
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/60Electrodes characterised by their materials
    • H10D64/66Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/665Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/60Electrodes characterised by their materials
    • H10D64/66Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/681Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
    • H10D64/685Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered being perpendicular to the channel plane
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503Nitride Group III-V materials, e.g. AlN or GaN
    • H10P14/6312
    • H10P14/6339
    • H10P14/69391
    • H10P14/69392

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  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Formation Of Insulating Films (AREA)

Description

1335625
(1) 九、發明說明 【發明所屬之技術領域】 本發明係有關III - V族半導體裝置的領域。 【先前技術】 今曰的大部份積體電路都以矽,週期表第IV % 種元素的基底。III _v族元素的化合物諸如砷 (GaAs)、銻化銦(InSb)、和磷化銦(InP),都爲已知套 矽遠較爲優良的半導體性質,包括更高的電子移動霉 和速度。不同於III一 V族化合物者,矽容易地氧众 成幾乎完善的電介面。此種大自然的禮物促成有數個 層的二氧化矽之近乎完全的電荷約束。相反地,III-化合物的氧化物具有不良的品質,例如,彼等包含起 阱電荷,且在化學上係複雜者。 量子井場效電晶體(QWFET)業經以蕭特基金屬 (Schottky metal gate)和InSb井爲基底而提出。彼€ 低有效功率耗散上比以矽爲基的技術顯示出更有希^ 彼等也顯示出改良的高頻性能。可惜地,因爲閘極ί 例如 InSb/AlInSb表面上的費米能階釘札(Fermi pinning)所致低蕭特基屏障,所以有高的關閉狀態 state)閘極漏電流。 高一 k閘極絕緣體業經提出用於QWFETs。參 2005年1月3日提出申請的序號1 1 /0208,378, 的一 化鎵 有比 及飽 而形 原子 V族 陷, 閘極 在降 ,且 屬在 level (off- 例如 稱爲
QUANTUM
WELL
TRANSISTOR
USING
HIGH (2) (2)1335625 DIELECTRIC CONSTANT DIELECTRIC LAYER"。不過, 在商—k材料與例如inSb/A1InSb表面之間的介面上仍有 問題。 【發明內容及實施方式】 本發明係關於在一半導體裝置中將一高k電介質與一 11V族約束區相接介之方法和裝置。於下面的說明中, 述及許多特定的化學以及其他細節,以期提供對本發明的 徹底了解。技藝人士顯而易見,本發明之實施並不用此等 特定細節。於其他情況中,習知的處理步驟並未多加贅 述’以免不必要地混淆本發明。 圖1例示在金屬閘極1 3與單晶矽體或基材1 0之間的 介面。最典型地,矽10包含帶有用於控制電晶體的閘極 13的場效電晶體之通道區。當通道區與閘極之間的絕緣 層之等效氧化物厚度(EOT)在5-30A範圍內且較佳者在 10- 15A範圍內之時,此等裝置表現得特別好。雖然二氧 化矽(Si 02)提供優良的電介質,但以此等薄的層,難以得 到可靠的二氧化矽電介質。倒不如使用高k材料(如,10 或更大的介電常數者)。如圖1中所示者,先在矽1〇之上 形成(或爲原有的)二氧化矽區11。然後,在二氧化矽區 11上面形成高k電介質12,諸如二氧化給(Hf02)。其 次,在高k電介質上形成金屬閘極,典型地爲具有靶向功 函數者。該高k電介質諸如Hf02或二氧化鉻(Zr02)提供 一優異的介面。高k電介質可在低溫沈積程序中利用有機 -6- - (3) 1335625 先質形成,諸如供HfO2沈積用的烷氧化物先質在原子層 沈積(ALD)程序中形成。用電子束蒸發或濺鍍形成的金屬 閘可爲鈾、鎢、鈀、鉬或其他金屬。 EOT,如圖1結構的右邊所示者’包括約4A’係與 矽10的上表面相結合,其由靠近單晶結構的表面之缺陷 所致。在此之上,顯示出約5A的二氧化矽區11。之後’ 於ALD程序中形成高k電介質’其EOT爲3— 4A。對於 φ 圖1中所示結構所得EOT爲I2 - 13人。 於圖1結構的左方,顯示出各區的物理厚度(ρτ)°如 可看出者,與Si02區11相比之下,該高k電介質相當地 厚(約20A)。此相當厚的區可促成具有低EOT(3 - 4A)的 可靠、高品質電介質之形成。
如稍早提及者’難以針對圖1結構製成相應的介面’ 其中係使用ΠΙ-V族化合物。從此等化合物形成的氧化 物都具有不良的品質,且對高k電介質不能良好地黏附。 φ 於圖2中係顯示,下文中所更完整描述的在ΠΙ-V 族化合物與高k電介質之間的介面。III - ν族區20係連 同介面區21的橋聯硫(S)原子一起例示,以作爲硫族兀素 化物介面區的一具體實例。如所要描述者’此等橋聯原子 可促成對高k電介質區22(於一具體實例中所示爲Hf02) 之更佳配合。 圖3結構的EOT包括約6A,係經結合以III — V族化 合物的上表面,諸如約束區20,以及特別是在此區上未 完全移除掉的原有的氧化物,和約束區內的晶格缺陷。介 (4) 1335625 面21可爲硫族元素諸如氧(〇)、S、硒(Se)、 重的硫族元素釙(P〇)因其放射性而爲不利者) 的EOT在所示具體實例中爲約3A,對應於| 此區的PT爲3-10A。於此上方,形成有一高 22,其具有約2 0A之PT及3-4A之EOT。 似於圖1的金屬閘1 3之金屬閘極2 3。 於一典型電晶體中,在變質緩衝層或 AllnSb)之間約束有例如InSb之量子井。此等 井更高的能帶間隙以緩和電子井所具窄能帶間 電及崩潰之影響。 於圖3中,再度地於電介質區30與III 一 32之間顯示出該硫族元素化物介面區。該硫 爲"X"而原子層數目顯示爲〃。對於氧, 大於1,例如,3,可以使用立體okioxidizing 過氧化二_第三丁基或過氧化二-異丙基)以 脫離基的含〇 —取代基(如0— t Bu),其也可 準ALD先質反應。此可進一步防止與大氣的 S或Se較佳者爲等於1、2或3。此膜可從單 積。複數種二_有機二_硫一族元素化物的任 以使用。 於圖5中,係例示—種程序,從πι_ν 生長50開始’其典型地係在第一約束層上 地,如已提及者,III 一 V族井可包含InSb或 提及者,於另一程序51中,係在該量子井上 碲(Te)。(較 。介面區 2 1 :個原子層。 k電介質區 後,使用類 約束層(如 層具有比該 隙對裝置漏 V族約束區 族兀素經表 η典型地爲 agent(例如 遞送帶龐大 有利地與標 反應性。該 價二聚物沈 何一者都可 族量子井的 發生。再度 InP。如已 形成約束區 -8 - (5) (5)1335625 或層。此對應於,例如圖2的區20。該約束層典型地爲 與該井相容,不過,具有較大能帶間隙之材料。對於 InSb井,可以使用類金屬AllnSb。程序50和51可以使 用例如分子束磊晶或金屬有機化合物氧相沈積來進行。 在形成硫族元素化物層之前,要移除掉約束層上的原 有的氧化物和任何其他氧化物。圖5的程序52可經由利 用酸,例如檸檬酸、HC1或HF處理表面而進行。 其次,如程序53所不者,形成硫族元素化物層。此 形成程序係於一具體實例中,配合圖4A和4B予以顯 示。於圖4A中,顯示二苯基二硫化物之化合物,其最終 會留下在含類金屬的III- V族約束區與高k電介質之間 倂列的硫族元素化物膜。也可以使用其他的二-硫族元素 化物諸如二硒化物。再者,也可以使用其他先質諸如苯 環、或類似者。於二-苯基的情況中,一個苯基顯示係經 約束層的鍊原子所置換,而另一個,被來自形成高k電介 質中所用的先質之一的例如Hf或A1原子所置換。此留 下,如圖4B中所示者,在該二-硫族元素化物包含S之 情況中,留下S橋聯原子。如此,二苯基原子中之一者在 程序53中被置換,而另一者,在圖5的程序54中,被高 k電介質所用先質所置換。使用別的二-硫族元素化物也 可達到相同的結果。可以使用一般用來形成Hf02或Zr02 之先質。 於一具體實例中,約束層爲 AllnSb,如已提及者。 在用到此物之情況中,可以使用ai2o3作爲高k電介質以 -9- (6) (6)1335625 減低價數誤配。Al2 03可以先用三甲鋁(TM A)和水先質以 ALD法予以沈積。 最後,如圖5中所示者,進行金屬閘極沈積5 5。再 度地,可以使用普通的處理來形成閘極。由於III- V族 材料可能具有低熔點,例如InSb爲525t,所以在一具 體實例中,係使用 ALD來進行閘極沈積。在使用 Al2〇3 作爲高k電介質的情況中,可以使用鋁閘極來提供更大的 相容性。 圖6例示經由使用高k電介質諸如Al2〇3和金屬閘極 所得在閘極漏電流上的減低,此係與蕭特基金屬閘極相反 者。如在圖6中可輕易看出者,使用高k電介質可使漏電 流差異較低數個數量級。圖6的結果係來自鋁閘極、 Al2〇3電介質,AllnSb約束層及InSb量子井。 圖7例示可以用上述處理製造出的電晶體之結構。此 具體實例特別適合用於似耗乏模式裝置,因爲,例如此時 閘極係不被埋置於約束層內,如圖8的裝置者。於一具體 實例中,一較低約束區包括一 Al.i5In.85Sb層,此係形成 於例如半絕緣性GaAs基板之上。然後,在該較低約束層 上生長InSb之例如,量子井72。其次,在一具體實例 中,形成包含Al.2QIn.8QSb的上約束層73,此層包括一施 體區,更特定言之,於一具體實例中係一Te摻雜區。此 Te摻雜可供給載體到量子井73。圖7的多層結構可以使 用分子束磊晶或金屬有機化學氣相沈積法來生長。該經摻 雜的施體區係經由使Te(或Si)摻雜劑從例如固體來源流 -10- - (7) 1335625 進分子束磊晶室內而形成。 層73的厚度與閘極78的功函數,共同決定該電晶體 的底限電壓,且如稍早提及者,提供一似耗乏模式裝置於 圖7的具體實例。因此對該閘極選擇較低的功函數以減低 . 底限電壓。於圖7中也例示一源極接觸76和汲極接觸 77,以及鋁閘極78。舉例而言,在一具體實例中,層70 可爲3微米厚,量子井72可爲3奈米厚,約束層73可爲 φ 5奈米厚,且Te、5_摻雜施體區可經摻雜到 1— 1.8xl012cm·2 之層次,μ 等於 18 — 閘 極長度爲85奈米。 圖8例示另一具體實例,其具有一凹陷閘極用以增加 電壓底限値來提供更似增強模式裝置。再度地,其中有一 較高能帶間隙,較低約束層80、一量子井81、及由一蝕 刻劑停止層90分隔的兩經摻雜的約束層9 1和92。兩層 91和92都經摻雜,如分別由5摻雜平面82和89所示 φ 者。高k電介質8 7猶如該金屬閘極8 8 —般係凹陷到該層 92之中。正是此凹陷及對閘極88所用之功函數金屬的選 擇,而提供經增加的底限電壓。諸層厚度、摻雜量、等等 可相同於圖7的具體實例者。增加的層92可爲45奈米厚 度者。 如此,乃說明在數個具體實例中,介於III _V族約 束區與高k電介質區之間的介面,以及使用該介面的裝 置。 -11 - (8) 1335625 【圖式簡單說明】 圖1例示先前技藝在矽基材與金屬閘極之間的高k電 介質介面。 圖2例示111 — V族約束區而與金屬閘之間的介面, 包括一高k電介質與硫族元素化物區。 圖3例示透過硫族元素化物區而與高k電介質接介之 約束區。 φ 圖4A例示二苯基-二硫化物化合物,其苯基經置 換。 圖4B例示在約束區與高k電介質之間之圖4A化合 物。 圖5例示在一 III- V族半導體裝置中形成一金屬閘 極所實施之程序。 圖6爲一圖表,係例示使用高k電介質,相較於一蕭 特基金屬閘極,對於閘極漏洩之效益。 • 圖7爲具有氧化鋁(A1203)、高k電介質層的半導體 裝置之橫截面立視圖。 圖8爲具有高k電介質和凹下的金屬閘極之III - V 族半導體裝置之橫截面立視圖。 【主要元件符號說明】 1 0 :單晶矽體或基材 1 1 :二氧化矽電介質 122,22,87 :金屬層 -12- (9)1335625
13,23,88:金屬閘極 20 : III — V 族區 2 1 :介面區 30 :電介質區 32 : III— V族約束區 70 : Al.15IN.85Sb 層 72,73,8 1 :量子井 7 6 :源極接觸 7 7 :汲極接觸 7 8 :閘極 8 0 :下約束層 82,89: <5摻雜平面 91,92:經摻雜上約束層 90 :蝕刻劑停止層
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Claims (1)

1335625 --- 竹年6月日修(更)正替換頁 十、申請專利範圍 附件3Α: 第95 1 43047號專利申請案 中文申請專利範圍替換本 民國99年6月21日修正 1. 一種製造半導體裝置之方法,其包括: 生長一III— V族化合物之第—區; 在該第一區上生長一約束區; 在該約束區上形成硫族元素化物區; 在該硫族元素化物區上形成一電介質區,其中該硫族 元素化物區於該約束區與該電介質區之間包括[〇]η橋聯( 其中η大於1 )、或二硫化物橋聯或二硒化物橋聯;及 在該電介質區上形成一金屬閘極。 2. 如申請專利範圍第1項之方法,其包括在形成該硫 族元素化物區之前,從該約束區移除原有的氧化物。 3. 如申請專利範圍第1項之方法,其中該第一區包含 InSb或InP ° 4 ·如申請專利範圍第3項之方法,其中該電介質區包 含高k電介質。 5. 如申請專利範圍第4項之方法,其中該高k電介質 包含Hf02。 6. —種製造半導體裝置之方法,其包括: 形成一InSb井; 在該InSb井上形成一AllnSb約束區: 從該AllnSb區的表面移除原有氧化物;及 1335625 年&月修r更)正替換買 -—||- —·* ·Ι _ _ —~ 在該AllnSb區的表面上形成一Al2〇3層。 7. 如申請專利範圍第6項之方法,其中該Al2〇3的形 成包括使用三甲基鋁先質和水之原子層沈積(ALD)法。 8. 如申請專利範圍第6項之方法,其中該原有氧化物 的移除包括用酸處理AllnSb區的表面。 9. 如申請專利範圍第6項之方法,其中該InSb係在底 下之AllnSb層上形成。 10. 如申請專利範圍第9項之方法,其中該Ailnsb區 的形成包括形成Si或Te的施體區。 11. 一種半導體裝置,其包括: — I n S b 區 I —經配置在該InSb區上的AllnSb區; —經配置在一硫族元素化物區上的A丨2 0 3區,該硫族 元素化物區經配置在該A11 n S b區上,其中該硫族元素化物 區於該AllnSb區與該八丨2〇3區之間包括[〇]n橋聯(其中n大於 1 )、或二硫化物橋聯或二硒化物橋聯;及 一經配置在該A12 ◦ 3區上的A1閘極。 12_如申請專利範圍第11項之裝置,其中該InSb區爲 由該AllnSb約束區所約束的量子井。 13. 如申請專利範圍第12項之裝置,其中該八12〇3爲 —具有厚度小於30A之層。 14. 如申請專利範圍第12項之裝置,其中該約束區包 含經Si或Te摻雜之區。 1 5 ·如申請專利範圍第1 4項之裝置,其包括經配置在 -2 - 1335625 * Ϊ 上- ' —1 —^ ί m - - - 一· (ί1年厶月〒細正替換頁 • 】— , _ k間極的相反側上之源極和汲極之接觸。 16. 如申請專利範圍第1 5項之裝置’其中該金屬閘極 係凹陷進入該AllnSb區以提供—增強模式電晶體。 17. —種半導體裝置,其包括: 在第一區中的III— V族元素的化合物; 一約束區’其具有比該第一區更寬的能帶間隙; 一經配置在該約束區上的硫族元素化物區: φ —經配置在該硫族元素化物區上的高k電介質,其中 該硫族元素化物區於該約束區與該高k電介質區之間包括 [〇]n橋聯(其中η大於1)、或二硫化物橋聯或二硒化物橋聯 :及 —經配置在該高k電介質上的金屬閘極。 18. —種半導體裝置,其包括: 在第一區中的III— V族元素的化合物; 一約束區,其具有比該第一區更寬的能帶間隙: φ 一經配置在該約束區上的硫族元素化物區; 一經配置在該硫族元素化物區上的高k電介質;及 一經配置在該高k電介質上的金屬閘極,其中該硫族 元素化物區包含硫。 19. 一種半導體裝置,其包括: 在第一區中的ιπ—ν族元素的化合物; —約束區,其具有比該第一區更寬的能帶間隙; 一經配置在該約束區上的硫族元素化物區; 一經配置在該硫族元素化物區上的高1"®介質;及 -3- 1335625 h年6九21 q ;遠(史)正m I * τ π- . - —---— · II 一經配置在該高lc電介質上的金屬閘極,其中該硫族 元素化物區包含硒。
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