1365024. 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種半導體製程技術，尤指一種電路 板及其製法。 【先前技術】 隨著電子產業的蓬勃發展，電子產品亦逐漸邁入多功 能、高性能的研發方向。為滿足半導體封裝件高積集度 (Integration)以及微型化（Miniaturizati〇n)的封裝 需求，承載半導體晶片之封裝基板，逐漸由單層板演變成 多層板（Multi-layer Board)，俾於有限的空間下，藉 由層間連接技術（lnterlayer Connecti〇n)以擴大封裝 基板上可利用的線路面積，以因應高電子密度之積體電路 (IntegratedCircuit)的使用需求；為此，遂發展出一 種增層技術(build-up)，亦即在一核心電路板(咖 cirxint board)表面利用線路增層技術交互堆疊多層介 電層及線路層，並於該介電層中開設導電盲曰孔 (conductive via)以供上、下層線路之間電性連接。 為因應微處理器、晶片組、繪圖晶片與特殊應用積體 電路（朦）等高效能晶片之運算需要，佈有線路之半導體 板亦需提昇其傳遞晶片訊號、改善頻寬、控制阻抗 專功月匕，以因應高"◦數封裝件的發展； 封裝件輕薄短小、多功萨丄土— 々付。千等體 的開發方向，封裝基板二^ 高線路密度及高頻化 半導體封步其你制私"朝 線路及小孔徑發展；現有 、土衣壬攸傳統1〇〇微米之線路尺寸，已縮減 110822 5 1365024 » 域在⑻〇微米以下’其中，包括導線寬度⑴㈣咖) 及線路間距（space)等持續朝向更小的線路精产進/研 發。 - 請參閱第Μ至1G圖所示’係顯示習知封裝基板之製 法，如第1A圖所示，提供一核心板10，該核心板1〇 = 有兩相對之表面10a，於該表们0a上形成有核心線路層 ιοί，並於該核心板10中形成有導電通孔1〇2，以電性丄 接該核心板10表面l〇a之核心線路層1〇1，·如第Μ圖所 示，於該核心板10之表面10a及其上之核心線路層^ 上形成有第-介電層12a’且該第一介電層…中形 複數介電層開孔i20a，以顯露部分之核心線路層如 1 =示，於該第一介電層仏上及其㈣層開孔 2〇a表面上形成有導電層13,且於該導電層^上 阻層14，並使該阻層〗4 _來成 乂 詨導雷屛n夕却 形成有複數開口區140以露出 :乂 表面’且該開口區14〇係顯露各該介 =層開孔l2Qa，以作為後續電鍍線路層之線路槽； 1D圖所示，於該阻屉 弟 . ^ . s 14之開口區140中的導電層13上 尾銀幵/成第一線路層1(=; 19n ^ 3 15a且於該第一介電層12a之介電 層開孔12〇a中形成第一 电 核心線路層ΠΠ;如孔151a，以電性連接至該 覆蓋之導電層13，以丄所不，移除該阻層14及其所 电曰，从露出該第一線路# 所示，於該第一線路屏P料層15a，如第1F圖 層結構16，該婵15a及弟一介電層12a上形成有增 12b、形成於該第二八 卜令主/弟一；丨電層 ;丨電層上之第二線路層15b、以及複 110822 1365024 $ 脱之第二： 電性連接該第二線路層 『之苐導電盲孔跡其中部份之第二導電盲孔咖 電性連接該第—線路層15a;如第ig圖所示於該增層 結構16上形成錢數電性接觸墊164，且於 16 ,形成有防焊層17,並於該防焊層17中形成有複= 防烊層開孔1 70以對應露出各該電性接觸墊〗64 ^ 上述製法中，由於該第一導電盲孔151</ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; [Prior Art] With the rapid development of the electronics industry, electronic products have gradually entered the direction of multi-functional and high-performance research and development. In order to meet the high integration and integration requirements of semiconductor packages, package substrates carrying semiconductor wafers have gradually evolved from single-layer boards to multi-layer boards. In the space, the interlayer connection technology (lnterlayer Connecti〇n) is used to expand the available circuit area on the package substrate to meet the demand for the use of integrated circuits with high electron density; Build-up, that is, on the surface of a core circuit board (Cirxint board), a plurality of dielectric layers and circuit layers are alternately stacked by a line build-up technology, and conductive blind holes are formed in the dielectric layer (conductive Via) for electrical connection between the upper and lower lines. In order to meet the computing needs of high-performance chips such as microprocessors, chipsets, graphics chips, and special application integrated circuits (朦), the semiconductor boards with lines need to improve their transfer of chip signals, improve bandwidth, and control impedance. The new moon, in response to the development of high-quote packages; the package is light and short, and it is multi-functional. The development direction of the thousand-throw body, the package substrate, the high-density line, the high-frequency semiconductor, the step-by-step development of the high-frequency semiconductor, and the development of the existing line. Reduction 110822 5 1365024 » Domains below (8) 〇 micron 'including wire width (1) (four) coffee) and line spacing (space) continue to lean toward smaller lines. - Please refer to the method of displaying the conventional package substrate as shown in Fig. 1 to Fig. 1G. As shown in Fig. 1A, a core board 10 is provided, which has two opposite surfaces 10a on the table. A core circuit layer ιοί is formed on the 0a, and a conductive via hole 1〇2 is formed in the core board 10 to electrically connect the core circuit layer 1〇1 of the surface of the core board 10, such as the third layer. As shown in the figure, a first dielectric layer 12a' is formed on the surface 10a of the core board 10 and a core circuit layer thereon, and a plurality of dielectric layer openings i20a are formed in the first dielectric layer. a portion of the core circuit layer is as shown in FIG. 1 , a conductive layer 13 is formed on the surface of the first dielectric layer and the (4) layer opening 2〇a, and the resist layer 14 is disposed on the conductive layer The resist layer 〖4 _ 乂詨 乂詨 乂詨 屛 屛 却 却 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕a line slot; as shown in the 1D diagram, the silver layer / the first circuit layer 1 (=; 19n ^ 3 15a) is on the conductive layer 13 in the open area 140 of the barrier. A first electrical core circuit layer is formed in the dielectric layer opening 12a of the dielectric layer 12a; for example, the hole 151a is electrically connected to the covered conductive layer 13 to remove the resist layer. 14 and its electric device, as shown by the first line #, in the first circuit screen P layer 15a, such as the first F layer structure 16, the 婵15a and the first dielectric layer 12a are formed with 12b Formed in the second and eighth orders of the master / brother one; the electric layer; the second circuit layer 15b on the electric layer, and the complex 110822 1365024 $ second: the electrical connection of the second circuit layer Conductive blind vias, wherein a portion of the second conductive vias are electrically connected to the first circuit layer 15a; as shown in the ig diagram, the money electrical contact pads 164 are formed on the buildup structure 16, and A solder resist layer 17 is formed, and a plurality of anti-corrugated layer openings 1 70 are formed in the solder resist layer 17 to correspondingly expose the respective electrical contact pads. 64 ^ In the above manufacturing method, the first conductive blind vias 151
第-介電们2a之介電層開孔⑽中，而該介電：二 12〇a通常係以雷射鑽孔形成，而該雷射鑽孔一次僅能鑽 —個孔’即㈣雷射搶之移動速度極，决，亦無法同時完成 ，數個介電層開1 12Ga，使得生產速度受限而無法提 昇，因而降低生產量。 又該雷射鑽孔形成之介電層開孔120a係為外大内小 之錐形孔，且於該錐形孔之底部因雷射形成有膠渣，當該 介電層開孔120a之孔徑很小，於該介電層開孔12〇&底部 _之膠渣不易移除，使得該介電層開孔12〇a之孔壁、介電 層開孔120a中之核心線路層1〇1等表面與導電層13之間 的結合性不佳，且該介電層開孔120a顯露該核心線路層 ιοί之底部的口徑較小，因而降低該第一導電盲孔i5ia 與核心線路層1〇1之接觸面積’使得該第一導電盲孔151a 與核心線路層101之間的結合性降低，進而影響電性連接 的可靠度。 且該雷射鑽孔之光束直徑有其限制，並無法持續縮 因而影響高密度佈線之使用需求，有礙於細線路製程 110822 7 1365024 能力之提升。 此卜該I知封裝基板具有核心板，使得整體厚 度增加，而無法達到薄小之目的。 目此’如何提高形成介電·層開孔之速度、並且提高形 介電層開孔中之導電盲孔與其電性連接之線路之 間的結合強度、及縮，】、介雷恳 '' 電層開孔之孔徑以提高佈線密 度，仍存在其技術瓶頸而有待克服。 【發明内容】 鑑於以上所述習知技術之缺點，本發明之主要目的係 提供一種電路板及其製法，能提高形成開孔之速度。〃 …本發明之又-目的係提供一種電路板及其製法，能提 介電層開孔中之導電柱與其電性連接之線路 之間的結合強度。 j 之再一目的係提供一種電路板及其製法.，能縮 h W電層開孔之孔徑以提高佈線密度。 為達上述及其他目的，本發明揭露一種電路板，係包 括.第一介電層，俜且右笛 ± 、 .. 係八有第一表面及第二表面；第一線路 層’係嵌埋於該第一介雷屏坌 * , 7丨電層之第一表面中，且顯露於該 Ί層之第-表面；複數第__導電柱，係設於該第 電層中’並電性連接該第—線路層，且該第—導電柱之 面係顯露於第一介電 於該第-介電乂 增層結構，係設 於註第’該增層結構具有複數形成 連接至該第一導電柱。 电任 110822 8 1365024 依上述之電路板，該第二線路層復包括複數電性連接 墊，且該電性連接墊係形成於該第一導電柱上，該電性連 接墊之直徑係大於、等於或小於該第一導電柱之外徑。 依上述之結構，該增層結構係包括有至少一第二介電 \層、設於該第二介電層上之第二線路層、以及複數設於該 ^第二介電層之令並電性連接設於該第二介電層上、下面之 第二線路層的第二導電柱；其中，該第二線路層復包括複 數電性連接墊，且該電性連接墊係形成於該第二導電柱 鲁上，該電性連接塾之直徑係大於、等於或小於該第二導電 柱之外徑；復包括複數第二電性接觸墊，係設於該增層結 構最外層之第二線路層，並於該增層結構上覆設有第二防 焊層，於該第二防焊層中設有複數個第二防焊層開孔，以 對應露出各該第二電性接觸墊。 該第一線路層復包括複數第一電性接觸墊，於該第一 線路層及第一介電層之第一表面覆設有第一防焊層，該第 聲一防焊層具有複數第一防焊層開孔，以對應露出各該第一 電性接觸墊。 本發明復提供一種電路板，係包括：第一介電層，係 具有第-表面及第：表面，於該第二表面設有複數第日一線 槽；第一線路層，係嵌埋於該第一介電層之第一表面中， 且顯露於該第-介電層之第—表面；I數第—導電柱，係 設於該些第-線槽内之第—介電層中，並電性連接該第一 線路層；以及增層結構，係設於該第一介電芦之第二表 面、第'線槽及第-導電柱上，且該增層結構具有形：； 110822 9 1365.024 該第線槽中之第二線路層，且使部份之第二線路層對庶 電性連接各該第一導電柱。 〜 依上述之電路板，該第二線路層復包括複數電性連接 墊，且該電性連接塾係形成於該第一導電柱上，該電性連 接塾之直&係大於、等於或小於該第__導電柱之外徑。 依上述之結構，該第一線路層復包括複數第一電性 觸墊，於該第一線路層及第一介電層之第-表面覆設有第 :二二於該第一防焊層中設有複數個第-防焊層開 十應路出各該第一電性接觸墊。 該增層結構係包括有至少一具有第 !層數設於該第二介電層之第二線槽中之第二線路層:： 及複數設於該第二介電 二線路層及第1二J 連接該第一線槽中第 二線路層之線路層之第二導電柱’又該第 層復包括複數電性介電層之表U第二線路 ㈣且該些電性連接㈣對應設於 第二導電電性連接墊係大於、等於或小於該 結構最外層之第，線弟二電性接觸墊，係設於該增層 焊層，該第二防^增層結構上並設有第二防 出各該第二有㈣”二㈣相孔輯應露 载板本種電路板之製法，係包括··提供-承 層上形成有第—導^成有第―線路層；於該第一線路 導電柱上形：有第於該承载板、第-線路層及第-成有第-介電層；移除部份之第一，以 110822 10 1365.024 =低其厚度並露出該第—導電柱之端面；卩及於該第- 二電層及第一導電柱上形成有增層結構，該增層結構具有 複數形成於該第二纟面上之第二線路層 ，且該第二線路層 電性連接至該第一導電柱。 依上述之電路板之製法，該第二線路層復包括複數電 性連接墊，且該電性連接墊係形成於該第一導電桎上，該 電性連接墊之直徑係大於、等於或小於該第一導電柱之外 徑。The dielectric-layer 2a is in the dielectric layer opening (10), and the dielectric: two 12〇a is usually formed by laser drilling, and the laser drilling can only drill one hole at a time, that is, (four) thunder The speed of shooting is very high, and it can't be completed at the same time. Several dielectric layers open 1 12Ga, which makes the production speed limited and cannot be improved, thus reducing the production. The dielectric layer opening 120a formed by the laser drilling is a small outer tapered hole, and a molten metal is formed at the bottom of the tapered hole, and the dielectric layer opening 120a is formed. The pore size is small, and the slag of the dielectric layer opening 12 amp & bottom is not easily removed, so that the dielectric layer opening 12 〇 a hole wall, the dielectric layer opening 120 a core circuit layer 1 The bonding between the surface of the first layer and the conductive layer 13 is not good, and the opening of the dielectric layer opening 120a reveals that the diameter of the bottom of the core circuit layer is small, thereby reducing the first conductive blind hole i5ia and the core circuit layer. The contact area of 1〇1 reduces the bond between the first conductive blind via 151a and the core wiring layer 101, thereby affecting the reliability of the electrical connection. Moreover, the diameter of the beam of the laser drilling has its limitation, and it cannot be continuously reduced, thus affecting the use requirements of the high-density wiring, which hinders the improvement of the capability of the thin line process 110822 7 1365024. Therefore, it is known that the package substrate has a core plate, so that the overall thickness is increased, and the purpose of thinness cannot be achieved. Therefore, how to increase the speed of forming the dielectric layer opening and increase the bonding strength between the conductive blind holes in the opening of the dielectric layer and the electrically connected lines, and shrinkage, The aperture of the electrical layer opening to increase the wiring density still has its technical bottleneck and needs to be overcome. SUMMARY OF THE INVENTION In view of the above disadvantages of the prior art, the main object of the present invention is to provide a circuit board and a method of manufacturing the same that can increase the speed at which openings are formed. Further, another object of the present invention is to provide a circuit board and a method of manufacturing the same that can improve the bonding strength between a conductive post in an opening of an electrical layer and a line to which it is electrically connected. A further object of the present invention is to provide a circuit board and a method of manufacturing the same, which can reduce the aperture of the opening of the electric layer to increase the wiring density. To achieve the above and other objects, the present invention discloses a circuit board comprising: a first dielectric layer, and a right flute ±, .. system has a first surface and a second surface; the first circuit layer is embedded In the first surface of the first dielectric layer, the first surface of the electrical layer, and exposed on the first surface of the germanium layer; a plurality of __ conductive pillars are disposed in the first electrical layer Connecting the first circuit layer, and the surface of the first conductive pillar is exposed to the first dielectric layer in the first dielectric interlayer structure, and is provided in the first portion of the layered structure having a plurality of formations connected to the first A conductive column. In the above-mentioned circuit board, the second circuit layer includes a plurality of electrical connection pads, and the electrical connection pads are formed on the first conductive post, the diameter of the electrical connection pads is greater than, It is equal to or smaller than the outer diameter of the first conductive column. According to the above structure, the build-up structure includes at least one second dielectric layer, a second circuit layer disposed on the second dielectric layer, and a plurality of layers disposed on the second dielectric layer. Electrically connecting the second conductive pillars of the second circuit layer on the second dielectric layer and the second circuit layer; wherein the second circuit layer comprises a plurality of electrical connection pads, and the electrical connection pads are formed on the second conductive layer a second conductive pillar, the diameter of the electrical connection is greater than, equal to, or smaller than the outer diameter of the second conductive pillar; the plurality of second electrical contact pads are included in the outermost layer of the buildup structure a second circuit layer, and a second solder resist layer is disposed on the layered structure, and a plurality of second solder mask openings are disposed in the second solder resist layer to respectively expose the second electrical contacts pad. The first circuit layer includes a plurality of first electrical contact pads, and the first surface of the first circuit layer and the first dielectric layer is covered with a first solder resist layer, and the first soundproof solder resist layer has a plurality of A solder resist layer is opened to correspondingly expose each of the first electrical contact pads. The present invention further provides a circuit board comprising: a first dielectric layer having a first surface and a surface: wherein the second surface is provided with a plurality of first-day slots; the first circuit layer is embedded in the The first surface of the first dielectric layer is exposed on the first surface of the first dielectric layer; the first number of the first conductive pillars are disposed in the first dielectric layer in the first trenches. And electrically connecting the first circuit layer; and a build-up structure is disposed on the second surface of the first dielectric reed, the 'throove and the first conductive post, and the build-up structure has a shape: 110822 9 1365.024 The second circuit layer in the first line slot, and a portion of the second circuit layer is electrically connected to each of the first conductive columns. 〜 according to the above circuit board, the second circuit layer includes a plurality of electrical connection pads, and the electrical connection system is formed on the first conductive pillar, and the electrical connection is greater than, equal to or Less than the outer diameter of the first __ conductive column. According to the above structure, the first circuit layer includes a plurality of first electrical contact pads, and the first surface layer and the first surface of the first dielectric layer are covered with the second: the first solder resist layer A plurality of first-pre-soldering layers are provided to open the first electrical contact pads. The build-up structure includes at least one second circuit layer having a second number of layers disposed in the second trench of the second dielectric layer: and a plurality of the second dielectric layer and the first layer The second J is connected to the second conductive pillar of the circuit layer of the second circuit layer in the first trench, and the second layer includes the second electrical line (4) of the plurality of electrical dielectric layers, and the electrical connections (4) are correspondingly provided. The second conductive electrical connection pad is greater than, equal to, or smaller than the outermost layer of the structure, and the second electrical contact pad is disposed on the build-up solder layer, and the second anti-additive layer structure is The second method for preventing the second (four)" two (four) phase hole accommodating dew carrier plate is a method for manufacturing the circuit board, which comprises: providing - the first layer formed on the carrier layer has a first - circuit layer; The first line conductive pillar is shaped to have a first dielectric layer on the carrier board, the first circuit layer, and a first dielectric layer; the first portion of the removed portion is 110822 10 1365.024 = low thickness and exposed An end surface of the first conductive pillar; and a buildup structure formed on the first electric layer and the first conductive pillar, the buildup structure having a plurality of layers formed thereon a second circuit layer on the second surface, and the second circuit layer is electrically connected to the first conductive pillar. According to the manufacturing method of the circuit board, the second circuit layer includes a plurality of electrical connection pads, and the electricity The connection pads are formed on the first conductive pad, and the diameter of the electrical connection pad is greater than, equal to, or smaller than the outer diameter of the first conductive pillar.
依上述之製法，該第一線路層及第一導電柱之製法， 係包括：於該承載板上形成有第一導電層；於該第一導電 層上形成有第-阻層，且該第一阻層中形成有第一開口區 以露出部份之第一導電層；於該第一開口區中形成第一 線路層’於該第-阻層及第—線路層上形成第二阻層，且 該第二阻層中形成有第一開孔，以露出第一線路層；曰於該 第-開孔中形成該第一導電柱；α及移除該第二阻層、第 一阻層及其所覆蓋之第一導電層β θAccording to the above method, the first circuit layer and the first conductive pillar are formed by: forming a first conductive layer on the carrier plate; forming a first resist layer on the first conductive layer, and the first a first opening region is formed in a resist layer to expose a portion of the first conductive layer; a first circuit layer is formed in the first opening region to form a second resist layer on the first resist layer and the first circuit layer And forming a first opening in the second resist layer to expose the first circuit layer; forming the first conductive pillar in the first opening; and removing the second resist layer and the first resistor Layer and the first conductive layer β θ covered by it
依上所述，該增層結構係包括有至少一第二介電層 形成於該第二介電層上之第二線路層、以及複數形成於曰該 第二介電層之中並電性連接設於該第二介電層上、下X 第二線路層的第二導電柱；肖第二線路層具有複數電: 連接备’且該些電性連接墊係分別形成於該第二導 上，該電性連接墊之直徑係大於、等於或小於該;二柱 柱之外徑。 又依上所述之製法 復包括移除該承載板， 11 以露出該 110822 130D.U24, 第一介電層之第一表面及第 括複數第-電性接觸墊，於今第二弟一線路層復包 第-表面覆設有第一防焊:第-介電層之 數個第一防焊層開孔，^^弟一防焊層中設有複 數：复包括於該增層結構最外層之第二線路二墊: 性接觸墊’於該增層結構上形成有第二防成有- ==防焊層中形成有複數第二防焊層開； 路出各該第二電性接觸墊。 7應 本發明肢供-種電路板之製法，係包括：提供 ::，於該承载板上形成有第'線路層；於部份： 芦及莖一道士 ^ 等冤柱，於該承載板、第一線路 二2 成具有第-表面及第二表面之第- 一線路層及第-導電柱:^於";表繁面形入成於該承载板、第 第二線槽，且部份之第一線槽對應露出各該 之端面，以及於該第-介電層上形成有增層 :構，該增層結構具有形成於該第一線槽中之第二線路 二且使部份之第二線路層對應電性連接各該第一導電 柱0 依上述之電路板之製法，該第二線路層復包括複數電 '連接墊’且該電性連接墊係形成於該第一導電柱上，該 電性連接塾之直徑係大於、等於或小於該第一導電柱 徑。 1 第一導電柱之製法， 110822 依上述之製法，該第一線路層及 12 該承載板上形成有第-導電層；於該第-導電 有第一阻層，且該第-阻層中形成有第-開口區 以路出部份之第一邕 線路層；於該第^ 開口區中形成第一 該 、ο 阻層及第一線路層上形成第二阻層，且 中形成有第—開孔，以露出部份之第一線路 ρ二、、第開孔中形成第-導電桎；以及移除該第二 廣第一阻層及其所覆蓋之第一導電層。 形成有之製法該第二線路層之部份表面上復包括 法 f電桎，該第二線路層及第二導電柱之製 導電社 於該第一介電層、第一線槽之孔壁、及第一 士之端面上形成有第二導電層；於該第二導電層上 乂成有金屬層，且於該第一 除夫乐綠糟中形成該第二線路層；移 ’、/成於第一線槽中之金屬層，並使兮第-结;Μ # 於第一介雷展少主二. I使孩第一線路層顯露 形成有第曰、，於該第二導電層及第二線路層上 區：露出二:/’Γ該第三阻層中形成㈣ 绫敗® 。刀之第一線路層；於該第二開口區中之第- 蓋之第二導電層，以露出：第移三阻層及其所覆 路出这第一線路層及第二導電柱。 層之第Ί Ϊ二除該承载板’以露出該第-介電 ^ 、路層；該第一線路層復包括複數 叨復叹有第一防焊層，並於該笫一 一防煜第防谇層中設有複數個第 防知層開孔，以對應露出各該第一電性接觸塾。 該增廣結構係包括有至少一具有第二線槽之第二介 110822 13 1365024 電層、設於該第二介電層之第二錄 及複數八·-線槽中之第二線路層、以 H 層中並電性連接該第··線槽中第 -線路層及第：線槽中第二線路層之第二導電柱，又 =面顯露於第二介電層之表面，·該第二線路 .二：第硬導=連接墊，且該些電性連接塾係對應形成 芦之第U ;復包括於該增層結構最外 構上形成有第二防谭層，並於該第：，於該增層結 個苐二防焊層開孔以對 、層h成有複數 本發明之電路板及其製接觸塾。 :成第-導電層及第一阻層，於該第 二形成第-線路層，接著於該第一線路層區 成第一阻層，且該第二阻層中以曝光顯:方^ 複數苐一開孔，藉由皞弁麵必、—先衫方式一次形成有 續可於阻層開孔中形成第一層開孔之孔徑，後 需於介電層中以雷射 乂“佈線密度’且無 產速度，接著再於該第二開开：二能=電路板之生 合強度’接著移除該第二阻岸、：之r線路層之間的結 -導電層，以露出該第一線;層Γ第;及^ 載板、第—線 曰及第一導電柱，再於該承 移除部份之第—;電第二：電^ 後再於該第一介電層;路出該導電柱之端面，最 電杈之知面上形成有第二導電 II0822 14 1365024 ΐίΐΐ阻層’且於該第三阻層之第二開σ區中形成有第 、·一 e ’以電性連接該第—導電柱’再於該第三阻層及 :二?層上形成有第四阻層，且於該第四阻層之第二開 阻展：第二導電柱，俾可藉由曝光顯影以在第二及第四 2:快速形成複數第-及第二開孔’藉由縮小阻層開孔 望一 t於開孔中形成導電柱以提高佈線密度，且提高該 吐^電柱與核心線路層、及第二導電柱與第_線路層之 矣“性，或於該第-介電層之第二表面上形成喪埋於其 面之第二線路層及形成於其中之第二導電柱，以電性連 接第-線路層’藉以縮小整體厚度；1形成該增層結構之 該承載板’以形成無核心板之電路板，俾能縮小整 體厚度，以達薄小之目的。 【實施方式】 、▲以下藉由I特定的具體實施例說明本發明之實施方 式’熟悉此技藝之人士可由本說明#所揭示之内容輕易地 瞭解本發明之其他優點及功效。 [第一實施例] 請參閱第2A至20圖，係顯示本發明之電路板之製法 第一實施例之剖面示意圖。 如第2A圖所示，首先提供一承載板2〇。 如第2B圖所示，於該承載板2〇上形成有第一導電層 21a;接著，於該第一導電層21a上形成有第一阻層22a， 且該第-阻層22a中形成有複數第一開口區咖曰以露出 部份之第一導電層21a。 110822 15 1365.024. 如第2C圖所示，於該第—開口區22〇a 第一線路層23a。 寬鍍形成有 如第2D圖所示，於該第—阻層他及第 上形成第二阻層22b,且該第二限請中形：= 一開孔2識，以露出部份之第-線路層23a。 如第2E圖所示’於該第—開孔22 -導電柱使該第_導電柱24a電性連== 層23a。 伐通弟一線路According to the above, the build-up structure includes a second circuit layer having at least one second dielectric layer formed on the second dielectric layer, and a plurality of second dielectric layers formed in the second dielectric layer and electrically Connecting a second conductive pillar disposed on the second dielectric layer and the lower X second wiring layer; the second second wiring layer has a plurality of electrical connections: and the electrical connection pads are respectively formed on the second conductive pillar The diameter of the electrical connection pad is greater than, equal to, or less than the outer diameter of the two pillars. According to the above-mentioned manufacturing method, the carrier board is removed, 11 to expose the 110822 130D.U24, the first surface of the first dielectric layer and the second plurality of first-electric contact pads, and the second younger line The first surface of the layer is covered with a first solder mask: a plurality of first solder mask openings of the first dielectric layer, and a plurality of first solder mask layers are provided in the solder mask layer: the complex layer is included in the buildup layer The second line of the outer layer is two pads: the contact pad 'is formed on the layered structure with a second anti-welding layer. - == a plurality of second solder mask layers are formed in the solder resist layer; Contact pad. 7 The method for manufacturing a circuit board of the present invention includes: providing: a 'circuit layer formed on the carrier plate; and a portion: a reed and a stem, and the like, on the carrier plate. a first circuit 20% having a first-surface layer and a second-surface layer and a first-conducting column: the surface of the first line is formed in the carrier board and the second line slot, and a portion of the first wire groove correspondingly exposing each of the end faces, and forming a build-up layer on the first dielectric layer, the build-up structure having a second line 2 formed in the first wire groove and a portion of the second circuit layer is electrically connected to each of the first conductive pillars. According to the method of manufacturing the circuit board, the second circuit layer includes a plurality of electrical connection pads, and the electrical connection pads are formed on the first circuit layer. On a conductive post, the diameter of the electrical connection is greater than, equal to, or less than the diameter of the first conductive pillar. 1 The method of manufacturing the first conductive pillar, 110822, according to the above method, the first circuit layer and 12 the carrier plate is formed with a first conductive layer; the first conductive layer has a first resistive layer, and the first resistive layer Forming a first germanium circuit layer having a first opening region to form an exit portion; forming a first resist layer and a first resistive layer on the first opening layer and the first wiring layer in the first opening region, and forming a second - opening the hole to expose a portion of the first line ρ2, forming a first conductive ridge in the first opening; and removing the second wide first resist layer and the first conductive layer covered thereby. Forming a part of the surface of the second circuit layer further comprises a method, wherein the second circuit layer and the second conductive column are electrically conductive to the first dielectric layer and the first trench And forming a second conductive layer on the end surface of the first conductor; forming a metal layer on the second conductive layer, and forming the second circuit layer in the first Schnauzer green stalk; moving ', / a metal layer formed in the first wire slot, and the first layer is formed by the first layer of the first layer of the first layer. The first layer of the layer is exposed to form a third layer, and the second layer is formed. And the upper layer of the second circuit layer: exposed two: / 'Γ formed in the third resistive layer (4) 绫 ® ® . a first circuit layer of the knives; a second conductive layer of the first cover in the second opening region to expose: the first three-resist layer and the first circuit layer and the second conductive column are covered. The second layer of the layer is divided by the carrier plate to expose the first dielectric layer and the road layer; the first circuit layer includes a plurality of ruins, a first solder mask layer, and the first solder mask layer The plurality of anti-knowledge layers are provided in the anti-mite layer to respectively expose the first electrical contact ports. The augmented structure includes at least one second dielectric layer 110822 13 1365024 having a second trench, and a second circuit layer disposed in the second recording and the complex eight-channel of the second dielectric layer And electrically connecting the first conductive layer in the first circuit layer and the second circuit layer in the first wire slot in the H layer, and the surface is exposed on the surface of the second dielectric layer, The second line. The second: the first hard guide = the connection pad, and the electrical connections are corresponding to the U of the reed; the second outer layer is formed on the outermost structure of the buildup structure, and The first: a plurality of solder mask layers are formed in the build-up layer to form a plurality of circuit boards of the present invention and the contact pads thereof. Forming a first conductive layer and a first resistive layer, forming a first circuit layer in the second layer, and then forming a first resistive layer in the first circuit layer region, and exposing the second resistive layer to a plurality of layers After opening the hole, the aperture of the first layer can be formed in the opening of the resist layer by means of the first surface of the mask, and then the aperture of the first layer is formed in the dielectric layer. 'and the rate of no production, and then the second opening: two can = the strength of the circuit board' then remove the junction-conducting layer between the second barrier, the r circuit layer to expose the first a line; a layer of the first layer; and a carrier plate, a first line and a first conductive column, and then the first part of the removed portion; the second: the second and the second dielectric layer; An end surface of the conductive pillar is formed, and a second conductive II0822 14 1365024 ΐ ΐΐ ΐΐ ΐΐ layer is formed on the most electric 知 surface, and a first, a ′′ is formed in the second open σ region of the third resist layer Electrically connecting the first conductive pillar to form a fourth resistive layer on the third resistive layer and the second layer, and forming a second resistive layer on the fourth resistive layer: the second conductive pillar borrow Exposing and developing to form a plurality of first and second openings in the second and fourth portions 2: forming a conductive pillar in the opening by narrowing the opening of the resist layer to increase the wiring density, and increasing the wiring And forming a second circuit layer buried in the surface of the core circuit layer, and the second conductive pillar and the _ wiring layer, or forming a second circuit layer buried on the second surface of the first dielectric layer Two conductive pillars are electrically connected to the first circuit layer 'to reduce the overall thickness; 1 to form the carrier plate of the build-up structure to form a circuit board without core plates, and the overall thickness can be reduced to achieve a small thickness . [Embodiment] ▲ Embodiments of the present invention will be described below with reference to specific embodiments of the present invention. Those skilled in the art can readily appreciate other advantages and effects of the present invention from the disclosure of the present invention. [First Embodiment] Referring to Figs. 2A to 20, there are shown cross-sectional views showing a first embodiment of a method of manufacturing a circuit board of the present invention. As shown in Fig. 2A, a carrier board 2 is first provided. As shown in FIG. 2B, a first conductive layer 21a is formed on the carrier plate 2? Next, a first resist layer 22a is formed on the first conductive layer 21a, and the first resist layer 22a is formed therein. A plurality of first open areas are displayed to expose a portion of the first conductive layer 21a. 110822 15 1365.024. As shown in Fig. 2C, the first circuit layer 23a is in the first opening region 22a. The wide plating is formed as shown in FIG. 2D, and the second resist layer 22b is formed on the first resist layer and the upper portion, and the second limit is medium-shaped: = an opening 2 is recognized to expose the first portion - Circuit layer 23a. As shown in Fig. 2E, the conductive pillars of the first opening 22 are electrically connected to the first conductive pillar 24a == layer 23a. Cutting a line
如弟2F圖所示，移除該第二阻層^ 及其所覆蓋之第一導雷爲91 、+ 丨且層22c θ la，以路出該第一線路芦2*^ 及第一導電柱24a。 層23c 第一 如第2G圖所示，於該承載板2〇、第一線路層 導電柱24a上形成有第—介電層心。 如第2H圖所示，移除部份之第一介電層―，以降 低其厚度並露出該第一導電柱24a之端面，使該第一介電 曰5a八有第一表面25a’形成於該承載板2〇上，並形成 相對之第二表面25a，，。 如第21圖所示，於該第一介電㉟—之第二表面 5=及第導電柱24a之端面上形成有第二導電層灿； 接著於該第一導電層21b上形成有第三阻層Me，且於 該第三阻層22c中形成有複數第二開口區220。，以露出 部份之第二導電層21b，且該第二開口區22〇c並顯露該 第一導電桎24a之端面上的第二導電層21b。 如第2J圖所示，於該第二開口區22〇c中電鍍形成第 16 110822 1365.024 . 二線路層23b’該第二線路層23b具有複數電性連接墊 231，且該些電性連接墊231係分別形成於該第一導電柱 24a上，又該電性連接墊231之直徑係大於、等於或 該苐一導電枉24a之外徑。 ； 如第2K圖所示’於該第二線路層2补及第三阻層zb 上形成有第四阻層22d，且該第四阻層22d中形成有曰第二 開孔220d，以露出電性連接墊231。 如第2L圖所示，於該第二開孔㈣中電鑛形成 =電柱灿，使該第二導電柱24b電性連接該第二線路 如第2M圖所示 及其所覆蓋之第二導 及第二線路層23b。 移除該第四阻層22d、第三阻層22c 電層21b，以露出該第二導電柱2扑 如第2N圖所示，之後重覆第 -介電層25a之第一…R ⑽圖，以於該第 弟一表面25a”上形成有增層結構， 增層結構26係包括有至少一第 構26,該 第二介靜❿u 第—；m5b、形成於該 兮第一人; 之第二線路層23b，、以及複數形成於 1 一：電層之中並電性連接該第二介電 面 之弟二線路層23b，23b，的第二:面 層23b復包括硬數電性連接塾231，，且該些電 231，係對應形成於各該第 連接墊 整如，之直徑係大於、等^電柱撕上，又該電性連接 外徑。 ^ 4於或小於該第二導電柱24b，之 如第 20圖所示，移除該承載板2〇, 以露出該第一線 110822 17 1365.024 路層23a及第一介電層25之第_ 禾表面25a ’且該第一 線路層23a復包括複數第一電性 仏 电改接觸墊232a，於該第一 線路層23a及第一介電層25a之笛 ± 曆之第一表面25a，覆設有第 一防焊層27a，並於該第一 —a P方焊層27a中設有複數個第一 防4層開孔270a，以對岸霪屮夂 9Q0 耵應路出各該第一電性接觸墊 又該增層結構26最外層之第二線路層挪,形成有 複數第-電性接觸塾264,於該增層結構％上形成有第 -防焊層27b，並於該第二防焊層饥中形成有複數個第 -防焊層開孔襲以對應露出各該第二f性接觸㈣心 本發明復提供-種電路板，係包括：第一介電層 25a’係具有第一表面25a’及第二表面25&，，;帛一線路層 23a，係設於該第一介電層25a之第一表面，中且^ 路於該第一介電層25a之第一表面25a，；複數第一導電 柱24a ’係設於該第一介電層25a中，.並電性連接該第一 線路層23a，且該第-導電柱24a之端面顯露於第一介電 層25a之第二表面25a”；以及增層結構％，係設於該第 一介電層25a之第二表面25a，，上，該增層結構％具有複 數形成於該第一介電層25a之第二表面25a，，上之第二線 路層23b，且該第二線路層23b電性連接至該第一導電柱 24a。 依上述之電路板，該第二線路層23b復包括複數電性 連接墊231，且該電性連接墊231係形成於該第一導電柱 24a上’該電性連接墊231之直徑係大於、等於或小於該 第一導電柱24a之外徑。 110822 18 1365024. 又依上述之結構，該增層結構26係包括有至少一第 二介電層25b、設於該第二介電層现上之第二線路層 23b’、以及複數設於該第二介電層25b之中並電性連接^ 第二介電層25b上 '下面之第二線路層挪篇，的第: 導電柱24b’’該第二線路層咖，復包括複數電性連接塾 231’’且該電㈣接墊231，細彡成於該第二導電柱⑽， t.’該電性連㈣231，之直彳㈣大於、等於或小於該第 -導電柱24b’之外徑；復包括複數第二電性 咖，係設於該增層結構26最外層之第二線路層咖，塾 並於該增層結構26上覆設有第二防焊層27b’於該第二 =焊層27b中設有複數個第二防焊層開孔27〇b，輯： 露出各該第二電性接觸墊264。 〜 依上所述，該第一線路層仏復包括複數第一電性接 觸塾232a，於該第—線路層咖及第一介電層❿之第 覆設有第一防焊層仏，該第一防焊層 有複數第1焊層開孔27Ga，以制露出 接觸墊232a。 ^ ^ [第二實施例] 第二I::第至3;圖’係顯示本發明之電路板之製法 第一及二’面不意圖’與前-實施例之不同處在於該 : = 係分別形成於該第-介電層中，且使該 第^線路層表面分別顯露於第一介電層之表面。 兮笛人/圖所7，提供—係如第2G圖所示之結構，於 該第一"電層25a t形成有複數第—線槽如，且該第 19 110822 丄 . 一線槽2518中露出該第-導電柱24a之端面。 如第3B圖所示，你分结 ,^ 咕' 於該第一 ”電層25a、第一線槽251a =土、及一導電柱24a之端面上形成有第二導電層 21b。 如第3C圖所示，於 _ 金屬層23,且於㈣…第一導電層训上電鍵形成有 « " …"苐—線槽251a中電鍍形成有第二線路 層23\以電性連接該第一導電柱24a。 么嵐Π3Ι)圖所7^’移除未形成於該第-線槽25ia中之 23b顯露於該第—介路f 23b’使該第二線路層 電層25a之表面，且該第二線路層23b 電性連接塾231係形成 於、等於或小於該第a_上導電該柱m如之直經係大 如第3£圖所示，於兮 一 m上形成有第三阻層22c第= 21b及第二線路層 有複數第二開w22()e,tt 1該第三阻層版中形成 如第㈣所示二㈡部份之第二線路層咖。 層⑽上電鍍形成有第二導電柱24b。 線路 第-示：移除該第三阻層22c及其所覆蓋之 24b層21b’以露出該第二線路層⑽及第二導電柱 如第3H圖所示，於兮笛人‘ 23b、及第二導電枝⑽^第—介電層25a、第二線路層 & ¥電枝24b上形成有第二介電層25卜 圖所示，之後得重覆第3A至3H圖之製裎， 110 1365024 以於該第介電層25a之第二表面25a”上形成有增層結 構26 ’該增層結構26係包括至少一具有複數第二線槽 251b之第一介電層25b、設於該第二介電層2肋之第二 線槽251b中之第二線路層咖，、以及複數設於該第二介 •電層25b中並電性連接該第一線槽25ia中第二線路層 23b之第—導電柱24b及第二線槽25ib，中第二線路層 23b’之第二導電柱24b,’又該第二線路層訓之表面顯露 於該第二介電層现之表面；該第二線路層23b，23b，復 _包括複數電性連接墊231，231’，且該些電性連接墊231 係分別形成於該第-導電柱24a上，又該電性連接塾231 之直徑係大於、等於或小於該第一導電柱24a之外徑，而 該電性連接墊231，係分別形成於該第二導電柱24b，24b， 上，又該電性連接墊231，之直徑係大於、等於或小於該 第一；導電柱24b，24b’之外徑.。 如第3J圖所示，移除該承載板2〇，以露出該第一線 ⑩路層23a及第一介電層25a之第一表面25a，，且該第一 線路層23a復包括複數第一電性接觸墊232a，於該第一 線路層23a及第-介電層25a之第-表面25a，覆設有第 一防焊層27a，並於該第一防焊層27a中設有複數個第一 .防焊層開孔270a，以對應露出各該第一電性接觸墊 • 232a;又該增層結構26最外層之第二線路層2北，上形成 有複數第二電性接觸墊264，於該增層結構上形成有 第二防焊層27b’並於該第二防焊層27b中形成有複數個 第二防焊層開孔270b以對應露出各該第二電性接觸墊 110822 21 !365〇24 264。 本發明復提供一種電路板，係包括：第_介電層 25a ’係具有第一表面25a’及第二表面25a，，，於該第_表 面25a”設有複數第一線槽251a;第一線路層23a，係嗖 於該第一介電層25a之第一表面25a，中，且顯露於該& 一介電層25a之第一表面25a，；複數第一導電柱24^係 設於該些第一線槽251a内之第一介電層25a中，並電性 連接該第一線路層23a;以及增層結構26,係設於該第一 介電層25a之第二表面25a”上，且該增層結構26具有形 成於該第一線槽251a中並顯露於第二表面25a，，之第二線 路層23b，且使部份之第二線路層23b對應電性連接各該 第一導電柱24a。 ~ 依上述之電路板’該第二線路層23b復包括複數電性 連接墊231 ’且該電性連接墊231係形成於該第一導電柱 24a上，該電性連接墊231之直徑係大於等於或小於該 第一導電柱24a之外徑。 依上述之結構’該第一線路層23a復包括複數第一電 性接觸墊232a，於該第—線路層23a及第一介電層 之第一表面25a’覆設有第—防焊層27a，並於該第一防焊 層27a中設有複數個第—防焊層開孔27〇a，以對應露出 各該第一電性接觸墊232a。 該增層結構26係包括有至少一具有第二線槽25lb， 之第二介電層25b、設於該第二介電；| 25b之第二線槽 251b中之第一線路層23b，、以及複數設於該第二介電層 22 110822 1365024 . ⑽中並電性連接該第一線槽咖中第二線路層咖之 第-導電柱24b及第二線槽251b,中第二線路層咖，之 -導電纟24b，又該第二線路層2扑，之表面顯露於第二 .介電層25b之表面；其中，該第二線路層撕復包括複數 231’，且該些電性連接墊231，係對應設於各 =第-導電柱24b，上，該電性連接墊231，係大於、“ 二導電柱灿，；復包括複數第二電性接觸墊 層結構26最外層之第二線路層_， 層27bH6上並設有第二防焊I 27卜該第二防焊 f 27b具有硬數個第二防焊層開孔 第二電性接觸塾264。 謂應路出各該 本發明之電路板及其製承 形成第-導電層及第—阻芦，…板之表面上先 甲形成第-線靜，接菩該第一阻層之第-開口區 成第二阻層，且該曰第p者於該第一線路層及第一阻層上形 複數第-開孔，ΐΐ: 以曝光顯影方式一次形成有 續可於阻層開孔顯影以縮小阻層開孔之孔徑’後 需於介電層中以+射制^一導電柱以提高佈線密度’且無 產速度，接著再於:二= 二而能提高電路板之生 該第-導電柱以提高；二生連接成第一導電柱，以藉由 度，接著移除該第二_、思 連接之線路之間的結合強 電層，以露出孩第Ί 0、第一阻層及其所覆蓋之第一導 板、第'線路層；第及第-導電柱’再於該承載 除部份之第—介 電柱上㈣第-介電層；之後移 曰以路出該第一導電柱之端面，最後 11082 I365U24 . 再於該第一介電層及導電柱 / 及第三阻層，且於該 上形成有第二導電層 線路層’以電性連接該第一;:口區中形成有第二 .二線路層上形成有第四阻層，且二：於該第三阻層及第 t形成第二導電柱 '^第四阻層之第二開孔 子电往’俾可精由曝光顧# 層中快速形成複數第一及第孔=在弟二及弟四阻 孔徑，於開孔中形成導藉由縮小阻層開孔之 ^ . 等電柱^提向佈線密度，且描离亏坌 -導電柱與核心線路層、及第 ：，該第 合性；或於該第-介電層之第二導^與弟—線路層之結 τ- ^ 第一表面上形成後埋於JL矣 之第二線路層及形成於其 …、 第一蝮Μ π 又弟一蛤電柱，以電性連接 f線路層，藉以縮小整體厚度；且形成 移除該承載板，以形成無核：：-構之後 厚度，以達薄小之目的。板俾能縮小整體 ★上述實施例係用以例示性說明本發明之原理及其功 政，而非用於限制本發明。任何熟習此項技藝之人士均可 在不違背本發明之精神及料下，對上述實施例進行修 改。因此本發明之權利保護範圍，應如後述之申請專利範 圍所列。 【圖式簡單説明】 第1A至1G圖係為習知電路板及其製法之剖視示竟 圍， 第2A至20圖係為本發明電路板及其製法之第一實施 例剖視圖；以及 ' 第3A至3 J圖係為本發明電路板及其製法之第二實施 110822 24 1365024 . 例剖視圖。 【主要元件符號說明】 10 核心板 101 核心線路層 102 導電通孔 10a 表面 120a 介電層開孔 12a 、 25a 第一介電層 12b 、 25b 第二介電層 13 導電層 14 阻層 140 開口區 151a 第一導電盲孔 151b 第二導電盲孔 15a 、 23a 第一線路層 15b 、 23b 、23b’ 第二線路層 16、26 增層結構 164 電性接觸墊 17 防焊層 170 防焊層開孔 20 承載板 21a 第一導電層 21b 第二導電層 220a 第一開口區 25 110822 1365024 220b 第 220c 第 220d 第 22a 第 22b 第 22c .第 22d 第 23 金 231、 231， 電 232a 第 24a 第 24b、 24b， 第 251a 第 251b， 第 25a， 第 25a” 第 264 第 270a 第 270b 第 27a 第 27b 第As shown in FIG. 2F, the second resistive layer ^ and the first guided lightning covered by the second resistive layer ^ are 91, + 丨 and the layer 22c θ la is taken to exit the first line reed 2*^ and the first conductive Column 24a. Layer 23c First As shown in Fig. 2G, a first dielectric layer core is formed on the carrier board 2'' and the first wiring layer conductive pillar 24a. As shown in FIG. 2H, a portion of the first dielectric layer is removed to reduce the thickness thereof and expose the end surface of the first conductive pillar 24a, so that the first dielectric layer 5a has a first surface 25a' formed. On the carrier plate 2, and forming an opposite second surface 25a, . As shown in FIG. 21, a second conductive layer is formed on the second surface 5 of the first dielectric 35 and the end surface of the conductive pillar 24a; and then a third surface is formed on the first conductive layer 21b. The resist layer Me has a plurality of second opening regions 220 formed in the third resist layer 22c. And exposing a portion of the second conductive layer 21b, and the second opening region 22〇c and exposing the second conductive layer 21b on the end surface of the first conductive bump 24a. As shown in FIG. 2J, the 16th 110822 1365.024 is formed in the second open region 22〇c. The second circuit layer 23b has a plurality of electrical connection pads 231, and the electrical connection pads are The 231 is formed on the first conductive pillar 24a, and the diameter of the electrical connection pad 231 is greater than, equal to or equal to the outer diameter of the first conductive bump 24a. As shown in FIG. 2K, a fourth resist layer 22d is formed on the second circuit layer 2 and the third resist layer zb, and a second opening 220d is formed in the fourth resist layer 22d to expose Electrical connection pad 231. As shown in FIG. 2L, in the second opening (4), the electric ore is formed to be electrically connected, and the second conductive post 24b is electrically connected to the second line, as shown in FIG. 2M and the second guide covered thereby. And the second circuit layer 23b. Removing the fourth resistive layer 22d and the third resistive layer 22c from the electrical layer 21b to expose the second conductive pillar 2 as shown in FIG. 2N, and then repeating the first...R (10) diagram of the first dielectric layer 25a. a layered structure is formed on the first surface 25a" of the first younger brother, and the buildup structure 26 includes at least one first structure 26, the second dielectric layer 第u-;m5b is formed in the first person; The second circuit layer 23b, and the second plurality of surface layers 23b, 23b formed in the electrical layer and electrically connected to the second dielectric layer 23b, 23b, include a plurality of electrical layers. The connection 塾231, and the electricity 231 is formed correspondingly to each of the first connection pads, the diameter is greater than, the electric column is torn, and the electrical connection is external. ^4 is less than or less than the second The conductive post 24b, as shown in FIG. 20, removes the carrier plate 2〇 to expose the first line 110822 17 1365.024 layer 23a and the first dielectric layer 25 of the first dielectric layer 25a' and the first The circuit layer 23a includes a plurality of first electrical 仏 electrically modified contact pads 232a, and is disposed on the first surface 25a of the first circuit layer 23a and the first dielectric layer 25a. There is a first solder resist layer 27a, and a plurality of first anti-four-layer openings 270a are disposed in the first-a P-square solder layer 27a, and the first electrical property is discharged by the opposite bank 9Q0. The contact pad and the second circuit layer of the outermost layer of the build-up structure 26 are formed, and a plurality of first-electrode contact pads 264 are formed, and a first solder resist layer 27b is formed on the build-up structure %, and the second anti-solder layer A plurality of first-solderproof layer openings are formed in the solder layer hunger to correspondingly expose the second f-contacts (four). The present invention provides a circuit board comprising: the first dielectric layer 25a' has a first a surface 25a' and a second surface 25&,; a line layer 23a is disposed on the first surface of the first dielectric layer 25a, and is disposed on the first surface of the first dielectric layer 25a 25a, a plurality of first conductive pillars 24a' are disposed in the first dielectric layer 25a, electrically connected to the first wiring layer 23a, and an end surface of the first conductive pillar 24a is exposed on the first dielectric layer a second surface 25a" of 25a; and a build-up structure % is disposed on the second surface 25a of the first dielectric layer 25a, and the build-up structure % has a plurality of The second line of the second surface layer 25a of the dielectric layer 25a ,, 23b, 23b and the second wiring layer electrically connected to the first conductive pillar 24a. According to the circuit board, the second circuit layer 23b includes a plurality of electrical connection pads 231, and the electrical connection pads 231 are formed on the first conductive pillars 24a. The diameter of the electrical connection pads 231 is greater than It is equal to or smaller than the outer diameter of the first conductive post 24a. 110822 18 1365024. According to the above structure, the build-up structure 26 includes at least one second dielectric layer 25b, a second circuit layer 23b' disposed on the second dielectric layer, and a plurality of The second dielectric layer 25b is electrically connected to the second dielectric layer 25b on the second dielectric layer 25b. The second conductive layer 24b'' the second circuit layer includes a plurality of electrical properties. Connecting the 塾 231 ′′ and the electric (four) pad 231 is finely formed on the second conductive pillar (10), t. 'the electrical connection (four) 231, the straight 彳 (four) is greater than, equal to or less than the first conductive pillar 24b ′ The second outer layer of the second layer of the layered structure 26 is disposed on the second layer of the layered structure 26, and the second solder resist layer 27b is disposed on the layered structure 26 The second = solder layer 27b is provided with a plurality of second solder mask openings 27 〇 b, and each of the second electrical contact pads 264 is exposed. According to the above, the first circuit layer further includes a plurality of first electrical contact pads 232a, and the first solder mask layer is disposed on the first circuit layer and the first dielectric layer The first solder resist layer has a plurality of first solder layer openings 27Ga to expose the contact pads 232a. ^^ [Second Embodiment] The second I:: the third to the third; the figure shows that the first and second aspects of the circuit board of the present invention are different from the previous embodiment in that: Formed in the first dielectric layer, respectively, and the surface of the second circuit layer is exposed on the surface of the first dielectric layer. The whistle/map 7, provided, is a structure as shown in Fig. 2G, in which the first "electric layer 25a t is formed with a plurality of first-line grooves, and the 19th 110822 一. a line groove 2518 The end surface of the first conductive pillar 24a is exposed. As shown in FIG. 3B, you divide, and form a second conductive layer 21b on the end faces of the first "electric layer 25a, the first trench 251a = soil, and a conductive pillar 24a. As shown in the figure, in the _ metal layer 23, and in the (four) ... first conductive layer training, the key is formed with « "..." 苐-line groove 251a is electroplated to form a second circuit layer 23\ electrically connected to the first a conductive post 24a is removed from the first-line groove 25ia and is exposed on the surface of the second circuit layer 25a. And the second circuit layer 23b is electrically connected to the second layer 23, and is formed at a level equal to or less than the first a-high conductivity. The column m is as large as the third line, and is formed on the first m. The third resist layer 22c is at the 21st and the second circuit layer has a plurality of second openings w22()e, tt1, and the second resist layer forms a second circuit layer of the second (2) portion as shown in the fourth (4) layer. The second conductive pillar 24b is formed by electroplating. The circuit is shown as follows: the third resistive layer 22c and the 24b layer 21b' covered by the third resistive layer 22c are removed to expose the second wiring layer (10) and the second conductive pillar as shown in FIG. 3H. Show, Yu Yu The second dielectric layer 25 is formed on the whistle '23b, and the second conductive branch (10), the first dielectric layer 25a, the second circuit layer, and the second electric layer 24b, and then the third layer is repeated. 3H, 110 1365024, a second layer 25a" of the dielectric layer 25a is formed with a build-up structure 26'. The build-up structure 26 includes at least one first dielectric having a plurality of second trenches 251b. An electrical layer 25b, a second circuit layer disposed in the second trench 251b of the second dielectric layer 2, and a plurality of electrodes disposed in the second dielectric layer 25b and electrically connected to the first line The second conductive pillar 24b of the second circuit layer 23b in the slot 25ia, the second conductive pillar 24b of the second circuit layer 23b', and the surface of the second circuit layer are exposed to the second a surface of the dielectric layer; the second circuit layer 23b, 23b, the complex includes a plurality of electrical connection pads 231, 231', and the electrical connection pads 231 are respectively formed on the first conductive pillar 24a, The diameter of the electrical connection port 231 is greater than, equal to, or smaller than the outer diameter of the first conductive post 24a, and the electrical connection pads 231 are respectively formed in the second The conductive posts 24b, 24b, and the electrical connection pads 231 have diameters greater than, equal to, or less than the first; outer diameters of the conductive posts 24b, 24b'. As shown in FIG. 3J, the carrier board 2 is removed to expose the first line 10 layer 23a and the first surface 25a of the first dielectric layer 25a, and the first line layer 23a includes a plurality of An electrical contact pad 232a is disposed on the first surface layer 23a and the first surface 25a of the first dielectric layer 25a, and is provided with a first solder resist layer 27a, and a plurality of first solder resist layers 27a are disposed in the first solder resist layer 27a. First, the solder resist layer opening 270a correspondingly exposes each of the first electrical contact pads 232a; and the second circuit layer 2 of the outermost layer of the buildup structure 26 is formed with a plurality of second electrical contacts thereon. a pad 264, a second solder resist layer 27b' is formed on the layered structure, and a plurality of second solder mask opening 270b are formed in the second solder resist layer 27b to correspondingly expose the second electrical contacts. Pad 110822 21 !365〇24 264. The present invention further provides a circuit board comprising: a first dielectric layer 25a' having a first surface 25a' and a second surface 25a, wherein the first surface 25a" is provided with a plurality of first wire grooves 251a; a circuit layer 23a is disposed on the first surface 25a of the first dielectric layer 25a, and is exposed on the first surface 25a of the dielectric layer 25a; and the plurality of first conductive pillars 24 The first dielectric layer 25a in the first trench 251a is electrically connected to the first wiring layer 23a; and the build-up structure 26 is disposed on the second surface 25a of the first dielectric layer 25a. And the build-up structure 26 has a second circuit layer 23b formed in the first wire groove 251a and exposed on the second surface 25a, and a portion of the second circuit layer 23b is electrically connected to each other. The first conductive pillar 24a. The second circuit layer 23b includes a plurality of electrical connection pads 231', and the electrical connection pads 231 are formed on the first conductive pillars 24a. The diameter of the electrical connection pads 231 is greater than It is equal to or smaller than the outer diameter of the first conductive post 24a. According to the above structure, the first circuit layer 23a includes a plurality of first electrical contact pads 232a, and the first surface 25a of the first circuit layer 23a and the first dielectric layer is covered with a first solder mask 27a. And a plurality of first solder mask openings 27a are formed in the first solder resist layer 27a to correspondingly expose the first electrical contact pads 232a. The build-up structure 26 includes at least one second dielectric layer 25b having a second trench 25b, a first wiring layer 23b disposed in the second trench 251b of the second dielectric; | 25b, And a plurality of the second dielectric layer 22 110822 1365024 (10) and electrically connected to the first conductive pillar 24b and the second trunking 251b of the second wiring layer of the first trunking, the second circuit layer a surface of the second dielectric layer 25b, the surface of which is exposed on the surface of the second dielectric layer 25b; wherein the second circuit layer tearing comprises a plurality 231', and the electrical properties The connection pad 231 is correspondingly disposed on each of the first conductive pillars 24b, and the electrical connection pads 231 are larger than "two conductive pillars"; and the outermost layer of the plurality of second electrical contact pad structures 26 is included. The second circuit layer _, the layer 27bH6 is provided with a second solder resist I 27. The second solder resist f 27b has a plurality of second solder mask opening and a second electrical contact 塾 264. The circuit board of the present invention and the system thereof form a first conductive layer and a first resistive layer, and the surface of the first resistive layer forms a first-line static, and the first resistive layer is connected The first opening region is formed as a second resist layer, and the first surface of the first circuit layer and the first resist layer is formed by a plurality of first-opening holes, and the first opening is formed by exposure and development. The hole is developed to reduce the aperture of the resistive opening, and then the + conductive pillar is required to be printed in the dielectric layer to increase the wiring density', and the speed is not produced. Then, the second board can improve the life of the board. The first conductive pillar is raised; the second conductive joint is connected to the first conductive pillar to remove the combined strong electric layer between the second and the connected connecting lines, thereby exposing the child first zero, the first resistance The layer and the first guide plate, the 'the circuit layer; the first and the first conductive column' are disposed on the first dielectric layer of the carrier-substrate (4), and then moved to the road An end surface of the first conductive pillar, and finally a first dielectric layer and a conductive pillar and a third resistive layer, and a second conductive layer wiring layer is formed thereon to electrically connect the first; a second resist layer is formed on the second and second circuit layers in the mouth region, and two: a second conductive pillar is formed on the third resistive layer and the second conductive pillar '^The fourth open hole of the fourth resistive layer is turned to the '俾可精精的光# layer to quickly form the first number and the first hole = the second and the fourth four apertures in the dipole, forming a guide in the opening to reduce The barrier layer is opened. The isoelectric column raises the wiring density, and traces the deficit-conducting pillar and the core wiring layer, and the first: or the second conductivity of the first dielectric layer. And the younger brother-the junction of the circuit layer τ- ^ is formed on the first surface and buried in the second circuit layer of JL矣 and formed in the ..., the first 蝮Μ π and the other one is electrically connected to the f-line layer, Thereby, the overall thickness is reduced; and the carrier plate is removed to form a coreless::--thickness to achieve a thinness. The slabs can be reduced in size. The above embodiments are intended to illustrate the principles of the present invention and its operations, and are not intended to limit the present invention. Any of the above-described embodiments can be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A to 1G are cross-sectional views showing a conventional circuit board and a method for manufacturing the same, and FIGS. 2A to 20 are cross-sectional views showing a first embodiment of the circuit board and the method of manufacturing the same according to the present invention; 3A to 3J are second embodiment of the circuit board of the present invention and its manufacturing method 110822 24 1365024. [Main component symbol description] 10 core board 101 core circuit layer 102 conductive via 10a surface 120a dielectric layer opening 12a, 25a first dielectric layer 12b, 25b second dielectric layer 13 conductive layer 14 resist layer 140 open area 151a first conductive blind hole 151b second conductive blind hole 15a, 23a first circuit layer 15b, 23b, 23b' second circuit layer 16, 26 build-up structure 164 electrical contact pad 17 solder resist layer 170 solder mask opening 20 carrier plate 21a first conductive layer 21b second conductive layer 220a first open region 25 110822 1365024 220b 220c 220d 22a 22b 22c. 22d 23rd gold 231, 231, electricity 232a 24a 24b, 24b , 251a, 251b, 25a, 25a", 264, 270a, 270b, 27a, 27b
一開孔 二開口區 二開孔 一阻層 二阻層 三阻層 四阻層 屬層 性連接墊 一電性接觸墊 一導電柱 二導電柱 一線槽 二線槽 一表面 二表面 二電性接觸墊 一防焊層開孔 二防焊層開孔 一防焊層 二防焊層 26 110822One opening, two opening areas, two openings, one resistance layer, two resistance layers, three resistance layers, four resistance layers, layered connection pads, one electrical contact pad, one conductive column, two conductive columns, one wire slot, two wire slots, one surface, two surfaces, two electrical contacts. Pad one solder mask opening two solder mask opening one solder mask two solder mask 26 110822