TWI552657B - Interposer substrate and method of fabricating the same - Google Patents

Description

Intermediary substrate and its preparation method

The invention relates to an interposer substrate, in particular to an interposer substrate for a package stack structure and a method for fabricating the same.

With the evolution of semiconductor packaging technology, semiconductor devices have developed different package types, and in order to improve electrical functions and save packaging space, a plurality of package structures are stacked to form a package on package (Package on Package, PoP), this kind of package can use the heterogeneous integration feature of System in Package (SiP), which can use different electronic components, such as memory, CPU, graphics processor, image application processor, etc. The integration of the system through the stack design is suitable for a variety of thin and light electronic products.

In the early package stack structure, a memory package (commonly known as a memory IC) is stacked on a logic package (commonly known as a logic IC) by a plurality of solder balls, and as electronic products become thinner, lighter, and more functionally advanced, The wiring density of memory packages is getting higher and higher, in nanometers, so the spacing between the contacts is smaller; however, the pitch of the logic packages is in micrometers, which cannot be effectively reduced to the corresponding Memory package The spacing results in a memory package with a high line density, but there is no logical package that can be matched, so that the electronic product cannot be efficiently produced.

Therefore, in order to overcome the above problem, an interposer substrate is added between the memory package and the logic package. For example, the logic package of the logic chip with a large electrical connection between the bottom end of the interposer substrate is provided. The upper end of the interposer substrate electrically couples the memory package with the memory chip with a small pitch.

FIG. 1 is a schematic cross-sectional view of a conventional interposer substrate 1. As shown in FIG. 1 , the interposer 1 includes a first insulating layer 13 , a first wiring layer 11 , a plurality of first conductive pillars 12 , a second wiring layer 14 , and a plurality of second conductive pillars 15 . The second insulating layer 16 and the surface treatment layer 17, 17'. The first insulating layer 13 has opposite first and second surfaces 13a, 13b. The first circuit layer 11 is embedded in the first insulating layer 13 and exposes the first surface 13a, and is used as a pad. The first conductive pillar 12 is disposed in the first insulating layer 13 and disposed on the first circuit layer 11 . The second circuit layer 14 is disposed on the second surface 13b of the first insulating layer 13 and the first conductive pillars 12. The second conductive pillar 15 is disposed on the second circuit layer 14. The second insulating layer 16 is disposed on the second surface 13b of the first insulating layer 13 and covers the second circuit layer 14 and the second conductive pillar 15 , and exposes a part of the surface of the second conductive pillar 15 to The second insulating layer 16 is provided as a ball pad. The surface treatment layer 17 is disposed on the exposed surface of the first circuit layer 11 and the exposed surface of the second conductive pillar 15.

However, in the method of manufacturing the intermediate substrate 1, the surface treatment layer 17, 17' is an organic solder retainer (Organic Solderability Preservative). It is called OSP), which cannot be applied to products where the ball pad (ie, the second conductive column 15) needs to be exposed to general environment for a long time, such as LGA (land grid array) products.

Further, if the surface treatment layer 17' on the ball pad (i.e., the second conductive pillar 15) is changed to the material of chemical nickel palladium gold (ENEPIG) or electroplated nickel gold (Ni/Au), there will be the following problems:

First, the selection process is required (ie, two surface treatments are performed, one is the surface treatment layer 17 of the OSP, and the other is the surface treatment layer 17' of the chemical nickel palladium gold (ENEPIG) or electroplated nickel gold (Ni/Au)) Moreover, it is necessary to cover the photoresist during the process, so that the problem of photoresist deposition is likely to occur, which causes quality risk.

Second, it is difficult to control the problems of intermetallic compounds (IMC) and nickel barriers.

Therefore, how to overcome various problems in the prior art has become a problem that is currently being solved.

In view of the above-mentioned deficiencies of the prior art, the present invention provides an interposer substrate comprising: a first insulating layer having opposite first and second surfaces; and a first circuit layer formed on the first insulating layer And exposing a first surface of the first insulating layer to a surface thereof; a plurality of first conductive pillars are formed in the first insulating layer and disposed on the first circuit layer and connected to the first insulating layer a second surface layer is formed on the second surface of the first insulating layer and electrically connected to the first conductive pillars; and the plurality of second conductive pillars are formed on the second conductive layer The second circuit layer is electrically connected to the second circuit layer; a second insulating layer is formed on the second circuit layer a second surface of an insulating layer for covering the second conductive pillars and the second wiring layer, and exposing an end surface of the second conductive pillar to the second insulating layer; and a plurality of immersion tin plating layers Formed on the exposed surface of the first circuit layer and the end surface of the second conductive pillar.

The invention provides a method for fabricating an interposer, comprising: forming a first circuit layer on a carrier board, and forming a plurality of first conductive pillars on the first circuit layer; forming a first insulating layer on the carrier board The first insulating layer has a first surface and a second surface opposite to each other, and the first insulating layer is bonded to the carrier board by the first surface thereof, and the first conductive pillars are exposed to the first insulating layer a second surface of the layer; a second circuit layer is formed on the second surface of the first insulating layer and the first conductive pillars, and the second circuit layer is electrically connected to the first conductive pillars; a second conductive layer is electrically connected to the second conductive layer, and a second insulating layer is formed on the second surface of the first insulating layer to cover the second conductive layer a second conductive pillar and the second circuit layer, and exposing an end surface of the second conductive pillar to the second insulating layer; removing the carrier plate to expose the first circuit layer to the first of the first insulating layer a surface; and forming an immersion tin plating layer separately from the first circuit layer And the second end surface of the conductive pillar.

In the foregoing method, part or all of the carrier plate can be selectively removed.

In the above-mentioned interposer substrate and the method of manufacturing the same, the first insulating layer is formed on the carrier plate by a molding method, a coating method or a pressing method, so that the material of the first insulating layer is a mold compound, a primer or Dielectric material.

In the above interposer substrate and the method of manufacturing the same, the surface layer of the first circuit layer Lower than the first surface of the first insulating layer.

In the above interposer substrate and the method of manufacturing the same, the end surface of the first conductive pillar is flush with the second surface of the first insulating layer.

In the above interposer substrate and the method of manufacturing the same, the end surface of the second conductive pillar is a spherical surface.

In the above interposer substrate and the method of manufacturing the same, the end surface of the second conductive pillar is flush with the surface of the second insulating layer.

In the above interposer substrate and the method of manufacturing the same, the second insulating layer is formed on the carrier plate by a molding method, a coating method or a press bonding method, so that the material of the second insulating layer is a mold compound and a bottom layer. Paint or dielectric material.

In the above interposer substrate and the method of manufacturing the same, the surface of the immersion tin plating layer is not higher than the first surface of the first insulating layer.

In the above interposer substrate and the method of manufacturing the same, the surface of the immersion tin plating layer is higher than the first surface of the first insulating layer.

In the above interposer substrate and the method of manufacturing the same, the surface of the immersion tin plating layer is not higher than the surface of the second insulating layer.

In the above interposer substrate and the method of manufacturing the same, the surface of the immersion tin plating layer is higher than the surface of the second insulating layer.

In addition, in the foregoing interposer substrate and the method of manufacturing the same, the portion of the carrier is removed, so that the carrier is retained as a supporting structure.

As can be seen from the above, the intermediate substrate of the present invention and the method for preparing the same, the immersion tin plating layer is used as a surface treatment layer, and is suitable for a product in which the ball-filling pad needs to be exposed to a general environment for a long period of time, and does not require a selection process, so the present invention The system of law is relatively simple. Moreover, it is easy to control the intermetallic compound, and there is no problem of barrier of the nickel layer, so the quality is relatively stable.

1, 2, 2'‧‧‧Intermediate substrate

11, 21‧‧‧ first line layer

12, 22‧‧‧ first conductive column

13, 23‧‧‧ first insulation

13a, 23a‧‧‧ first surface

13b, 23b‧‧‧ second surface

14, 24‧‧‧ second circuit layer

15, 25‧‧‧ second conductive column

16, 26‧‧‧Second insulation

17, 17'‧‧‧ surface treatment layer

20‧‧‧Loading board

20a‧‧‧Metal

20’‧‧‧Support structure

21a, 26a, 27a, 27a’‧‧‧ surface

22a, 25a‧‧‧ end face

27, 27'‧‧‧ immersion tin plating

4‧‧‧Electronic components

5‧‧‧ solder balls

6‧‧‧Package colloid

1 is a schematic cross-sectional view of a conventional interposer substrate; FIGS. 2A to 2F are cross-sectional views showing a method of fabricating the interposer of the present invention; wherein the 2F' is a second aspect of FIG. 2F; And the 2G and 2G' diagrams are schematic cross-sectional views of the subsequent processes of the 2Fth diagram.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "upper", "first", "second" and "one" are used in the description, and are not intended to limit the scope of the invention. Changes or adjustments in the relative relationship are considered to be within the scope of the present invention.

Figures 2A to 2F are in the coreless form of the present invention. A schematic cross-sectional view of the method of fabricating the substrate 2. In this embodiment, the interposer 2 is a carrier for a flip-chip chip scale package (FCCSP).

As shown in Fig. 2A, a carrier plate 20 is provided. In the present embodiment, the carrier 20 is a substrate, such as a copper foil substrate, but is not particularly limited. The present embodiment is described by a copper foil substrate having copper-containing metal members 20a on both sides.

As shown in FIG. 2B, a first wiring layer 21 is formed on the carrier 20 by a patterning process.

As shown in FIG. 2C, a plurality of first conductive pillars 22 are formed on the first wiring layer 21 by electroplating by a patterning process.

In the embodiment, the first conductive pillars 22 are in contact with and electrically connected to the first circuit layer 21 .

As shown in FIG. 2D, a first insulating layer 23 is formed on the carrier 20, the first insulating layer 23 has opposite first and second surfaces 23a and 23b, and the first insulating layer 23 The first surface 23a is bonded to the carrier 20, and the first conductive pillar 22 is exposed on the second surface 23b of the first insulating layer 23.

In the present embodiment, the first insulating layer 23 is formed on the carrier 20 by a molding method, a coating method, or a pressing method, and the material of the first insulating layer 23 is a molding compound. , Primer, or dielectric material such as epoxy (Epoxy).

Furthermore, the end surface 22a of the first conductive pillar 22 is flush with the second surface 23b of the first insulating layer 23.

As shown in FIG. 2E, a second circuit layer 24 is formed on the second surface 23b of the first insulating layer 23 and the first conductive pillars 22, and a plurality of second conductive pillars 25 are formed on the second circuit layer. 24, the second circuit layer 24 is electrically connected to the second conductive pillars 25, and then a second insulating layer 26 is formed on the second surface 23b of the first insulating layer 23 to cover the second Conductive post 25 and the second circuit layer 24.

In this embodiment, the end surface 25a of the second conductive pillar 25 is exposed to the second insulating layer 26 such that the end surface 25a of the second conductive pillar 25 serves as a spherical surface. Specifically, the end surface 25a of the second conductive pillar 25 is flush with the surface 26a of the second insulating layer 26.

Furthermore, the second insulating layer 26 is formed by a molding method, a coating method or a press bonding method, and the material forming the second insulating layer 26 is a mold compound, an epoxy resin or a dielectric material.

As shown in FIG. 2F, all the carrier boards 20 are removed, so that the surface 21a of the first circuit layer 21 is exposed on the first surface 23a of the first insulating layer 23, and the surface 21a of the first circuit layer 21 is Lower than the first surface 23a of the first insulating layer 23. Next, an Immersion Tin layer 27, 27' is formed on the surface 21a of the first wiring layer 21 and the end surface 25a of the second conductive pillar 25, respectively.

In this embodiment, the metal material 20a is removed by etching, so that the surface 21a of the first circuit layer 21 is slightly etched, so that the surface 21a of the first circuit layer 21 is dimpled to the insulating layer 23. First surface 23a.

Moreover, when etching the metal material 20a, the end surface 25a of the second conductive pillar 25 is slightly etched, so that the end surface 25a of the second conductive pillar 25 is lower than The surface 26a of the second insulating layer 26.

Further, the surface 27a of the one side immersion tin plating layer 27 is higher or lower than the first surface 23a of the first insulating layer 23. Alternatively, the surface 27a of the immersion tin-plated layer 27' on the other side is higher or lower than the surface 26a of the second insulating layer 26.

As shown in Fig. 2F', the patterned etching removes portions of the carrier 20 so that the carrier is retained as the support structure 20'.

In the subsequent process, as shown in FIG. 2G, the electronic component 4 is disposed on the first surface 23a of the first insulating layer 23, and the electronic component 4 is electrically connected to the first circuit layer 21 and packaged. The colloid 6 covers the electronic component 4 to complete an LGA (land grid array) product.

Or, as shown in FIG. 2G', the electronic component 4 is disposed on the first surface 23a of the first insulating layer 23, and the electronic component 4 is electrically connected to the first circuit layer 21, and forms a plurality of solder balls. 5 is on the immersion tin layer 27' on the second conductive pillar 25 to complete a BGA (ball grid array) product.

Therefore, the method of the present invention uses the immersion tin plating layer 27, 27' as a surface treatment layer, which can be applied to a product in which the ball pad (ie, the second conductive pillar 25) needs to be exposed to a general environment for a long period of time, such as LGA ( Land grid array) products.

Furthermore, the process of the invention is relatively simple, and the process of the invention is not required.

Moreover, it is easy to control an intermetallic compound (IMC), and there is no problem of a nickel barrier, so that the quality is relatively stable.

The present invention further provides an interposer substrate 2, 2' comprising: a first insulating layer 23, a first wiring layer 21, a plurality of first conductive pillars 22, and a second The circuit layer 24, the plurality of second conductive pillars 25, a second insulating layer 26, and a immersion tin plating layer 27.

The first insulating layer 23 has a first surface 23a and a second surface 23b opposite to each other, and the first insulating layer 23 is a mold compound, an epoxy resin or a dielectric material.

The first circuit layer 21 is embedded in the first surface 23a of the first insulating layer 23, and the surface 21a of the first circuit layer 21 is lower than the first surface 23a of the first insulating layer 23.

The first conductive pillar 22 is formed in the first insulating layer 23 and communicates with the second surface 23b of the first insulating layer 23, and the end surface 22a of the first conductive pillar 22 is flush with the first insulating layer. The second surface 23b of layer 23.

The second circuit layer 24 is formed on the second surface 23b of the first insulating layer 23 and the first conductive pillars 22 and electrically connected to the first conductive pillars 22.

The second conductive pillar 25 is formed on the surface 24a of the second circuit layer 24 and electrically connected to the second circuit layer 24, and the end surface 25a of the second conductive pillar 25 is a spherical surface.

The second insulating layer 26 is formed on the second surface 23b of the first insulating layer 23 to cover the second circuit layer 24 and the second conductive pillar 25, and the end faces of the second conductive pillars 25 25a is exposed to the second insulating layer 26.

The immersion tin plating layer 27, 27' is formed on the surface 21a of the first wiring layer 21 and the end surface 25a of the second conductive pillars 25.

In one embodiment, the immersion tin layer 27 is higher or lower than the first surface 23a of the first insulating layer 23.

In one embodiment, the immersion tin layer 27' is higher or lower than the surface 26a of the second insulating layer 26.

In one embodiment, the interposer substrate 2' includes a support structure 20' disposed on the first surface 23a of the first insulating layer 23.

In summary, the interposer substrate and the method for manufacturing the same are mainly applied to products with fine pitch and high number of package stack structures, such as smart phones, tablets, Netcom, notebook computers, etc., and the products need to be The high-frequency high-speed operation, the thin and light design, the stronger the function, the faster the storage and the higher the storage amount, the more the intermediate substrate of the present invention is used.

Furthermore, the interposer substrate 2, 2' of the present invention can be combined with the logic package or the memory package by the first circuit layer 21, and the logic package or the memory package can be combined by the second conductive pillar 25. .

The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

2‧‧‧Intermediate substrate

21‧‧‧First line layer

21a, 26a, 27a, 27a’‧‧‧ surface

22‧‧‧First conductive column

23‧‧‧First insulation

23a‧‧‧ first surface

23b‧‧‧ second surface

24‧‧‧Second circuit layer

25‧‧‧Second conductive column

25a‧‧‧ end face

26‧‧‧Second insulation

27, 27'‧‧‧ immersion tin plating

Claims (25)

An interposer includes: a first insulating layer having opposite first and second surfaces; a first circuit layer formed in the first insulating layer, and one surface of the first circuit layer Exposing the first surface of the first insulating layer; a plurality of first conductive pillars are formed in the first insulating layer and disposed on the first circuit layer and connected to the second surface of the first insulating layer; a second circuit layer is formed on the second surface of the first insulating layer and electrically connected to the first conductive pillars; and the plurality of second conductive pillars are formed on the second circuit layer And electrically connecting the second circuit layer; a second insulating layer is formed on the second surface of the first insulating layer to cover the second conductive pillars and the second circuit layer, and The end surface of the second conductive pillar is exposed on the second insulating layer; and the plurality of immersion tin plating layers are respectively formed on the exposed surface of the first circuit layer and the end surface of the second conductive pillar. The interposer according to claim 1, wherein the material forming the first insulating layer is a mold compound, a primer or a dielectric material. The interposer substrate of claim 1, wherein the surface of the first circuit layer is lower than the first surface of the first insulating layer. The interposer substrate of claim 1, wherein an end surface of the first conductive pillar is flush with the second surface of the first insulating layer. The interposer substrate of claim 1, wherein the end face of the second conductive post is a spherical surface. The interposer substrate of claim 1, wherein an end surface of the second conductive pillar is flush with a surface of the second insulating layer. The interposer according to claim 1, wherein the material of the second insulating layer is a mold compound, a primer or a dielectric material. The interposer substrate of claim 1, wherein the surface of the immersion tin plating layer is not higher than the first surface of the first insulating layer. The interposer substrate of claim 1, wherein the surface of the immersion tin plating layer is higher than the first surface of the first insulating layer. The interposer substrate according to claim 1, wherein the surface of the immersion tin plating layer is not higher than the surface of the second insulating layer. The interposer substrate of claim 1, wherein the surface of the immersion tin plating layer is higher than the surface of the second insulating layer. The interposer substrate of claim 1, further comprising a support structure disposed on the first surface of the first insulating layer. The method for manufacturing an interposer includes: forming a first circuit layer on a carrier board, and forming a plurality of first conductive pillars on the first circuit layer; forming a first insulating layer on the carrier board, the first The insulating layer has opposite first and second surfaces, and the first insulating layer is bonded to the carrier by the first surface thereof, and the first conductive pillars are exposed to the second of the first insulating layer surface; Forming a second circuit layer on the second surface of the first insulating layer and the first conductive pillars, and the second circuit layer is electrically connected to the first conductive pillars; forming a plurality of second conductive pillars in the first a second circuit layer electrically connected to the second conductive pillars; a second insulating layer is formed on the second surface of the first insulating layer to cover the second conductive pillars and the a second circuit layer, and exposing an end surface of the second conductive pillar to the second insulating layer; removing the carrier plate to expose the first circuit layer to the first surface of the first insulating layer; The tin plating layer is on the exposed surface of the first circuit layer and the end surface of the second conductive pillar. The method of fabricating an interposer according to claim 13 , wherein the first insulating layer is formed on the carrier by a molding method, a coating method or a press bonding method. The method of fabricating an interposer according to claim 13, wherein the surface of the first circuit layer is lower than the first surface of the first insulating layer. The method of fabricating the interposer according to claim 13 , wherein the end faces of the first conductive pillars are flush with the second surface of the first insulating layer. The method for manufacturing an interposer according to claim 13, wherein the end face of the second conductive post is a spherical surface. The method for preparing an interposer substrate according to claim 13 of the patent application, The end surface of the second conductive pillar is flush with the surface of the second insulating layer. The method of fabricating an interposer according to claim 13, wherein the second insulating layer is formed by a molding method, a coating method, or a press bonding method. The method of fabricating an interposer according to claim 13, wherein all of the carrier plates are removed. The method of fabricating an interposer according to claim 13, wherein a portion of the carrier is removed such that the carrier is retained as a support structure. The method of fabricating an interposer according to claim 13, wherein the surface of the immersion tin plating layer is not higher than the first surface of the first insulating layer. The method of fabricating an interposer according to claim 13, wherein the surface of the immersion tin plating layer is higher than the first surface of the first insulating layer. The method of fabricating the interposer substrate according to claim 13, wherein the surface of the immersion tin plating layer is not higher than the surface of the second insulating layer. The method of fabricating an interposer according to claim 13, wherein the surface of the immersion tin layer is higher than the surface of the second insulating layer.