201002166 【發明所屬之技術領域】 . 丨發明係有關於—種電路板及其製法，尤指-種電路 .板之層間線路層的電性連接結構及其製法。 【先前技術】 - 豸著電子產業的蓬勃發展，電子產品亦逐漸邁入多功 能、南性能的研發方向。為滿^半導體封裝件高積华产 (mtegrat刚）以及微型化（Miniaturizat應）的封^ 需求，承載半導體晶片之封姑这4 、 封裒基板，逐漸由雙層板演變成 多層板（㈣卜1咖B0ard)，俾於有限的空間下1 由層間連接技術（I n t r 1 a v ^ ^「 · ayer Connection)以擴大封裝 土板上可利用的線路面積，古帝— 、 口應问电子岔度之積體電路 (Integrated Circuit)的使用兩卡.失山^ ^ ,. 便用而求，為此，遂發展出一 種增層技術（build-up)，亦卽力社# 〜仙b〇ard)表面利用二=: 板（咖 雷W持找/ 增層技術交互堆疊多層介 ^ "曰，亚於該介電層中開設導電盲孔 (conductive via)以供上、下層線路之間電性連接。 為因應微處理器、晶片組、怜 電路Usin辇日、、，日囷日日片與特殊應用積體 1C)寺尚效能晶片之瞀兩 封裝乏運π而要，佈有線路之半導體 =基板亦4升其傳遞晶片訊號、改善頻寬、㈣ ==以因應高1/0數封裝件的發展;且為符：半“ 裝件輕涛短小、多功能、高速度、高線路穷产及 方向’封裝基板已朝向細線路及小孔現有 〜封裝基板製程從傳統⑽微米之線路尺寸:已二 110821 5 201002166 包括導線覓度（1 ine width) 向更小的線路精度進行研 王π牡的30微米以下，其中， 及線路間距（Space)等持續朝 /發。 请參閱f IAS 1G 1)所示，係顯示習知封裝基板之製 :’如第1A圖所示，提供一核心板1〇，該核心板1〇 : f〇r目對之表面於該表面W成有核心線路層 ，亚於該核心板10中形成有導電通孔102,以電性連 接該:心板1◦表面1 一線路層如第二 不，於該核心板10之表面10 上形成有第-介電層12a，且該二:二::;線:層101 =介=開孔心’以顯露部份之核心 第1C圖所不’於該第一介電層⑸上 :表面，形成有導電層13,且於該導電層13上开;：： 且匕14，並使該阻層工 ’有 電層13之部份表面，且開「口區140以露出該導 層開孔12Ga;如f 1D # σ °° 14G對應各該介電 中的導電層u上電且層Μ 一介電層12a之介# ^ 線路層15a，且於該第 书層開孔1 2〇a φ形士士 μ ... ⑸"電性連接該 ：成有弟-導電盲孔 移除該阻層14及复所f t層101圖所示， 路層15a’·如第1F :: ¥電層13,以露出該第-線 介電層12a上开彡士 '不，於该第一線路層15&及第一 有至少-第：人带有〜層結構16 ’該增層結構1 6係包括 線路層W、—:及？ 12广形成於該第二介 \數形成於該第三介電層之中並電性連 11082] 6 201002166 線路層之第二導電盲孔151b，其中部份之第二 • ^电目孔151b電性連接該第—線路層15&;如第 戶: ' T，於該增層結構1 6最外層之第_缚& β ^斤 '弟—、'泉路層15b形成有複 π，並於該防焊層17 上$成有防谭層 •對庫-屮夂π 巾升乂成有複數個防焊層開孔17〇以 對二路出各戎％性接觸墊1 64。 =雷射鑽孔形成之介電層開孔120a係為 門=錐形孔之底部因雷射形成有膠渣，使得 f路層T〇;3:CL壁、介電層開孔120a中之核心線 潰〜一)之製程，然後再形成線路; 則膠清對後續再米：：： “隹形孔之孔徑越小’ —對後、再形成線路之結合性的影響越大；再 ^電層開孔120a顯露該核心線路層m之底部的口徑= 接觸2降低該第—導電盲孔151a與核心線路層101之 接面積，使得該第—導電盲孔1513與核 i之間的結合性降低，㈣料電性連接的可靠度。 各^射鑽孔之精度及開孔的孔徑有其限制，並益 :=縮小，因而影響高密度佈線之使用需： 線路製程能力之提升。 於、、、田 又该雷射鑽孔形成之介電層開孔120a係為外大内小 f錐形孔’且於該錐形孔之底部因f射形成有膠渣，使得 電層開孔12〇a之孔壁、介電層開孔i2〇a中之核心線 路層ιοί等表面與導電層13之間的結合性不佳，必須^ Π0821 7 201002166 查(Desmear)之製程’然後再形成線路；惟去， “如必能將膠渣完全去除，且當錐形孔 ， 編對後續再形成線路之結合性的影響越大；=， .開孔_顯露該核心線路層1〇1之底::口 .=，因而降低該第-導電盲細a與核心線路二 ==，使得該第—導電盲孔咖與核心線路们G1 B 、結合性降低，進而影響電性連接的可靠声。 =該雷㈣孔之精度及開孔絲有其_ 路製程能力之提升。 之使用而求，有礙於細線 因此’如何提高形成於該介電層 其電性連接之線路之間的社八強声w 了之W目孔與 【發明布摘，仍存在其技術瓶頸而有待克服。 釔於以上所述習知技術之缺點，本發明之φ i 提供一種電路板及法，月之主要目的係 可靠度連接’而可大破雷射開孔之限制以提高佈線密度及 孔;核心線路層二並具有複數貫穿兩表面之通 孔中执有^ θ、d%緣板之表面上，並於各該通 心線：電性連接該絕緣板之兩表面上的核 上;複二:；，，係設於該絕緣板及核心線路層 电柱，係設於該第一介電層中，並電性連 110821 8 2010021^心線路層，且該些第一導電柱之端面與第一介電 層表面齊平；第二導電層，係設於該第一導電柱上；以及 第一線路層，係設於該第一介電層上，該第一線路層具有 複數第一電性連接墊，且該些第一電性連接墊係對應設於 各該第一導電柱之第二導電層上，以電性連接各該第一導 電柱。 依上述之電路板，該第一電性連接墊係大於、等於或 小於該第一導電柱。 , 依上述之結構，復包括增層結構，係設於該第一介電 層及第一線路層上，該增層結構係包括至少一第二介電 層、設於該第二介電層上之第二線路層、以及複數設於該 第二介電層之中並電性連接該第一線路層及第二線路層 之第二導電柱，該第二線路層復包括複數第二電性連接 墊，且該些第二電性連接墊係對應形成於各該第二導電柱 上，該第二電性連接墊係大於、等於或小於該第二導電柱。 依上所述，復包括複數電性接觸墊，係設於該增層結 C 構最外層之第二線路層上，於該增層結構之最外層上設有 防焊層，並於該防焊層中設有複數個防焊層開孔，以對應 露出各該電性接觸墊。 本發明復提供一種電路板，係包括：絕緣板，係具有 兩表面，並設有複數貫穿兩表面之通孔；核心線路層，係 設於該絕緣板之兩表面上，並於該些通孔中設有對應之導 電通孔以電性連接該絕緣板兩表面之核心線路層；複數第 一導電柱，係分別設於部份之核心線路層上；第一介電 9 110821 /首…即fcSL於該絕緣板、核心線路層及第一導電柱上，該第 一介電層具有複數第一開槽，且該些第一開槽並對應露出 /各該第一導電柱之端面；第二導電層，係設於該第一開槽 之表面、及第一導電柱上；以及第一線路層，係設於該第 一開槽中之第二導電層上，且該第一線路層具有複數第一 電性連接墊，以對應電性連接至各該第一導電柱，該第一 線路層並與第一介電層齊平。 依上述之電路板，該第一電性連接墊係大於、等於或 小於該第一導電柱。 依上述之結構，復包括增層結構，係設於該第一介電 層及第一線路層上，該增層結構係包括有至少一具有第二 開槽之第二介電層、設於該第二介電層之第二開槽中之具 有第二電性連接墊之第二線路層、以及複數設於該第二介 電層中並電性連接該第一線路層及第二線路層之第二電 性連接墊的第二導電柱，又該第二線路層之表面與第二介 電層之表面齊平，該第二電性連接墊係大於、等於或小於 、 該第二導電柱。 依上所述，復包括複數電性接觸墊，係設於該增層結 構最外層之第二線路層，於該增層結構之最外層上設有防 焊層，並於該防焊層中形成有複數個防焊層開孔，以對應 露出各該電性接觸墊。 本發明復提供一種電路板之製法，係包括：提供一絕 緣板，係具有兩表面，於該絕緣板中並形成有複數貫穿兩 表面之通孔；於該絕緣板上電鍍形成有核心線路層，且於 10 110821 ^ ^ U 中形成有對應之導電通孔，以電性連接該絕緣板 之兩表面的核心線路層；於該核心線路層上電鍍形成有複 /數第一導電柱；於該絕緣板、核心線路層及第一導電柱上 形成有第一介電層；移除部份之第一介電層，以露出該些 第一導電柱之端面；於該第一介電層及第一導電柱之端面 上形成有第二導電層；以及藉由該第二導電層以於該第一 介電層及第一導電柱上電鍍形成有第一線路層。 依上述之電路板之製法，該核心線路層及第一導電柱 之製法，係包括：於該絕緣板及其通孔之孔壁上形成有第 一導電層；於該第一導電層上形成有第一阻層，且該第一 阻層中形成有複數第一開口區，以露出部份之第一導電 層，又部份第一開口區對應該通孔及其孔端周圍之第一導 電層；於該第一開口區中形成該核心線路層，且於該通孔 中形成有導電通孔，以電性連接該絕緣板之兩表面上的核 心線路層；於該第一阻層及核心線路層上形成有第二阻 層，且該第二阻層中形成有複數第二開口區，以露出部份 ί 之核心線路層；於該些第二開口區中對應電鑛形成有第一 導電柱；以及移除該第二阻層、第一阻層及其所覆蓋之第 一導電層。 依上述之製法，該第一線路層復包括複數第一電性連 接墊，且該第一電性連接墊係形成於該第一導電柱上，該 第一電性連接墊係大於、等於或小於該第一導電柱。 依上所述，復包括於該第一線路層上電鍍形成有複數 第二導電柱，該第一線路層及第二導電柱之製法，係包 11 110821 第一介電層及第一導電柱之端面上形成該第二導 電層；於該第二導電層上形成有第三阻層，且於該第三阻 / 層中形成有複數第三開口區，以露出部份之第二導電層， : 且部份之第三開口區對應該第一導電柱之端面上的第二 導電層；於該第三開口區中形成該第一線路層，使該第一 線路層電性連接該第一導電柱；於該第一線路層及第三阻 層上形成有第四阻層，且該第四阻層中形成有複數第四開 口區，以露出部份之第一線路層；於該第四開口區中形成 該第二導電柱，使該第二導電柱電性連接該第一線路層； 移除該第四阻層、第三阻層及其所覆蓋之第二導電層，以 露出該第二導電柱及第一線路層。 復包括於該第一介電層、第一線路層及第二導電柱上 形成有增層結構，該增層結構係包括有至少一第二介電 層、形成於該第二介電層上之第二線路層、以及複數形成 於該第二介電層之中並電性連接該第一線路層及第二線 路層之第二導電柱，該第二線路層復包括複數第二電性連 ^ 接墊，且該些第二電性連接墊係對應形成於各該第二導電 柱上，該第二電性連接墊係大於、等於或小於該第二導電 柱。 復包括於該增層結構最外層之第二線路層上形成有 複數電性接觸墊，於該增層結構之最外層上形成有防焊 層，並於該防焊層中形成有複數個防焊層開孔以對應露出 各該電性接觸墊。 本發明復提供一種電路板之製法，係包括：提供一絕 12 110821 201002166 —丁'具有兩表面，方M亥絕緣 表面之通孔；於哕頌铁4 卫小成有歿數貫穿兩 、札，万、3絕緣板之兩表面上 /層，且於該些通孔中對岸 1形成有核心線路 . 了應形成有導電通孔，η带k、土， «絕緣板兩表面之核θ έ% β 电性連接該 四又极u線路層；於部份之 形成有第—導雷括 心“，、泉路層上電鍍 _柱上形成有第一介電層;於該 層及弟-導電 一開槽，且該笫一 π描+ ;丨包層中形成有複數第 -介電層、第-開槽之表面及第一：而面’·於該第 電層；以及藉由兮电上形成有第二導 久稭由6亥弟—導電層以於該第一 有第一線路層，且該第— ㈢中-电鍍形成 性連接至該第—導電柱。s八弟一電性連接墊以電 依上述之電路板之製法， 之製法，係包括·於兮“ 線路層及第-導電柱 匕括·於5亥絕緣板及其通 —導電層；於該第一導電層上形 ▲形成有第 層中形成有複數第pa ^ 一阻層，該第一阻 且部份之以露出部份之第-導電層， 導電層;孔及其孔端周圍之第- 通孔中對庫❹右省/也成5亥核心線路層，且於該些 面上的核心線路層;於該第一阻;=接:絕緣板之兩表 第- R日層及核心線路層上形志右 一曰，且該第二阻層中形成有複數第二 、雨 邻份之核心線路層；於各該二 品以路 該第—導+ —開 £中對應電鍍形成 蓋之第—導電層。 阻層弟一阻層及其所覆 依上述之製法，該第一線路層之部份表面上復包括電 110821 13 201002166 第二導電柱，該第一電性連 — 小於該第一導電柱。 冰大灰、寺於或 . 依上所述，復包括於該第一介電芦、蒙一持 '二導電柱上形忐古4、，^弟、、泉路層及第 ，且古〜有增層結構，該增層結構係包括有至+一 *具有弟二開槽之第二介電層、形成於該 八+ ^一 開神中且·JL•穿 ^ 弟—7丨電層之第- 開才㈢中具另弟二電性連接塾之第 〈弟一 於該第二介電声中# + # έ & 、路層、以及複數形成 声之第；生二 該第—線路層及第二線路 滑之弟_包性連接塾的第二導電柱，又 I路 面與第-介帝岛々主_ 弟一線路層之表 弟一；丨毛層之表面齊平，該第二 不 等於或小於該第m。 $接塾係大於、 復包括於該增層結構最外層 複數電性接觸塾，於該增層結構之；：：：層上形成有 層，並於該防谭層中形成有複數個防焊二；防谭 各該電性接觸墊。 θ 4孔以對應露出 本發明之電路板及其製法，能形成 路層之電性連接，而可突4羽 I柱作為層間線 牧叩J大破白知糟由雷射 孔之孔徑限制及避免產生膜 h層進订開 可靠度。 H查的問碭’以提高佈線密度及 【實施方式】 以下藉由特定的具體實施例 式，孰籴此#蓺+ Λ 1 月本^明之貫施方 ,，·、’“技蟄之人士可由本說明書所揭示之向旦^ 瞭解本發明之其他優點及功效。 之内谷輕易地 [第一實施例] 凊芩閱第2A至2N圖，係鞀干太於nn 口係㉝不本發明之電路板之製法 】1082] ]4 201义02%例之剖面示意圖。 如第2A圖所示，首先’提供一具有兩表 ...‘緣板20，於該絕緣板2〇中並形成有複數貫穿兩表面20a ，之通孔201。 如f 2B圖所示，於該絕緣板2〇及其通孔2 上形成有第一導電層2la;接著，於該第一 ： 形成有第一阻層22a，且該第—阻層他中❹= 口區馳以露出部份之第一導電層⑴，又== :區綠對應各該通孔2G1及其孔端周圍之第一:電： 如第2C圖所示，於該第—開口區22()a中電鑛 核心線路層202，且於該通孔201中形成有^電通孔 ==電性連接該絕緣板2〇之兩表面如上的核心線 上开=Γ-圖所示’於該第一阻層…及核心線路層2〇2 上开/成有第—阻層22b，且辞楚-rrn a 丄 — w亥弟—阻層2化中形成有複數 弟一開:區22Gb’以露出部份之核心線路層2〇2。 如第2E圖所示，於該些第二開口區2_ 形成有第—導電柱23a，使該些第一導電柱⑽電 至該核心線路層202。 如第2F圖所示，移除該第二阻層2化、第一阻 及其所覆蓋之第一莫带爲91 導电層21a，以露出該核心線路層202 及第一導電杈23a。 如第2G圖所示，於該絕緣板2〇、核心線路層2〇2及 110821 15 201002166 和―〒电柱233上形成有第一介電層2知 如第2H圖所示，移除部份之第— 出該些第一導電柱23a之端面。 兒g 24a，以露 介電層24a及第—導電柱 第 如第21圖所示 咖之端面上形成有第二導電層2ib 弟^~導電柱 電層21b上形成有第三阻層22c，且於—方、该第-導 形成有複數第三開口區220c，以露出層，中 …部份之第三開口鳴對應各 之端面上的第二導電層21b。 包柱23a 〜如第2J圖所示，於該第三開口區22〇c中 =、、泉路層25a，且該第-線路層祝具有複數^ 一 2墊251a’使該些第―f性連接㈣ ^ ::該:::電柱1且該些第-電性連接塾= 、寻於或小於該第一導電柱23a。 切圖所示’於該第—線路層25a及第三阻層22c ^有第四阻層22d ’且該第四阻層_中形成有複數 開:區22Gd ’以露出部份之第-線路層25a。 士曾口第2L圖所示’於該第四開口區22〇d中電鑛形成有 f — V電柱23b，使該第二導電柱2补電性連接至 線路層25a。 如第2M圖所示，移除該第四阻層22d、第三阻層22c 所覆蓋之第二導電層2lb，以露出該第二導電桎23b 及弟一線路層25a。 如第2N圖所示，之後重覆第2G至2M圖之製法，以 110821 16 201002166 心乐-介電層24a、第-線路層25a及第二導電柱伽 .上形成有增層結構26,該增層結構26係包括有至少 '二介電層祕、形成於該第二介電物上之第二線路層 — 以及複數設於該弟二介電層⑽之中並電性連接該 B及第二線路層挪之第二導電嫌該 •此第二二2 5 b復包括後數第二電性連接塾⑸b，且該 = 23b係對應電性連接至各該第二電性連接 1—b數=該增層結構26最外層之第二線路層现 數電性接觸墊264 ’且於該增層結構26之最外層 焊^門ΠτΓ 27，並於該防焊層27中形成有複數個防 4層開孔270’以對應露出各該電性接觸墊咖。 呈有^明復提供一種電路板，係包括：絕緣板20，係 =表面2Ga，並具有複數貫穿兩表面如 核轉路層2〇2,係設於該絕緣板2〇之表面咖上〇1甘 於忒通孔201中設有導電通孔2〇2a，以带 ^ :2◦之兩表面2〇a i的核心線路層2: 一 ==於_緣…核心線路物上;複= 二電才23a，係設於該第一介電層…中，並電性 電：:=02’且該第一導電柱W之端面與 二4:表面齊平；第二導電層仙，係設於該第一導電 a上，以及第一線路層25a，係設於該第一介電 上H線路層25a具有複數第—電性連接墊曰 且该些第一電性連接墊251争 a， 一二導電層二導電柱 书丨王連接至各該第一導電柱 130821 17 201002166201002166 [Technical Field to Be Invented by the Invention] The invention relates to a circuit board and a method of manufacturing the same, and more particularly to a circuit, an electrical connection structure of an interlayer circuit layer of a board, and a method of manufacturing the same. [Prior Art] - Taking advantage of the booming electronics industry, electronic products are gradually entering the development direction of multi-function and south performance. In order to meet the needs of the semiconductor package (Mtegrat just) and miniaturization (Miniaturizat), the semiconductor substrate is sealed, and the substrate is gradually changed from a double-layer board to a multi-layer board ((4) Coffee B0ard), in a limited space 1 by the inter-layer connection technology (I ntr 1 av ^ ^ " · ayer Connection) to expand the available circuit area on the package soil, the ancient emperor -, the mouth should ask the electronic temperature The use of integrated circuits (two integrated cards) is lost. ^ ^ ,. It is used for this purpose, 遂 developed a build-up technology (build-up), also 卽力社# 仙仙b〇ard) Surface utilization two =: board (Care W holding / layering technology interactive stacking multilayer ^ " 曰, in the dielectric layer to open a conductive via (conductive via) for the electrical connection between the upper and lower lines In order to respond to the microprocessor, chipset, Psychic Usin, Japan, Japan, Japan, Japan, Japan, Japan, Japan, Japan, Japan, Japan, Japan, Japan, Japan, Japan, Japan, Japan, Japan, Japan, Japan, Japan, Japan, Japan, Japan, Japan, Japan = The substrate is also 4 liters, which transmits the chip signal, improves the bandwidth, and (4) == 1/0 number of package developments; and for the symbol: semi-"mounting light, short, multi-function, high-speed, high-line production and direction' package substrate has been oriented toward fine lines and small holes existing ~ package substrate process from the traditional (10) Micrometer line size: already two 110821 5 201002166 including wire twist (1 ine width) to less than 30 micrometers of the fineness of the line, and the line spacing (Space) and so on. Please refer to the f IAS 1G 1), which shows the manufacture of a conventional package substrate: 'As shown in FIG. 1A, a core board 1〇 is provided, the core board 1〇: f〇r facing the surface W is formed with a core circuit layer, and a conductive via hole 102 is formed in the core board 10 to electrically connect the core board 1 ◦ surface 1 and a circuit layer such as a second layer on the surface 10 of the core board 10 A first dielectric layer 12a is formed, and the two: two::; line: layer 101 = dielectric = open core 'to expose the core of the core 1C to the first dielectric layer (5): a conductive layer 13 is formed on the surface, and is opened on the conductive layer 13; and: 匕14, and the resist layer is formed to have a part of the surface of the electric layer 13, and the "mouth region 140 is opened to expose the conductive layer. The opening 12Ga; for example, f 1D # σ °° 14G corresponds to the conductive layer u in each of the dielectrics and is electrically connected to the dielectric layer 12a, and the circuit layer 15a is opened in the first layer. 〇a φ 形士士μ ... (5)" Electrical connection: Having a brother-conductive blind hole to remove the resistive layer 14 and the ft layer 101 shown in the figure, the road layer 15a'· as in 1F :: ¥Electrical layer 13 to expose the first-line dielectric layer 12a on the open gentleman' In the first circuit layer 15 & and the first has at least - the first: a person with a ~ layer structure 16 'the layered structure 16 includes a circuit layer W, -: and 12 wide formed in the second interface The number is formed in the third dielectric layer and electrically connected to the second conductive via hole 151b of the 201002166 circuit layer, and a part of the second electrical hole 151b is electrically connected to the first circuit layer 15& ;; as the first household: 'T, in the outermost layer of the layered structure, the first outer layer of the _ binding & β ^ 斤 ' brother -, 'spring layer 15b formed with complex π, and on the solder resist layer 17 It has an anti-tank layer. • The library-屮夂π towel is upgraded into a plurality of solder mask openings 17〇 to the second way. Each contact pad is 1 64. = The dielectric layer formed by laser drilling The opening 120a is a process in which the bottom of the gate=conical hole is formed by the laser, so that the f-layer T〇; 3: the CL wall, the core line in the dielectric layer opening 120a is broken, and then the process is performed, and then Re-form the line; then the glue clears the subsequent re-meter::: "the smaller the aperture of the 隹-shaped hole" - the greater the influence of the combination of the subsequent and re-formed lines; the electric layer opening 120a reveals the core circuit layer The mouth at the bottom of m The reduction of the contact 2 = - bonding area 151a and the conductive vias 101 of the core circuit layer, such that - of conductive vias 1513 and binding between the nuclear i decreases, the reliability of electrical connection material (iv). The accuracy of each hole and the aperture of the hole have their limitations, and the benefits are reduced by =, thus affecting the use of high-density wiring: The improvement of the line process capability. The dielectric layer opening 120a formed by the laser drilling is formed by the outer large small f-conical hole ', and the slag is formed at the bottom of the tapered hole by the f-shooting, so that the electric layer is opened. The hole between the hole wall of the hole 12〇a, the core circuit layer ιοί in the dielectric layer opening i2〇a, and the conductive layer 13 is not good, and must be processed by the method of Desmear's and then '0821 7 201002166 Form the line; only go, "If the glue can be completely removed, and the effect of the tapered hole, the combination of the subsequent re-formation of the line is greater; =, . Opening_ reveal the core circuit layer 1〇1 The bottom:: mouth. =, thus reducing the first-conducting blind a and the core line two ==, so that the first conductive blind hole coffee and the core line G1 B, the combination is reduced, thereby affecting the reliability of the electrical connection Sound. = The accuracy of the (4) hole and the opening of the wire have an improvement in its process capability. The use of the wire is hindered by the thin wire and therefore how to improve the formation of the electrical connection between the wires of the dielectric layer. The eight major voices of the Society have been able to overcome the problem of the W mesh hole and the invention, but it still needs to be overcome. Knowing the shortcomings of the technology, the φ i of the present invention provides a circuit board and a method, and the main purpose of the month is the reliability connection', and the limitation of the laser opening is large to increase the wiring density and the hole; the core circuit layer has a plurality of The through holes of the two surfaces are on the surface of the θ, d% edge plate, and are respectively connected to the cores on the two surfaces of the insulating plate; the second is; The insulating plate and the core circuit layer are disposed in the first dielectric layer and electrically connected to the 110821 8 2010021^ core layer, and the end faces of the first conductive columns are flush with the surface of the first dielectric layer a second conductive layer is disposed on the first conductive pillar; and a first circuit layer is disposed on the first dielectric layer, the first circuit layer has a plurality of first electrical connection pads, and the The first electrical connection pads are respectively disposed on the second conductive layer of each of the first conductive pillars to electrically connect the first conductive pillars. According to the circuit board, the first electrical connection pad is larger than Is equal to or smaller than the first conductive column. According to the above structure, the complex layer structure is included. On the first dielectric layer and the first circuit layer, the build-up structure includes at least one second dielectric layer, a second circuit layer disposed on the second dielectric layer, and a plurality of second layers And electrically connecting the second conductive pillars of the first circuit layer and the second circuit layer, wherein the second circuit layer comprises a plurality of second electrical connection pads, and the second electrical connection pads are Correspondingly formed on each of the second conductive pillars, the second electrical connection pad is greater than, equal to, or smaller than the second conductive pillar. According to the above, the plurality of electrical contact pads are included in the build-up junction. a second soldering layer is disposed on the outermost layer of the C-layer, and a plurality of solder resist openings are formed in the solder resist layer to correspondingly expose the electrical properties. Contact pad. The present invention provides a circuit board comprising: an insulating plate having two surfaces and having a plurality of through holes penetrating through the two surfaces; a core circuit layer disposed on both surfaces of the insulating plate, and The hole is provided with a corresponding conductive through hole to electrically connect the core circuit layer on both surfaces of the insulating plate; the plurality of first conductive columns are respectively disposed on a part of the core circuit layer; the first dielectric is 9 110821 /... That is, the fcSL is on the insulating plate, the core circuit layer, and the first conductive pillar, the first dielectric layer has a plurality of first slots, and the first slots are corresponding to the exposed end faces of the first conductive pillars; a second conductive layer is disposed on the surface of the first trench and the first conductive pillar; and a first circuit layer is disposed on the second conductive layer in the first trench, and the first line The layer has a plurality of first electrical connection pads for electrically connecting to the first conductive pillars, the first circuit layer being flush with the first dielectric layer. According to the above circuit board, the first electrical connection pad is greater than, equal to, or smaller than the first conductive post. According to the above structure, the multi-layer structure is provided on the first dielectric layer and the first circuit layer, and the build-up structure includes at least one second dielectric layer having a second trench, and is disposed on a second circuit layer having a second electrical connection pad in the second trench of the second dielectric layer, and a plurality of second dielectric layers disposed in the second dielectric layer and electrically connected to the first circuit layer and the second circuit a second conductive pillar of the second electrical connection pad of the layer, wherein the surface of the second circuit layer is flush with the surface of the second dielectric layer, the second electrical connection pad is greater than, equal to or less than, the second Conductive column. According to the above, the plurality of electrical contact pads are disposed on the second circuit layer of the outermost layer of the buildup structure, and a solder resist layer is disposed on the outermost layer of the buildup structure, and the solder resist layer is disposed in the solder resist layer A plurality of solder mask openings are formed to correspondingly expose the respective electrical contact pads. The invention provides a method for manufacturing a circuit board, comprising: providing an insulating plate having two surfaces, wherein a plurality of through holes penetrating through the two surfaces are formed in the insulating plate; and a core circuit layer is formed on the insulating plate And a corresponding conductive via hole is formed in 10 110821 ^ ^ U to electrically connect the core circuit layers on both surfaces of the insulating plate; and the first/first conductive pillar is formed on the core circuit layer; Forming a first dielectric layer on the insulating plate, the core circuit layer and the first conductive pillar; removing a portion of the first dielectric layer to expose end faces of the first conductive pillars; and the first dielectric layer And forming a second conductive layer on the end surface of the first conductive pillar; and forming a first circuit layer on the first dielectric layer and the first conductive pillar by the second conductive layer. According to the method for manufacturing the circuit board, the core circuit layer and the first conductive pillar are formed by: forming a first conductive layer on the insulating plate and the hole wall of the through hole; forming on the first conductive layer a first resistive layer is formed, and a plurality of first open regions are formed in the first resistive layer to expose a portion of the first conductive layer, and a portion of the first open region corresponds to the first through the via hole and the hole end thereof a conductive layer; the core circuit layer is formed in the first opening region, and a conductive via is formed in the through hole to electrically connect the core circuit layer on both surfaces of the insulating plate; And forming a second resist layer on the core circuit layer, and forming a plurality of second open regions in the second resist layer to expose a portion of the core circuit layer; and corresponding to the electric ore in the second open regions a first conductive pillar; and removing the second resist layer, the first resist layer, and the first conductive layer covered thereby. According to the above method, the first circuit layer includes a plurality of first electrical connection pads, and the first electrical connection pads are formed on the first conductive pillar, and the first electrical connection pads are greater than, equal to or Less than the first conductive pillar. According to the above, the plurality of second conductive pillars are formed by electroplating on the first circuit layer, and the first circuit layer and the second conductive pillar are formed by the first dielectric layer and the first conductive pillar. Forming the second conductive layer on the end surface; forming a third resist layer on the second conductive layer, and forming a plurality of third open regions in the third barrier layer to expose a portion of the second conductive layer And a portion of the third open area corresponds to the second conductive layer on the end surface of the first conductive pillar; the first circuit layer is formed in the third open area, and the first circuit layer is electrically connected to the first a conductive pillar; a fourth resistive layer is formed on the first circuit layer and the third resistive layer, and a plurality of fourth open regions are formed in the fourth resistive layer to expose a portion of the first circuit layer; Forming the second conductive pillar in the fourth opening region, the second conductive pillar is electrically connected to the first circuit layer; removing the fourth resistive layer, the third resistive layer and the second conductive layer covered thereby The second conductive pillar and the first circuit layer are exposed. Forming a build-up structure on the first dielectric layer, the first circuit layer and the second conductive pillar, the build-up structure comprising at least one second dielectric layer formed on the second dielectric layer a second circuit layer, and a plurality of second conductive pillars formed in the second dielectric layer and electrically connected to the first circuit layer and the second circuit layer, the second circuit layer comprising a plurality of second electrical properties And the second electrical connection pads are formed on each of the second conductive pillars, and the second electrical connection pads are greater than, equal to, or smaller than the second conductive pillars. A plurality of electrical contact pads are formed on the second circuit layer of the outermost layer of the buildup structure, a solder resist layer is formed on the outermost layer of the buildup structure, and a plurality of anti-solder layers are formed in the solder resist layer The solder layer is opened to correspondingly expose each of the electrical contact pads. The invention provides a method for manufacturing a circuit board, which comprises: providing a through hole of 12 110821 201002166 - Ding 'with two surfaces, square M Hai insulation surface; Yu Tan 4 Wei Xiaocheng has a number of runs through two, , on the two surfaces/layers of the insulating sheets, and the core lines are formed on the opposite side of the through holes. The conductive vias, η-band k, soil, and the core θ of the two surfaces of the insulating board should be formed. % β is electrically connected to the four-pole U-line layer; the part is formed with a first-lead-lead "", and the first layer of the dielectric layer is formed on the column of the spring layer; on the layer and the brother - Conductively slotted, and the 笫-π trace+; the plurality of first-dielectric layers, the first-grooved surface and the first surface are formed in the enamel layer; and the surface is formed on the first electrical layer; Electrically formed with a second conductive straw from 6 hai - conductive layer for the first first circuit layer, and the first - (three) - electroplating formally connected to the first conductive column. The method of manufacturing the circuit board according to the above method, and the method for manufacturing the circuit board includes: "the circuit layer and the first-conducting column · 于 于 5 5 5 5 及其 及其 及其a conductive layer; formed on the first conductive layer ▲ formed with a plurality of layers of a first resist layer formed in the first layer, the first resist portion to expose a portion of the first conductive layer, a conductive layer; And the first-perforation hole around the hole end thereof is opposite to the core circuit layer of the Kuqian right province/also into the 5 hai core circuit layer on the surface; the first resistance; the second connection: the two tables of the insulation board The first R-layer and the core circuit layer have a right-hand shape, and a second circuit layer is formed in the second resist layer; and the second circuit layer is formed in the second resist layer; In the opening, the corresponding conductive layer is formed by electroplating. The first layer of the first circuit layer further comprises a second conductive pillar 110821 13 201002166, the first electrical connection being smaller than the first conductive pillar. According to the above, the complex is included in the first dielectric reed, Meng Yi holding 'two conductive columns on the shape of the ancient 4,, ^ brother, spring road layer and the first, and ancient ~ There is a build-up structure, the build-up structure includes a second dielectric layer having a slotted to +1*, and a second dielectric layer formed by the second slot, formed in the eight+^one open god and JL•穿^弟—7丨 electrical layer The first - Kai Cai (3) with the other brother's second electrical connection 〈 〈 弟 弟 于 于 于 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟The circuit layer and the second line slippery brother _ the second conductive column of the baggage connection, and the I road surface and the cousin of the first layer of the first dynasty dynasty; the surface of the bristles layer is flush, The second is not equal to or less than the mth. The 塾 大于 is larger than and is included in the outermost plurality of electrical contact 该 of the buildup structure, and a layer is formed on the layer of the buildup layer; and a plurality of solder resists are formed in the anti-tank layer Second; anti-Tan each of the electrical contact pads. The θ 4 hole can be used to correspondingly expose the circuit board of the present invention and the manufacturing method thereof, and can form an electrical connection of the road layer, and can protrude the 4 feather I column as the interlayer line 叩 大 大 知 知 由 由 由 由 由 由 由 由 由 由 由Produce film h layer to open the reliability. H check the question 'to improve the wiring density and [implementation] The following specific examples, by this #蓺 + Λ 1 month, the basics of the application, , · · "Technology Other advantages and effects of the present invention can be understood from the disclosure of the present specification. The inner valley is easy [first embodiment] Referring to the 2A to 2N drawings, the system is not in the invention. The method of manufacturing the circuit board] 1082]] 4 201 sense 02% of the schematic diagram of the section. As shown in Fig. 2A, first, 'provide a two-sheet... edge plate 20, formed in the insulating plate 2〇 a plurality of through holes 201 penetrating through the two surfaces 20a. As shown in the figure f 2B, a first conductive layer 21a is formed on the insulating plate 2 and its through hole 2; then, in the first: the first is formed a resistive layer 22a, and the first resistive layer of the first resistive layer is exposed to expose a portion of the first conductive layer (1), and ==: the green region corresponds to each of the through-holes 2G1 and the first periphery thereof: As shown in FIG. 2C, the core layer 202 of the electric ore is formed in the first opening region 22()a, and an electrical via hole is formed in the through hole 201== electrically connected to the insulating plate 2 The two core surfaces are as shown on the core line as shown in the figure below, and the first resist layer and the core circuit layer 2〇2 are opened/formed with the first resist layer 22b, and the word chu-rrn a 丄-w In the formation of the resist layer 2, a plurality of brothers are formed: the region 22Gb' is formed to expose a portion of the core circuit layer 2〇2. As shown in FIG. 2E, a first conductive pillar is formed in the second opening regions 2_ 23a, the first conductive pillars (10) are electrically connected to the core circuit layer 202. As shown in FIG. 2F, the second resistive layer is removed, and the first resist and the first moiré covered by the strip are 91. The electric layer 21a is formed to expose the core circuit layer 202 and the first conductive cymbal 23a. As shown in FIG. 2G, the insulating plate 2, the core circuit layer 2 〇 2 and the 110821 15 201002166 and the 〒 electric column 233 are formed. The first dielectric layer 2 is known as shown in FIG. 2H, and the end portions of the first conductive pillars 23a are removed from the first dielectric layer 2, and the dielectric layer 24a and the first conductive pillars are as described above. A second conductive layer 2b is formed on the end surface of the coffee cup shown in FIG. 21; a third resistive layer 22c is formed on the conductive pillar layer 21b, and a plurality of third open regions 2 are formed on the first guide. 20c, the third opening portion of the exposed layer, the middle portion corresponds to the second conductive layer 21b on each end surface. The package column 23a~ is shown in the second opening area 22〇c, as shown in FIG. 2J. a spring road layer 25a, and the first circuit layer has a plurality of pads 2 251a' such that the first f-th connections (four) ^::::: electric posts 1 and the first-electrical connections 塾=, The first conductive pillar 23a is found or smaller than the first conductive pillar 23a. The first circuit layer 25a and the third resistive layer 22c have a fourth resistive layer 22d' and a plurality of openings are formed in the fourth resistive layer_: The region 22Gd' exposes a portion of the first-line layer 25a. In the second opening region 22〇d, the electric ore is formed with an f-V electric column 23b, and the second conductive post 2 is electrically connected to the wiring layer 25a. As shown in FIG. 2M, the second conductive layer 2lb covered by the fourth resist layer 22d and the third resist layer 22c is removed to expose the second conductive bump 23b and the second wiring layer 25a. As shown in FIG. 2N, after the method of repeating the 2G to 2M, the build-up structure 26 is formed on the 110821 16 201002166 core-dielectric layer 24a, the first-line layer 25a, and the second conductive pillar. The build-up structure 26 includes at least a 'dielectric layer secret, a second circuit layer formed on the second dielectric material--and a plurality of dielectric layers (10) disposed in the second dielectric layer (10) and electrically connected to the B And the second conductive layer of the second circuit layer is smothered. The second second 252b includes a second electrical connection 塾(5)b, and the =23b is electrically connected to each of the second electrical connections. The b-number = the second circuit layer of the outermost layer of the build-up structure 26, the current electrical contact pad 264', and the outermost surface of the build-up structure 26 is soldered to the gate Π 27 , 27, and formed in the solder resist layer 27 A plurality of anti-4 layers of openings 270' are provided to correspondingly expose the respective electrical contact pads. The invention provides a circuit board comprising: an insulating plate 20, a surface 2Ga, and a plurality of surfaces penetrating through two surfaces, such as a nuclear circuit layer 2〇2, which are disposed on the surface of the insulating plate 2〇 1 忒 忒 忒 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 201 Only 23a is disposed in the first dielectric layer... and electrically charged: =0 2 ′ and the end surface of the first conductive pillar W is flush with the surface of the second 4: the second conductive layer is disposed at The first conductive layer A and the first circuit layer 25a are disposed on the first dielectric. The H circuit layer 25a has a plurality of first electrical connection pads, and the first electrical connection pads 251 compete for a, Two conductive layers, two conductive pillars, are connected to each of the first conductive pillars 130821 17 201002166
Li〇a v 依上述之電路板，該第 性逯接墊251a係大於 等於或小於該第一導電柱23a < 一八=述之結構，復包括增層結# 26，係設於該第 一"黾層24a及第—魂路声25a μ ^ $泉路廣咖上，該增層結構26係包 括有至 >、一第二介電層24b、設於該第二介電層上之 線二層25b、以及複數設於該第二介電層之中並電性連二 該第一線路層25a及第二線路層25b 它n 之弟一導電柱23b， 且“弟-相層25b復包括複數第二電性 該第二電性連接墊251b係形成於該第二導 又該第二電性連接墊腿係大於、等於或小於 電柱饥；並於該增層結構26最外層之第二㈣声1 : = : =性接觸墊264，於該增層結構…外層 層27 ’並於該防焊層27中設有複數個防焊Li〇av according to the above circuit board, the first splicing pad 251a is greater than or less than the first conductive post 23a <"黾层24a and the first-soul road sound 25a μ ^ $泉路广咖, the build-up structure 26 includes a >, a second dielectric layer 24b, is disposed on the second dielectric layer a second layer 25b of the line, and a plurality of wires disposed in the second dielectric layer and electrically connected to the first circuit layer 25a and the second circuit layer 25b, and the second conductive layer 23b, and the "dipole-phase layer" The second electrical connection pad 251b is formed on the second guide and the second electrical connection leg system is greater than, equal to, or less than the electric column; and the outermost layer of the buildup structure 26 The second (four) sound 1 : = : = sexual contact pad 264, in the build-up structure ... outer layer 27 ' and a plurality of solder resists are provided in the solder resist layer 27
盾開孔2 7 0，以料廏嘴山々A 乂對應路出各該電性接觸墊 [第二實施例] ^ 1閱帛3八至3H圖，係顯示本發明之電路板之製法 第一貫施例之剖面示音圖二 — 、 ^ ^M 刖一貫施例之不同處在於該 弟及第一線路層係分別开{占〜 中，且僅兮筮y成灰忒弟一及第二介電層 :使㈣-及弟二線路層表面 層之表面齊平。 木汉矛一；丨电 如弟3 A圖所示，挺你 該第一介♦ # % ^ —係如苐2G圖所示之結構，於 為弟’丨免層24a中形忐女…批外 之览0 小成有複數弟一開槽241a，且部份 之弟一開槽241a露出該第— V电柱23a之部份或全部端 110821 18 201002166 \m 。 :第3B圖所示，於該第一介電層…、第一開槽如& 之衣面、及弟一慕带Λ ^ 电柱23a上形成有第二導電層21b。 ^ 25^ 25la之第一線路/‘ J:形成具有第-電性連接墊 接至該第-導電枝曰23弟々了電性連接墊—電性連 於、等於或小_第 該弟—電性連接墊2513係大 ' μ乐一導電柱23a。 如第3 D及31)，闫& - ^ 化金屬層25,，如第3 :，薄化該金屬層25 ’以成為薄 路層❿及第-電：=所：；或移除未形成該第—線 層叫再於該:=5 :之金川^ 成有第三導電層2ie 示之結構作說明。 如第3E圖所示 阻層22c，且於該第 /弟一介電層24a及第一導電柱23a上形 如第3D’圖所示；之後以第3D圖所 於該薄化金屬層25,上形成有第三The shield opening is 270, and the electrical contact pad is corresponding to the material of the 廏 々 々 [ [ 第二 第二 第二 第二 第二 第二 第二 [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ 帛 帛 帛 帛 帛 帛 帛 帛 帛 帛 帛The difference between the cross-sectional diagrams of the examples and the ^^M 刖 刖 刖 刖 刖 刖 刖 刖 刖 刖 刖 刖 刖 刖 刖 刖 刖 刖 刖 刖 刖 刖 刖 刖 刖 刖 刖 刖 刖 刖 刖 刖 刖 刖 刖 刖 刖 刖 刖 刖 刖Dielectric layer: The surface of the surface layer of the (4)-and the second circuit layer is made flush. Muhan spear one; 丨电如弟3 A picture shows that you should be the first ♦ # % ^ — is the structure shown in Figure 2G, in the form of the 丨 丨 layer 24a in the form of a prostitute... The outer view 0 Xiaocheng has a plurality of slots 241a, and a part of the brother a slot 241a exposes part or all of the first-V pole 23a 110821 18 201002166 \m. : As shown in Fig. 3B, a second conductive layer 21b is formed on the first dielectric layer, the first slot, such as the <RTIgt; ^ 25^ 25la's first line / 'J: formed with a first-electrical connection pad to the first-conductive branch 23, the younger electrical connection pad - electrically connected to, equal to or small _ the younger brother - The electrical connection pad 2513 is a large 'μ Le-conductive post 23a. As in 3D and 31), yan & - metallized layer 25, as in 3: thinning the metal layer 25' to become a thin layer layer and the first - electricity: =:; or removed The formation of the first-line layer is further described by the structure of the third conductive layer 2ie. The resist layer 22c is shown in FIG. 3E, and is formed on the first dielectric layer 24a and the first conductive pillar 23a as shown in FIG. 3D'; and then the thinned metal layer 25 is shown in FIG. 3D. , formed a third
' 阻層22c中形成有複數第三開口 F 220c，以露出部份之薄化金屬層25,。 °° 如第3F圖所示，於該第三開口區22〇。中之 層25,上電鍍形成有第二導電柱2扑。 匕金屬 备如第3G圖所示，移除該第三阻層22c及其所费芸 薄化金屬層25’與第二導電層21b，以露出：皿之 25a及第—柱23b，且使該第一線路層仏與 八 電層24a之表面齊平。 ” 如第3H圖所示，之後得重覆第3A至沉圖之製程， 110821 39 201002166 矛一介電層24a、第一線路層25a、及第二導電才主 23b上形成有增層結構％，該增層結構2β係包括有至少 -一具有第二開槽241b之第二介電層24b、形成於該第二 ；介電層之第二開槽24沁中具有第二電性連接墊25比之^ .二線路層25b、以及複數形成於該第二介電層灿中並= 性連接該第一線路層25a及第二線路層咖之第二電性= 接塾251b的第二導電柱23b，又該第二線路層挪之表 面與第二介電層24b之表面齊平；該第二電性連接墊2511 ^大於、等於或小於該第二導電柱现；又於該增層結構 取外層之第二線路層25b上形成有複數電性接觸墊 2以’於該增層結構26之最外層上形成有防焊層打，並 於該防焊層27中形成有複數個防焊層開孔27〇以對應露 出各該電性接觸墊264。 本發明復提供一種電路板，係包括：絕緣板2〇，係 '、兩表面2〇a，亚設有複數貫穿兩表面之通孔201 ;核 心線路層202,係設於該絕緣板2〇之兩表面2〇a上，並 於该通孔2 01中設右逡啻、3 t 0 Λ 0 Λ ν電通孔202a以電性連接該絕緣板 兩表Φ心上之核心線路層咖；複數第一導電柱 a ’係分別设於部份之核心線路層2〇2上；第一介電層 24a ’係設於該絕緣板？ 曰 板20核心線路層202及第一導電柱 第—介電層^具有複數第-開槽_，且該 第„ :日241&亚對應露出各該第—導電柱23a之端面； 電層训，係設於該第—開槽如a之表面、及第 W柱23a上；以及第一線路層心，係設於該第一開 110821 20 201002166 倌mu中之第二導電声2 有第一電性連接墊π/，' /，且該第一線路層2“具 .1％ a以電性連接該第_導電柱23a , …亥弟-線路層25a並與第_介電層…齊平。 m边之電路板，該第_電 .等於或小於該第一導電柱仏。…云⑽大方、 述之結構，復包括於該第一 線路層25a及第—導雷妊9Q ^ 增層結構26係包括有至少=成有增層結構26，該 電層細、設於該第二開槽2仙之第二介 具有第二電性連接塾251b ^一^ 241b中之 設於該第二介電層地中並：二、f路層，、以及複數 « ^ '毛生連接5玄弟一線路声25a 及第-線路層25b之第 祕廣25a 9qk ^ ^ 包王連接塾251b的第-莫命虹 挪’又該第二線路層现之 面齊平；該第_π /、弟一"电層24b之表 乐一电性連接墊25lb並大 第二導電才主23b ;復包括於甘a 寺於或小於該 線路層25b上开增層結構26最外層之第二 9β . 成有祓數電性接觸墊264,於誃捭厚纟士拔 2 6之最外鼻卜犯少士 χ曰層、、-口構 …“ 有防焊層27,並於該防焊層27中开以 有複數個防焊層開孔27〇以 ：27中形成 264。 心、出各5亥电性接觸墊 ，發明之電路板及其製法，本發 法，能形成導雷如从* ρ 电略板及其製 桂作為層間線路層之電性遠桩二 習知藉由雷射於介電 ，而可突破 膠渣的問題，以接古 1民制及避免產生 徒回佈線密度及可靠度。 上述實施例係用以例示性說 κ原理及其功 Π0821 21 201002166 双，ΓΤΤί升用於限制本發明。杯 任何熟習此項技藝之人士均可 在不違背本發明之精神及餘 >砰及乾％下，對上述實施例進行修 改。因此本發明之權利保禮t m • 保°又靶圍，應如後述之申請專利範 ;圍所列。 【圖式簡單説明] 第1A至1G圖係為習知 圖， 電路板及其製法之剖視示意 剖視圖； 第2A至圖係為本發”路板及其製法第—實施例 ί^Ι 第3Α至3Η圖係為本發明電路板及其 剖視圖；以及 衣法弟二實施例 第3D’係為第3D圖之另一實施例剖視圖。 【主要元件符號說明】 10 核心板 101 、 202 核心線路層 102 ' 202b 導電通孔 10a' 20a 表面 12a 、 24a 第一介電層 120a 介電層開孔 12b 、 24b 弟—介電層 13 導電層 14 阻層 140 開口區 15a 、 25a 第一線路層 11082] 22 201002166 丄 id 丄 a 、 zd 1 a 第一導電盲孔 15b 、 25b 第二線路層 151b ' 251b 第二導電盲孔 ；16 ' 26 增層結構 164 、 264 電性接觸墊 17、27 防焊層 170 、 270 防焊層開孔 20 絕緣板 201 通孑L 21a 第一導電層 21b 第二導電層 21c 第三導電層 22a 第一阻層 220a 第一開口區 22b 第二阻層 220b 第二開口區 ,22c 第三阻層 220c 第三開口區 22d 第四阻層 220d 第四開口區 23a 第一導電柱 23b 第二導電柱 241a 第一開槽 241b 第二開槽 23 110821 201002166 L U 25， / 251a ；251b 金屬層 薄化金屬層 第一電性連接墊 第二電性連接墊 24 110821A plurality of third openings F 220c are formed in the resist layer 22c to expose a portion of the thinned metal layer 25. °° as shown in Fig. 3F, in the third open area 22〇. In the layer 25, the second conductive pillar 2 is formed by electroplating. The base metal is removed as shown in FIG. 3G, and the third resist layer 22c and the thinned metal layer 25' and the second conductive layer 21b are removed to expose the 25a of the dish and the pillar 23b, and The first circuit layer is flush with the surface of the eight electrical layer 24a. As shown in FIG. 3H, after the process of repeating the 3A to the sinker, the 110821 39 201002166 spear-dielectric layer 24a, the first circuit layer 25a, and the second conductive main body 23b are formed with a build-up structure%. The build-up structure 2β includes at least one second dielectric layer 24b having a second trench 241b formed in the second; the second trench 24沁 of the dielectric layer has a second electrical connection pad 25 than the second circuit layer 25b, and a plurality of second dielectric layers formed in the second dielectric layer and positively connected to the first circuit layer 25a and the second circuit layer second electrical = junction 251b second The conductive pillar 23b, and the surface of the second circuit layer is flush with the surface of the second dielectric layer 24b; the second electrical connection pad 2511^ is greater than, equal to, or smaller than the second conductive pillar; A plurality of electrical contact pads 2 are formed on the second circuit layer 25b of the outer layer of the layer structure to form a solder resist layer on the outermost layer of the buildup structure 26, and a plurality of solder resist layers are formed in the solder resist layer 27. The solder mask opening 27 is correspondingly to expose each of the electrical contact pads 264. The present invention provides a circuit board comprising: an insulating board 2 , the two surfaces 2〇a, the sub-layers are provided with a plurality of through holes 201 extending through the two surfaces; the core circuit layer 202 is disposed on the two surfaces 2〇a of the insulating plate 2, and in the through holes 2 01 The right turn, 3 t 0 Λ 0 Λ ν electrical through hole 202a is electrically connected to the core circuit layer on the two surfaces of the insulating plate; the plurality of first conductive columns a ' are respectively disposed on part of the core line The first dielectric layer 24a' is disposed on the insulating plate 曰 20 core circuit layer 202 and the first conductive pillar first-dielectric layer has a plurality of first-grooving_, and the first : the day 241 & sub-correspond to the end surface of each of the first conductive pillars 23a; the electrical layer training is provided on the surface of the first-groove such as a, and the W-pillar 23a; and the first circuit layer core, the system The second conductive sound 2 in the first opening 110821 20 201002166 倌mu has a first electrical connection pad π /, ' /, and the first circuit layer 2 "with .1% a electrically connected to the first _ The conductive column 23a, the circuit board layer 25a is flush with the first dielectric layer. The circuit board of the m side is equal to or smaller than the first conductive pillar. The cloud (10) is generous and described. structure The second circuit layer 25a and the first guide layer 9Q ^ buildup structure 26 include at least a build-up structure 26, and the electric layer is thin, and is disposed in the second slot 2 The second electrical connection 塾 251b ^ 241b is disposed in the second dielectric layer and is: two, f road layer, and a plurality of « ^ ' Maosheng connection 5 Xuandi one line sound 25a and The first line of the second line layer 25b is 25a 9qk ^ ^ The first part of the second line layer is flush with the first line of the second line layer; the first _π /, brother one " electric layer 24b of the musical-electrical connection pad 25lb and the second electrically conductive main body 23b; the second 9β which is included in the outermost layer of the layered structure 26 on or below the circuit layer 25b. Sexual contact pad 264, in the outermost nose of the thick 纟 拔 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 The solder mask opening 27 is formed at 264 in 27 . The heart, the 5th electrical contact pad, the invention of the circuit board and its manufacturing method, the present method, can form a lightning guide such as from the * ρ electric board and its made guilin as the interlayer circuit layer of the electrical far pile 2 By laser-based dielectrics, it is possible to break through the problem of glue residue, to avoid the generation of wiring density and reliability. The above embodiments are used to exemplify the κ principle and its function Π 0821 21 201002166 bis, which is used to limit the present invention. The above embodiments may be modified by anyone skilled in the art without departing from the spirit and scope of the invention. Therefore, the rights of the present invention, the protection of the m m and the target range, should be as described in the patent application form described later. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A to 1G are diagrams showing a conventional diagram, a schematic cross-sectional view of a circuit board and a method of manufacturing the same; and FIG. 2A to FIG. 2A is a "road board and a method of manufacturing the same - an embodiment ί^" 3Α至3Η图 is a circuit board of the present invention and a cross-sectional view thereof; and FIG. 3D of the second embodiment of the second embodiment is a cross-sectional view of another embodiment of the 3D figure. [Key element symbol description] 10 core board 101, 202 core line Layer 102' 202b conductive via 10a' 20a surface 12a, 24a first dielectric layer 120a dielectric layer opening 12b, 24b dielectric layer 13 conductive layer 14 resist layer 140 open region 15a, 25a first circuit layer 11082 ] 22 201002166 丄id 丄a , zd 1 a first conductive blind holes 15b , 25b second circuit layer 151b ' 251b second conductive blind hole; 16 ' 26 build-up structure 164 , 264 electrical contact pads 17 , 27 solder resist Layer 170, 270 solder mask opening 20 insulating board 201 through L 21a first conductive layer 21b second conductive layer 21c third conductive layer 22a first resistive layer 220a first open region 22b second resistive layer 220b second opening Zone, 22c third resistive layer 220c Three open areas 22d fourth resistive layer 220d fourth open area 23a first conductive pillar 23b second conductive pillar 241a first slot 241b second slot 23 110821 201002166 LU 25, / 251a ; 251b metal layer thinned metal layer An electrical connection pad, a second electrical connection pad 24 110821