200945519 九、發明說明： '【發明所屬之技術領域】 本發明係有關於-種封褒基板結構及其製法，尤指〜 種細線路之封裝基板及其製法。 【先前技術】 ’ A符合半導體封裝件㈣短小、多功能、高速度及高 頻化的開發方向’該㈣基板已朝向細線路及小孔徑發 展。.現有封裝基板製程從傳^丨⑽冑米之關鍵尺寸 ©(critical dimension) ’包括線路寬度（width)及線路間 距（pitch)等’已縮減至22微来’並且持續朝向更小的關 鍵尺寸發展。 為提间半^體晶片封裝用之封裝基板之佈線密度，業 界遂發展出-種增層技術（Built_up)，亦即在一核心板 (Core circuit board)表面利用線路増層技術交互堆疊多 層介電層及線路層。 ❹請參閱第1A至1G圖’係為習知封裝基板增層製法； 如第1A圖所示，提供一表面設有導電線路層ι〇ι之承载 層10’該導電線路層101具有複數導電線路1〇1已鱼電性 連接墊102,接著於該承載層1〇及導電線路層ι〇ι上妒 成介電層11a’且於該介電|⑴中形成複數盲孔H 以顯露該電性連接墊102;如第1B圖所示，於 11a及盲孔110a表面上形成導電層12a，接著於該導電^ 12a上形成光阻層13a，該光阻層…形成複數圖案化開 口區130a’以顯露盲孔110a中及部份之介電層上的 110687 5 200945519 :::i2a’如第1C圖所示’於該盲孔ll〇a中電鍍形成 .广孔UOa’且於該圖案化開口區驗之介電層 =成-線路層14a，且該線路層14a具有複數線路_ =性連接部U2a;如glD圖所示，移除㈣阻層. 及-所覆蓋之導電層12a，以顯露該複數線路"Η斑電 接部歐如第1E、1F圖所示’係重覆第ia圖至 (第1D圖所示之線路製程，於該介電層以上、該線路層 上形成增層結構15’其具有另一介電層爪、複數導 ❹電盲孔140b及另-線路層14b，且該線路層⑽且有複 數線路uib與電性連接部142b;如第1G圖所示，於增 層結構15最外層之介電層出上形成絕緣保護層16,且 於該絕緣保護層16中形成複數開孔16〇，以顯露最外層 之線路層14b作為電性接觸墊ι43。 惟，該電性連接墊102及電性連接部142a U2b之寬 度係大於該導電盲孔14Qa識之寬度，使同一線路層 14a’14b中之該線路141a，uib之間的間距無法縮小，各 ⑩電性連接墊102之間及各電性連接部142a，U2b之間的間 距亦…、法縮小，致使佈線密度無法提高，不利於封裝基板 之發展趨勢。 因此，如何提出一種封裝基板，以避免習知技術之佈 線空間浪費，而無法提高線路之佈線密度的缺失，實已成 爲目前業界亟待克服之課題。 【發明内容】 鑒·於上述習知技術之缺失，本發明之主要目的係提供 110687 6 200945519 -種提高線路佈局密度之細線路之封裝、 為達上述目的及其他目的土#八衣法。 封裝基板製法，係包括：提供 二揭路一種細線路之 形成導電線路’且該導電線路具有第一電性連面 承載層及該導電線路上形成第一第，j ，：層中：成盲孔，應顯露該第一電性連接部 之孔t大於該弟—電性連接部之寬度；於該第一八: 表面及該盲孔中形成導電層；於該導電層上^阻声電層 ❹該阻層形成開口區，4 Μ ν成阻層，且 虚開E該開口區對應該盲孔，且該開口Μ 度小於該盲孔之孔徑；於該開口區中之導電層 :線路層，而於該盲孔中之導電層上形成第—導電盲孔= =接該第一電性連接部與該第-線路層，且該第一電 性連接部之寬度小於該第一χ弟電 導電盲孔包覆該第一電性連接邱徑’以使該第一 m:以顯露該第-介電層及第一線路層。 ；述之衣法中，該承载層係可為絕緣板、具内声魂 路之封裝基板或多層封裝基板内部之介電材料層。 ;述之製法中，該第一線路層可具有設於第一導電 二：上電性連接部，且該第二電性連接部之寬度小 於第一導電盲孔之孔徑。 於上述之製法由^ 中’设可包括增層結構，其具有形成於 該第-介電層及該第一線路層上之至少一第二介電層、形 成於該第二介電層上之第二線路層、及形成於該第二介電 層中且電性連接該第二線路層之複數第二導電盲孔，且部 7 110687 200945519 •❹：：電盲孔電性連接該第一線路層。 •路層可具=電：::層r構為基本需求，該第-線 第二電性連接邙，而兮°以使邊第二導電盲孔包覆該 部，且該第三電性連^弟t線路層可具有第三電性連接 第二導電盲孔所包『。二可设於该第二導電盲孔上或被該 路層具有複數電性^觸^外’該增層結構最外面之第二線 護層’並於該結構上形成絕緣保 ❹孔之孔經。’生接觸塾之寬度可大於該第二導電盲 發％復提供—種細料之封裝基板 層’係至少一矣而@ 士、* υ何·承戰 電性連接部第二/電線路，且該導電線路具有第- 上.第一道"電層，係設於該承載層及導電線路 至1道•導孔，係設於該第—介電層中，並電性連接 =導第—電性連接部，且該第—電性連接部之 ❹覆；導電盲孔之孔徑，以使該第-導電盲孔包 |連接部，以及第—線路層，係設於該第-介 第二電性連接部’該第二電性連接部電性連 寸要δ玄第一導電盲孔。 依上述結構，該承載層係可為絕緣板、具内層線路之 士裝基板或多層封裝基板内部之介電材料層。 一又，該第一線路層可具有設於該第一導電盲孔上之第 :電性連接部，且該第二電性連接部之寬度可小於該第一 導電盲孔之孔徑。 110687 8 200945519 •社播1卜1於另°構’^樣中’該封裝基板復可包括增層 :?，_其八有設於該第-介電層及該第-線路層上之至少 於二/ 1層'6又於㈣二介電層上之第二線路層、及設 導電盲孔，且部份第二導電==二線路層之複數第二 ·· ^ ^ 等电盲孔電性連接該第一線路層。 「一、亡該第、線路層可具有第二電性連接部，且該第 =目孔包覆該第二電性連接部，而該第二線路層可具 -電性連接部，且該第三電性連接料於該第二導電 ❹：孔；或被第二導電盲孔所包覆。此外，該增層結構最外 ^第一線路層可具有複數電性接觸塾，且該增層結構上 邑：保濩層’其係具有複數開孔以對應顯露該電性接 觸墊’其中，該電性接觸墊之寬度大於該第二導電盲孔之 孔輕。 彳知’本發明之細線路之封裝基板及其製法 各電性連接部均為導電盲孔所包覆，且該第一線路層之第 ❹-電，連接部之寬度小於第—導電盲孔之孔徑，故，使 發月藉由上述兩個結構特徵，可避免線路佔用面積過 以達到細線路並提高線路佈設密度之目的。 【實施方式】 以下藉由特定的具體實施例說明本發明之 式’熟悉此技蟄之人士可由本說明書所揭示之内容輕易 瞭解本發明之其他優點及功效。 之細線路之 請參閱第2A至2L圖，係詳細說明本發明 封裝基板及其製法之剖面示意圖。 110687 9 200945519 力弟2A圖所示’提供-至少-表面具有複數導電線 路201之承載層20,該導電線路2〇1具有第-電性連接 部202，且於該承載層2〇及導電線路2〇1上形成第一介 電層…，並於該第一介電層叫中形成複數盲孔_， •且盲孔210a之孔控大於第一電性連接部之寬度，以 ,使盲孔21〇a對應顯露第一電性連接部202;其中，該承 =層2。係為絕緣板、具内層線路之封裝基板或多層封裝 基板内部之介電層之其中一者。 ❹ ” 2B圖所示，於該第—介電層…及盲孔咖 形成導電層22a’接著於該導電層22a上形成阻層仏， 且該阻層23a形成開口區23〇a。 電層223主要係作爲後續電錢金屬材料所需之 志机路徑’其可由金屬、合金或沉積數層金屬層所構 如選自銅、錫、鍊、鉻、欽、鋼—絡合金或錫一錯合金 所構成之群組之其中一者所組成，係以減鑛、蒸錢、盔 ❹^鍍及化學沈積之一者形成；該阻層…係例如為乾 =或液態光阻等光阻層(Phot〇resist)，其利用印刷、旋 j貼合等方式形成於該導電層仏上，再藉由曝光、顯 =方式加以圖案化’以形成圖案化開口區23〇a而顯露 ^之導電層22a，其中部份開口區23〇a對應顯露該盲 10a中之導電層22a’且該開口區2咖之寬度小於該 頁孔210a之孔徑。 如第2C圖所示，藉由該導電層22a，以於開口區23〇& 電鍍形成第-線路層241a，且於盲孔21Ga中形成第一 110687 10 200945519 :f以電性連接第—電性 電㈣接部202之寬度小於第—導電盲孔廳之孔 使得第一導電盲孔240a包覆嗲第 ^ 復”亥弟—電性連接部202。 另外，該第-線路層2仙具有第二 ^性連接第-導電盲孔24Ga，其中，該第：電性連^ 4 42a之見度小於第一導電盲孔2術之孔徑 二㈣接部⑽設於第-導電盲孔施之表面。 如$ 2D、2D，圖所示，移除該阻層 ❹導電層22a，以顯露該第一介電層…及第一= 241a。第2D’圖係以上視圖顯 、’ 曰 优圖顯不弟2D圖中虛線框中之第 :ΓΗ、第二電性連接部⑽、第-導電盲孔240a 與導電線路201及第一雪w_Λ 及弟電性連接部202之空間型態。如圖 所示，該導電線路201 #黎 天蹲之第一電性連接部2〇2為第一導電 盲孔24Ga所包覆’而該第—線路層2術之第二電性連接 部242a與第-導電盲孔24〇&相接部位僅位於第一導電盲 ❾4Ga之表φ範圍内’俾以免除習知技術之連接部位佔 用面積過大之問題。 如第2E圖至2H圖所示，重覆帛2A圖至帛2D圖所示 之線路製程’以於該第-介電層21a及第-線路層241a 上形成增層結構25，且該增層結構25具有設於第-介電 f 21&及第—線路層241a上之至少-第二介電層21b、 二於第一21b上之第二線路層241b、及設於第二 w電層21b中且電性連接第一及第二線路層24ia，24ib 之第二導電盲孔240b。 11 110687 200945519 。 二弟二線路層241b具有寬度小於第二導電盲孔裏 -之孔役之第三電性連接部242b，且部份第三電性連 242b設於第二導電盲孔240b之部份表面， 衣甶而部份第三電 '連接邛24扎被第二導電盲孔240b所包覆。 "層至2κ圖所示、’接著，於該增層結構25最 、-路層241c形成複數電性接觸塾2 電性接觸墊242c之宽产大於望-道带亡 亥 乙c之見度大於弟一導電盲孔24仆之孔徑。 如第2L圖所示’於增層結構25最外層之第二介電層 β層⑽及電性接觸墊池上形成絕緣保 顧且於該絕緣保護層26中形成複數開孔26〇，以 顯路该電性接觸墊242c。 本發明：提供一種細線路之封裝基板，係包括:承载 曰 ，於其至少一表面設有導電線路9ίΠ a - _ 加具有第一電性連接部202H=彳導電線路 承载層20 介電層21a，係設於 2〇1上；第一導電盲孔2伽，· G雷13中，並電性連接至導電線路201之第— Ο電性連接部202,哕筮乐 道+亡 μ第一電性連接部202之寬度小於第— V電盲孔240a之孔徑，以使第一 電性連接部202;以及第盲孔編包覆第一 ⑴上且電性連接第-導電盲孔240a。 層 之二該承载層2〇係為絕緣板、具内層線路 =基板或多層封裝基板内部之介電材料層。該 部242a，且第二電性J電盲孔2術上之第二電性連接 連接部242a之寬度小於第一導電盲 110687 12 200945519 • ·τυ ζαυει t 孑〇 ” 該封裝基板復包括增層結構25,其具有設於第一介 電層21a及第一線路層2仙上之至少一第二介電層 21 =、設於第二介電層21b上之第二線路層2仙，2仏、 及設於第二介電層21b t且電性連接第二線路層 ,241b，241c之複數第二導電盲孔24此，且部份第二導電盲 t孔240b電性連接第一線路層2仙。該第二導電盲孔娜 包覆第二電性連接部242a’而第二線路層漏具有第三 ❹=接部應’以設於第二導電盲孔鳩上或被第： 導電盲孔240b所包覆。 ^卜’該增層結構2巧外面之第二線路層心具有 =電丄生接觸塾242c’且該增層結構巧上設有絕緣保護 層26,其具有複數開孔26〇以對應顯露電 且電性接觸墊242c之寬度 " 見度大於弟一導電盲孔2401)之孔 徑。 參導電本發明之細線路之封裝基板及其製法，因 ίΓ你笛性連接部之寬度小於第一導電盲孔之 -:第；電性連接部為第一導電盲孔所包覆，且該第 :及第二电性連接部之寬度小於該第二導電盲孔之孔 毯’故’使本發明藉由各電性連接部設於各 面，且各導電盲孔包覆各電性連 艸施 电丨迓接冲之上述兩個結構特 徵，俾以免除線路佔用面積過大 高線路佈設密度之目的。 以以達細線路並提 上述實施例係用以例示性說明本發明之原理及其功 110687 13 200945519 ‘双π升用於限制本發明。任何熟習此項技藝之人士均可 -在不違背本發明之精神及範田壽下，對上述實施例進行修 改因此本發明之權利保護範圍，應如後述之 圍所列。 # 【圖式簡單説明】 ' _第1Α至1G圖係為習知半導體封裝基板增層製法之流 * 程示意圖；以及 第2Α至2L圖係為本發明細線路之封裝基板及其製法 ❹之剖面不意圖；其中，第2D，圖係為第2D圖之上視圖。 【主要元件符號說明】 10, 20 承載層 101 導電線路層 l〇la, 201 導電線路 102 電性連接塾 11a,lib 介電層 110a,210a 盲孔 O12a,22a 導電層 13a 光阻層 130a 圖案化開口區 14a, 14b 線路層 140a,140b 導電盲孔 141a,141b 線路 142a,142b 電性連接部 143, 242c 電性接觸墊 14 110687 200945519 i ϋ,乙 3 增層結構 16,26 絕緣保護層 160, 260 開孔 202 第一電性連接部 21a 第一介電層 r 21b 第二介電層 t 23a 阻層 230a 開口區 ^ 240a 第一導電盲孔 240b 第二導電盲孔 241a 第一線路層 242a 第二電性連接部 241b 、 241c 第二線路層 242b 第三電性連接部 ❿ 15 110687200945519 IX. Description of the invention: '[Technical field to which the invention pertains] The present invention relates to a structure of a sealed substrate and a method of manufacturing the same, and more particularly to a package substrate of a fine line and a method of manufacturing the same. [Prior Art] 'A conforms to the development direction of semiconductor package (4) short, versatile, high speed and high frequency'. (4) The substrate has been developed toward thin lines and small apertures. The existing package substrate process has been reduced from the critical dimension 'including line width and line pitch' to '22 microseconds' and continues to a smaller critical size. development of. In order to increase the wiring density of the package substrate for the semiconductor package, the industry has developed a layering technique (Built_up), that is, the layer stacking technology is used to alternately stack the multilayer dielectric on the surface of a core circuit board. Electrical layer and circuit layer. ❹Please refer to FIGS. 1A to 1G' as a conventional package substrate build-up method; as shown in FIG. 1A, a carrier layer 10 having a conductive circuit layer ι〇ι is provided on the surface, and the conductive layer 101 has a plurality of conductive layers. The circuit 1〇1 has a fish-electric connection pad 102, and then forms a dielectric layer 11a′ on the carrier layer 1〇 and the conductive layer ι〇ι and forms a plurality of blind holes H in the dielectric|(1) to reveal the Electrical connection pad 102; as shown in FIG. 1B, a conductive layer 12a is formed on the surface of 11a and the blind via 110a, and then a photoresist layer 13a is formed on the conductive layer 12a, and the photoresist layer ... forms a plurality of patterned opening regions. 130a' is formed by plating 110687 5 200945519:::i2a' on the dielectric layer of the blind via 110a and part of the dielectric layer as shown in FIG. 1C. The wide hole UOa' is formed. The patterned opening region is inspected by a dielectric layer = a wiring layer 14a, and the wiring layer 14a has a plurality of lines _ = a sexual connection portion U2a; as shown in the glD diagram, the (four) resist layer is removed. 12a, to reveal that the complex line " freckle electrical connection part of the European figure 1E, 1F shows 'repeated the ia diagram to (the line process shown in Figure 1D, Above the dielectric layer, the wiring layer is formed with a build-up structure 15' having another dielectric layer claw, a plurality of conductive electric blind holes 140b and another wiring layer 14b, and the circuit layer (10) has a plurality of lines uib and The electrical connection portion 142b; as shown in FIG. 1G, an insulating protective layer 16 is formed on the dielectric layer of the outermost layer of the build-up structure 15, and a plurality of openings 16 are formed in the insulating protective layer 16 to reveal the most The outer circuit layer 14b serves as the electrical contact pad ι43. However, the width of the electrical connection pad 102 and the electrical connection portion 142a U2b is greater than the width of the conductive via 14Qa, so that the same circuit layer 14a'14b The spacing between the lines 141a and uib cannot be reduced, and the spacing between the 10 electrical connection pads 102 and the electrical connection portions 142a and U2b is also reduced, so that the wiring density cannot be improved, which is disadvantageous for the package substrate. Therefore, how to propose a package substrate to avoid waste of wiring space of the prior art and to improve the lack of wiring density of the line has become an urgent problem to be overcome in the industry. know The main purpose of the present invention is to provide 110687 6 200945519 - a package for improving the layout density of fine lines, for the above purpose and other purposes. The method of manufacturing a package substrate includes: providing a second road a conductive line formed by a thin line and having a first electrical connection layer and a first electrode formed on the conductive line, wherein the layer is formed as a blind hole, and the first electrical connection portion should be exposed The hole t is larger than the width of the electrical connection portion; a conductive layer is formed on the surface of the first eight: and the blind hole; and the acoustic layer is formed on the conductive layer, and the resist layer forms an open area, 4 Μ ν is a resistive layer, and the open area corresponds to the blind hole, and the opening is smaller than the aperture of the blind hole; the conductive layer in the open area: the circuit layer, and the conductive layer in the blind hole Forming a first conductive hole == connecting the first electrical connection portion and the first circuit layer, and the width of the first electrical connection portion is smaller than the first electrical conductivity blind hole covering the first electric Sexually connecting the "path" to the first m: to reveal the first dielectric layer and Circuit layer. In the method of dressing, the carrier layer may be an insulating board, a package substrate having an inner acoustic circuit or a dielectric material layer inside the multilayer package substrate. In the method of manufacturing, the first circuit layer may have a first conductive connection: a power-on connection, and the second electrical connection has a width smaller than a diameter of the first conductive via. The above method can include a build-up structure having at least one second dielectric layer formed on the first dielectric layer and the first circuit layer, formed on the second dielectric layer a second circuit layer, and a plurality of second conductive blind holes formed in the second dielectric layer and electrically connected to the second circuit layer, and the portion 7 110687 200945519 • ❹:: the electric blind hole is electrically connected to the first A line layer. • The road layer may have a =::: layer r configuration as a basic requirement, the second line of the first line is electrically connected, and 兮° so that the second conductive blind hole covers the portion, and the third electrical property The circuit layer of the connection can have a third electrical connection to the second conductive blind hole. 2 may be disposed on the second conductive blind via or have a plurality of electrical contacts on the outermost layer of the outermost layer of the buildup structure and form an insulating insulating hole on the structure through. The width of the raw contact 可 can be greater than the second conductive blind hair 复 — — — 种 种 种 种 种 种 种 种 种 种 封装 封装 封装 封装 封装 封装 封装 封装 封装 封装 封装 @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ And the conductive line has a first-up. first track " electrical layer, which is disposed on the carrier layer and the conductive line to the one-way via hole, is disposed in the first dielectric layer, and is electrically connected = conductive a first electrical connection portion, and a coating of the first electrical connection portion; an aperture of the conductive blind hole, such that the first conductive padhole package|connection portion and the first circuit layer are disposed in the first The second electrical connection portion of the second electrical connection portion is electrically connected to the first conductive blind hole. According to the above structure, the carrier layer may be an insulating board, a substrate with an inner layer of a circuit or a layer of a dielectric material inside the multi-layer package substrate. The first circuit layer may have a first electrical connection portion disposed on the first conductive via hole, and the second electrical connection portion may have a smaller width than the first conductive via hole. 110687 8 200945519 • The social broadcast 1 卜 1 in another configuration 'the sample' of the package substrate may include a build-up layer: ?, _ eight of which are disposed on the first dielectric layer and the first-line layer at least The second circuit layer on the second/1 layer '6' and the (four) two dielectric layers, and the conductive blind hole, and the second conductive==two circuit layers, the second plurality··^ ^ electric blind hole The first circuit layer is electrically connected. "1. The circuit layer may have a second electrical connection portion, and the first mesh hole covers the second electrical connection portion, and the second circuit layer may have an electrical connection portion, and the The third electrical connection is coated with the second conductive ❹: hole; or covered by the second conductive blind hole. In addition, the first circuit layer of the build-up structure may have a plurality of electrical contact 塾, and the increase The layer structure is: the protective layer 'having a plurality of openings to correspondingly expose the electrical contact pad', wherein the width of the electrical contact pad is greater than the aperture of the second conductive via hole. The package substrate of the thin circuit and the electrical connection portions thereof are all covered by the conductive blind holes, and the width of the first circuit layer is smaller than the aperture of the first conductive hole, so that With the above two structural features, the purpose of the present invention can be avoided by the specific embodiment of the invention. The person can be easily disclosed by the contents of this manual. Other advantages and effects of the present invention. Please refer to Figures 2A to 2L for a detailed description of the package substrate of the present invention and a schematic diagram of the method for manufacturing the same. 110687 9 200945519 Li Di 2A shows 'provide - at least - surface has a carrier layer 20 of the plurality of conductive lines 201, the conductive line 2〇1 has a first electrical connection portion 202, and a first dielectric layer is formed on the carrier layer 2〇 and the conductive line 2〇1, and A plurality of blind holes are formed in a dielectric layer, and the hole control of the blind hole 210a is greater than the width of the first electrical connection portion, so that the blind hole 21A corresponds to the first electrical connection portion 202; The carrier layer 2 is one of an insulating board, a package substrate with an inner layer line, or a dielectric layer inside the multi-layer package substrate. 2 ” 2B shows the first dielectric layer and the blind hole coffee Forming the conductive layer 22a' then forming a resist layer on the conductive layer 22a, and the resist layer 23a forms an open region 23a. The electrical layer 223 is mainly used as a path for the subsequent electromotive metal materials. It can be composed of a metal, an alloy or a deposited metal layer such as copper, tin, chain, chromium, chin, steel-coalloy or tin. One of the group consisting of a wrong alloy is formed by one of mineral reduction, steaming, helmet plating, and chemical deposition; the resist layer is, for example, light such as dry = or liquid photoresist a resist layer (Phot〇resist) formed on the conductive layer by printing, bonding, or the like, and then patterned by exposure and display to form a patterned opening region 23〇a and revealed The conductive layer 22a, wherein a portion of the open region 23A corresponds to the conductive layer 22a' in the blind 10a and the width of the open region 2 is smaller than the aperture of the page hole 210a. As shown in FIG. 2C, the conductive layer 22a is used to form the first wiring layer 241a in the opening region 23〇& and the first 110687 10 200945519 :f is formed in the blind via 21Ga to electrically connect the first layer. The width of the electrical (four) contact portion 202 is smaller than the hole of the first conductive blind hole chamber such that the first conductive blind hole 240a is covered with the first electrical connection portion 202. In addition, the first circuit layer 2 The second conductive connection-conducting blind hole 24Ga, wherein the visibility of the first electrical connection 44 4a is smaller than the aperture of the first conductive blind hole 2 (four) junction (10) is provided in the first conductive blind hole The surface of the resistive layer 22a is removed as shown in FIG. 2D, 2D, to expose the first dielectric layer... and the first = 241a. The 2D' image is shown above, '曰优The figure shows the spatial pattern of the 虚线, the second electrical connection (10), the first conductive via 240a and the conductive line 201, and the first snow w_Λ and the electrical connection 202. As shown in the figure, the first electrical connection portion 2〇2 of the conductive line 201 is the first conductive blind hole 24Ga, and the first circuit layer 2 is the first The contact portion of the second electrical connection portion 242a and the first conductive via hole 24〇& is only located within the range φ of the first conductive blind ❾ 4Ga 俾 to avoid the problem that the occupied area of the connection portion of the prior art is excessively large. As shown in FIG. 2H, the wiring process shown in FIG. 2A to FIG. 2D is repeated to form a build-up structure 25 on the first dielectric layer 21a and the first-line layer 241a, and the build-up structure 25 is formed. Having at least a second dielectric layer 21b disposed on the first dielectric f 21 & and the first wiring layer 241a, a second wiring layer 241b disposed on the first 21b, and a second dummy layer 21b And electrically connecting the second conductive blind holes 240b of the first and second circuit layers 24ia, 24ib. 11 110687 200945519. The second circuit layer 241b has a width smaller than that of the second conductive blind hole - the third electrical property of the hole The connecting portion 242b, and a portion of the third electrical connection 242b is disposed on a portion of the surface of the second conductive blind via 240b, and a portion of the third electrical connection 245 is covered by the second conductive via 240b. "layer to 2κ map, 'Next, in the layering structure 25, the road layer 241c forms a plurality of electrical contacts 塾 2 electrical contact pads 2 The wide yield of 42c is greater than that of the see-the-band with the death of the sea. The visibility of the hole is greater than that of the younger one. The second dielectric layer of the second layer of the layered structure 25 is shown in Figure 2L (10). An insulating layer is formed on the electrical contact pad and a plurality of openings 26 形成 are formed in the insulating protective layer 26 to expose the electrical contact pad 242c. The present invention provides a package substrate for a fine circuit, including:曰, at least one surface thereof is provided with a conductive line 9 Π a - _ with a first electrical connection portion 202H = 彳 conductive line carrying layer 20 dielectric layer 21a, is set on 2 〇 1; first conductive blind hole 2 The gamma, G th 13 is electrically connected to the first electrical connection portion 202 of the conductive line 201, and the width of the first electrical connection portion 202 of the 哕筮乐道+死μ is smaller than the first-four electric blind hole 240a. The aperture is such that the first electrical connection portion 202; and the blind via are wrapped on the first (1) and electrically connected to the first conductive via 240a. The second layer of the carrier layer 2 is an insulating board, with an inner layer line = a substrate or a dielectric material layer inside the multilayer package substrate. The portion 242a, and the second electrical connection portion 242a of the second electrical J electric blind hole 2 has a width smaller than the first conductive blind 110687 12 200945519 • · τυ ζαυει t 孑〇 The structure 25 has at least one second dielectric layer 21 disposed on the first dielectric layer 21a and the first wiring layer 2, and a second wiring layer 2, 2 disposed on the second dielectric layer 21b. And a plurality of second conductive vias 24 electrically connected to the second dielectric layer 21b and electrically connected to the second circuit layer, 241b, 241c, and a portion of the second conductive blind via 240b electrically connected to the first line The second conductive blind hole covers the second electrical connection portion 242a' and the second circuit layer drain has a third ❹=junction portion to be disposed on the second conductive blind hole 或 or by: The conductive blind hole 240b is covered. The second circuit layer core of the build-up structure 2 has an electric contact contact 242c' and the build-up structure is provided with an insulating protective layer 26 having a plurality of The opening 26 〇 is corresponding to the aperture of the exposed electric and the electrical contact pad 242c has a larger aperture than the diameter of the conductive blind hole 2401. The package substrate of the thin line and the method for manufacturing the same, because the width of the flute joint is smaller than that of the first conductive blind hole: the first; the electrical connection is covered by the first conductive blind hole, and the first: The width of the second electrical connection portion is smaller than that of the second conductive blind hole. Therefore, the present invention is provided on each surface by each electrical connection portion, and each conductive blind hole covers each electrical connection. The above two structural features are connected to avoid the purpose of excessive line occupancy and high line layout density. The above embodiments are used to illustrate the principle and function of the present invention 110687 13 200945519 'Double π liters are used to limit the invention. Anyone skilled in the art can modify the above embodiments without departing from the spirit of the invention and Fan Tianshou. Therefore, the scope of protection of the present invention should be as described later. Listed in the following. # [Simple description of the diagram] ' _1Α to 1G diagram is a flow chart of the conventional semiconductor package substrate layering method; and the second to 2L diagrams are the package substrate of the thin line of the invention And its method 2D, the diagram is the top view of the 2D diagram. [Main component symbol description] 10, 20 carrier layer 101 conductive circuit layer l〇la, 201 conductive circuit 102 electrical connection 塾11a, lib dielectric Layers 110a, 210a blind holes O12a, 22a conductive layer 13a photoresist layer 130a patterned opening regions 14a, 14b circuit layers 140a, 140b conductive blind holes 141a, 141b lines 142a, 142b electrical connections 143, 242c electrical contact pads 14 110687 200945519 i ϋ, B 3 build-up structure 16, 26 insulation protective layer 160, 260 opening 202 first electrical connection 21a first dielectric layer r 21b second dielectric layer t 23a resist layer 230a open area ^ 240a First conductive blind hole 240b second conductive blind hole 241a first circuit layer 242a second electrical connection portion 241b, 241c second circuit layer 242b third electrical connection portion 110 15 110687