TWI401006B - Printed circuit board and fabrication method thereof - Google Patents

Description

Circuit board and its manufacturing method

The invention relates to a circuit board and a manufacturing method thereof, in particular to an electrical connection structure of an interlayer circuit layer of a circuit board and a manufacturing method thereof.

With the rapid development of the electronics industry, electronic products have gradually entered the direction of multi-functional, high-performance research and development. In order to meet the packaging requirements of semiconductor package high integration and miniaturization, the package substrate carrying semiconductor wafers has gradually evolved from a double-layer board to a multi-layer board, which is limited to a limited space. Next, an interlayer connection technology (Interlayer Connection) is used to expand the available circuit area on the package substrate to meet the demand for the use of a high electron density integrated circuit; for this reason, a buildup technique has been developed ( Build-up), that is, a plurality of dielectric layers and circuit layers are alternately stacked on the surface of a core circuit board by a line build-up technique, and a conductive via is provided in the dielectric layer for The upper and lower lines are electrically connected.

In order to meet the computational needs of high-performance chips such as microprocessors, chipsets, graphics chips, and special application integrated circuits (ASICs), semiconductor package substrates with lines need to be upgraded to transmit chip signals, improve bandwidth, control impedance, etc. Function to meet the development of high I/O number package; and in order to meet the development direction of semiconductor package light, short, multi-function, high speed, high line density and high frequency, the package substrate has been developed towards fine lines and small apertures. Existing semiconductor package substrate process has been reduced from the traditional 100 micron line size Up to now, 30 micrometers or less, including line width and space, continue to be developed toward smaller line accuracy.

Referring to FIGS. 1A to 1G, a conventional package substrate is shown. As shown in FIG. 1A, a core board 10 is provided. The core board 10 has two opposite surfaces 10a, and the surface 10a is formed on the surface 10a. a core circuit layer 101, and a conductive via 102 is formed in the core board 10 to electrically connect the core circuit layer 101 of the surface 10a of the core board 10; as shown in FIG. 1B, on the surface 10a of the core board 10 A first dielectric layer 12a is formed on the core circuit layer 101, and a plurality of dielectric layer openings 120a are formed in the first dielectric layer 12a to expose a portion of the core circuit layer 101; As shown in the figure, a conductive layer 13 is formed on the surface of the first dielectric layer 12a and the dielectric layer opening 120a, and a resist layer 14 is formed on the conductive layer 13, and the resist layer 14 is formed. An open area 140 is formed to expose a portion of the surface of the conductive layer 13, and a portion of the open area 140 corresponds to each of the dielectric layer openings 120a; as shown in FIG. 1D, in the open area 140 of the resist layer 14. a first circuit layer 15a is formed on the conductive layer 13 and a first conductive layer is formed in the dielectric layer opening 120a of the first dielectric layer 12a. The blind hole 151a is electrically connected to the core circuit layer 101; as shown in FIG. 1E, the resist layer 14 and the conductive layer 13 covered thereon are removed to expose the first circuit layer 15a; as shown in FIG. As shown in the first circuit layer 15a and the first dielectric layer 12a, a build-up structure 16 is formed. The build-up structure 16 includes at least one second dielectric layer 12b formed on the second dielectric layer. a second circuit layer 15b thereon, and a plurality of layers formed in the third dielectric layer and electrically The second conductive via 151b is electrically connected to the second conductive layer 151b, wherein a portion of the second conductive via 151b is electrically connected to the first circuit layer 15a; as shown in FIG. 1G, at the outermost layer of the buildup structure 16 The second circuit layer 15b is formed with a plurality of electrical contact pads 164, and a solder resist layer 17 is formed on the outermost layer of the buildup structure 16, and a plurality of solder mask openings are formed in the solder resist layer 17. 170 to expose each of the electrical contact pads 164.

Moreover, the dielectric layer opening 120a formed by the laser drilling is a small outer tapered hole, and a molten metal is formed at the bottom of the tapered hole, so that the dielectric layer opening 120a The bonding between the surface of the hole wall, the core circuit layer 101 in the dielectric layer opening 120a and the conductive layer 13 is not good, and the process of Desmear must be performed first, and then the line is formed; The process may not completely remove the slag, and the smaller the pore size of the tapered hole, the greater the influence of the slag on the subsequent re-formation of the line; further, the dielectric layer opening 120a reveals the core circuit layer. The bottom of the 101 has a small diameter, thereby reducing the contact area between the first conductive via 151a and the core wiring layer 101, so that the bonding between the first conductive via 151a and the core wiring layer 101 is reduced, thereby affecting electrical properties. The reliability of the connection.

Moreover, the precision of each of the laser drilling holes and the aperture of the opening hole are limited, and cannot be continuously reduced, thereby affecting the use requirements of the high-density wiring, which hinders the improvement of the fine line process capability.

Therefore, how to improve the bonding strength between the conductive blind vias formed in the openings of the dielectric layer and the lines electrically connected thereto, and to reduce the aperture of the dielectric layer openings to increase the wiring density, there is still a technical bottleneck get over.

In view of the above-discussed shortcomings of the prior art, the main object of the present invention is to provide a circuit board and a method of manufacturing the same that can increase the speed at which openings are formed.

Another object of the present invention is to provide a circuit board and a method of manufacturing the same that can improve the bonding strength between a conductive post formed in an opening of the dielectric layer and a line electrically connected thereto.

Still another object of the present invention is to provide a circuit board and a method of fabricating the same that can reduce the aperture of the opening of the dielectric layer to increase the wiring density.

In order to achieve the above and other objects, the present invention discloses a circuit board comprising: a core board having opposite surfaces, having a core circuit layer on the surface; a first dielectric layer disposed on the core board; a circuit layer is disposed on the first dielectric layer, and a conductive via hole is disposed in the first dielectric layer to electrically connect the core circuit layer; the second dielectric layer is disposed on the first dielectric layer a dielectric layer and a first circuit layer; a plurality of first conductive pillars are disposed in the second dielectric layer, and electrically connected to the first circuit layer, and the end surface of the first conductive pillar and the second dielectric layer The surface of the electrical layer is flush; and the second circuit layer is disposed on the second dielectric layer and has a plurality of electrical connection pads for electrically connecting to the first conductive pillars.

According to the above circuit board, the core board has conductive through holes for electrically connecting the core circuit layers on both surfaces of the core board; the electrical connection pads are greater than, equal to, or smaller than the first conductive pillars.

According to the above structure, the multi-layer structure is provided on the second dielectric layer and the second circuit layer, and the build-up structure includes at least one third dielectric layer disposed on the third dielectric layer. a third circuit layer thereon, and a plurality of second dielectric layers disposed in the third dielectric layer and electrically connected to the second and third circuit layers a conductive pillar, the third circuit layer further comprising a plurality of electrical connection pads, wherein the electrical connection pads are formed on the second conductive pillar, and the electrical connection pads are greater than, equal to, or smaller than the second conductive pillar .

According to the above, the plurality of electrical contact pads are disposed on the third circuit layer of the outermost layer of the buildup structure, and a solder resist layer is disposed on the outermost layer of the buildup structure, and in the solder resist layer A plurality of solder mask openings are provided to correspondingly expose the respective electrical contact pads.

The circuit board of the present invention comprises: a core board having opposite surfaces, having a core circuit layer on the surface; a first dielectric layer disposed on the core board; and a first circuit layer disposed on the core layer The first dielectric layer is flush with the first dielectric layer, and the first circuit layer has a plurality of first conductive holes electrically connected to the core circuit layer; the plurality of first conductive pillars are disposed on The first circuit layer; and the build-up structure is disposed on the first dielectric layer, the first circuit layer, and the first conductive pillar, the build-up structure has a second circuit layer, and the second circuit The layer has a plurality of electrical connection pads correspondingly disposed on each of the first conductive pillars.

According to the above circuit board, the core board is provided with a conductive through hole for electrically connecting the core circuit layer on both surfaces of the core board; the first dielectric layer is provided with a plurality of first openings and a first slot. And the first opening is exposed in the core circuit layer, the first circuit layer is disposed in the first slot, and has a first conductive hole disposed in each of the first openings to be electrically connected Up to the core circuit layer, and the electrical connection pad is greater than, equal to, or smaller than the first conductive pillar.

According to the above structure, the build-up structure includes at least one second dielectric layer having a second slit, and a second dielectric layer disposed in the second dielectric layer a second circuit layer, and a plurality of second conductive pillars disposed in the second dielectric layer and electrically connected to the second circuit layer, wherein a surface of the second circuit layer is flush with a surface of the second dielectric layer, The second circuit layer further includes a plurality of electrical connection pads, and the electrical connection pads are correspondingly disposed on the second conductive pillars, and the electrical connection pads are greater than, equal to, or smaller than the second conductive pillars.

According to the above, the electrical contact pad comprises a second circuit layer disposed on the outermost layer of the build-up structure, and a solder resist layer is disposed on the outermost layer of the build-up structure, and a plurality of solder resist layers are provided. Holes to correspondingly expose each of the electrical contact pads.

The invention provides a method for manufacturing a circuit board, comprising: providing a core board having opposite surfaces, having a core circuit layer on the surface; forming a first dielectric layer on the core board; a first circuit layer is formed on a dielectric layer, and a conductive via hole is formed in the first dielectric layer to electrically connect the core circuit layer; and a first layer is formed on the first circuit layer. a conductive pillar; a second dielectric layer is formed on the first dielectric layer, the first wiring layer and the first conductive pillar; and a portion of the second dielectric layer is removed to expose an end surface of the first conductive pillar; a second conductive layer is formed on an end surface of the second dielectric layer and the conductive pillar; a third resist layer is formed on the second conductive layer, and a plurality of third open regions are formed in the third resistive layer, a portion of the second conductive layer is exposed, and a portion of the third open region corresponds to the second conductive layer on the end surface of the first conductive pillar; and a plurality of electrical connection pads are formed in the third open region a second circuit layer, the electrical connection pads are electrically connected to each of the first conductive columns; And the third barrier layer and the second conductive layer is covered removed.

According to the manufacturing method of the above circuit board, a conductive via hole is formed in the core board to Electrically connecting the core circuit layers on both surfaces of the core board.

According to the above method, the first circuit layer and the first conductive pillar are formed by: forming a plurality of blind holes in the first dielectric layer to expose a portion of the core circuit layer; a first conductive layer is formed on the electrical layer, the hole wall of the blind hole, and a portion of the core circuit layer; a first resist layer is formed on the first conductive layer, and a first opening is formed in the first resist layer a portion of the first conductive layer is exposed, and a portion of the first opening region corresponds to the first conductive layer around the blind hole and the hole end thereof; a first circuit layer is formed in the first opening region, and a conductive via hole is formed in the blind via to electrically connect the core circuit layer; a second resist layer is formed on the first resist layer and the first circuit layer, and a second open region is formed in the second resist layer And exposing a portion of the first circuit layer; forming a first conductive pillar in the second opening region; and removing the second resist layer, the first resist layer and the first conductive layer covered thereby.

Forming a build-up structure on the second dielectric layer and the second circuit layer, the build-up structure comprising at least one third dielectric layer, and a third circuit layer formed on the third dielectric layer And a plurality of second conductive pillars formed in the third dielectric layer and electrically connected to the second and third circuit layers, wherein the third circuit layer further comprises a plurality of electrical connection pads, and the plurality of electrical The connection pads are formed on each of the second conductive pillars, and the electrical connection pads are greater than, equal to, or smaller than the second conductive pillars.

The third circuit layer further including the outermost layer of the buildup structure is formed with a plurality of electrical contact pads, a solder resist layer is formed on the outermost layer of the buildup structure, and a plurality of solder resists are formed in the solder resist layer Layer openings to correspondingly expose each The electrical contact pad.

The invention provides a method for manufacturing a circuit board, comprising: providing a core board having opposite surfaces, having a core circuit layer on the surface; forming a first dielectric layer on the core board; a first circuit layer is formed in a dielectric layer, and the first circuit layer is flush with the surface of the first dielectric layer, and a first conductive hole is formed in the first dielectric layer to electrically connect to the first conductive layer. a core circuit layer; a first conductive pillar is formed on a portion of the first circuit layer; and a buildup layer is formed on the first dielectric layer, the first circuit layer, and the first conductive pillar, the buildup layer A second circuit layer is formed in the structure, and the second circuit layer has a plurality of electrical connection pads correspondingly formed on each of the first conductive pillars.

According to the manufacturing method of the above circuit board, a conductive via hole is formed in the core board to electrically connect the core circuit layer on both surfaces of the core board.

According to the above method, the build-up structure includes at least one second dielectric layer having a second trench, a second circuit layer formed in the second trench of the second dielectric layer, and a plurality of The second dielectric layer is electrically connected to the second conductive pillar of the second circuit layer, and the surface of the second circuit layer is flush with the surface of the second dielectric layer, and the second circuit layer includes a plurality of The electrical connection pads are formed on each of the second conductive pillars, and the electrical connection pads are greater than, equal to, or smaller than the second conductive pillars.

The second circuit layer further including the outermost layer of the buildup structure is formed with a plurality of electrical contact pads, a solder resist layer is formed on the outermost layer of the buildup structure, and a plurality of solder resists are formed in the solder resist layer The layers are apertured to correspondingly expose each of the electrical contact pads.

The circuit board of the invention and the method for manufacturing the same can form the conductive column as the electrical connection of the interlayer circuit layer, and can break through the problem of the aperture limitation of the opening by the laser in the dielectric layer and avoiding the problem of generating the glue. Improve wiring density and reliability.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

[First Embodiment]

Referring to Figures 2A through 2M, there are shown cross-sectional views showing a first embodiment of the method of fabricating the circuit board of the present invention.

As shown in FIG. 2A, a core board 20 is provided, which has two opposite surfaces 20a. The surface 20a has a core circuit layer 201, and the core board 20 has a conductive via 202 therein to electrically connect the core. The core circuit layer 201 on both surfaces 20a of the board 20.

As shown in FIG. 2B, a first dielectric layer 21a is formed on the core board 20, and a plurality of blind holes 210a are formed in the first dielectric layer 21a to expose a portion of the core circuit layer 201.

As shown in FIG. 2C, a first conductive layer 22a is formed on the first dielectric layer 21a, the hole wall of the blind via 210a, and a portion of the core wiring layer 201; thereafter, on the first conductive layer 22a. a first resistive layer 23a is formed, and a first open region 230a is formed in the first resistive layer 23a to expose a portion of the first conductive layer 22a, and a portion of the first open region 230a corresponds to the blind via 210a and a first conductive layer 22a around the end of the hole.

As shown in FIG. 2D, a first wiring layer 24a is formed in the first opening region 230a, and a conductive blind hole 241a is formed in the blind hole 210a to be electrically connected to the core wiring layer 201.

As shown in FIG. 2E, a second resist layer 23b is formed on the first resist layer 23a, and a plurality of second open regions 230b are rapidly formed in the second resist layer 23b by exposure development to expose portions. The first circuit layer 24a.

As shown in FIG. 2F, the first conductive layer 22a and the first circuit layer 24a are used as a current conduction path, and the first conductive pillar 25a is plated in the second opening region 230b to make the first conductive pillar. 25a is formed on the first wiring layer 24a.

As shown in FIG. 2G, the second resist layer 23b, the first resist layer 23a and the first conductive layer 22a covered thereon are removed to expose the first wiring layer 24a and the first conductive pillar 25a.

As shown in FIG. 2H, a second dielectric layer 21b is formed on the first dielectric layer 21a, the first wiring layer 24a, and the first conductive pillar 25a.

As shown in FIG. 2I, a portion of the second dielectric layer 21b is removed by brushing to expose the end surface 251a of the first conductive pillar 25a.

As shown in FIG. 2J, a second conductive layer 22b is formed on the second dielectric layer 21b and the end surface 251a of the first conductive pillar 25a. Then, a third resist layer 23c is formed on the second conductive layer 22b. And a plurality of third opening regions 230c are formed in the third resist layer 23c to expose a portion of the second conductive layer 22b, and a portion of the third opening region 230c corresponds to the end surface 251a of the first conductive pillar 25a. The second conductive layer 22b.

As shown in FIG. 2K, the formation in the third opening region 230c has a complex The second circuit layer 24b of the electrical connection pads 242b, 242b', 242b", and the electrical connection pads 242b, 242b', 242b" are located on the first conductive pillar 25a, the electrical connection pads 242b, 242b' , 242b" is greater than, equal to, or less than the first conductive pillar 25a.

As shown in FIG. 2L, the third resist layer 23c and the second conductive layer 22b covered thereby are removed to expose the second wiring layer 24b.

As shown in FIG. 2M, a build-up structure 26 is formed on the second dielectric layer 21b and the second circuit layer 24b. The build-up structure 26 includes at least one third dielectric layer 21c formed on the second dielectric layer 21b. a third circuit layer 24c on the three dielectric layers, and a plurality of second conductive pillars 25b formed in the third dielectric layer and electrically connected to the third wiring layer, wherein a portion of the second conductive pillars 25b are electrically The second circuit layer 24b is connected to the second circuit layer 24b. The third circuit layer 24c includes a plurality of electrical connection pads 242c. The electrical connection pads 242c are formed on the second conductive pillars 25b. The electrical connection pads 242c are larger than A plurality of electrical contact pads 264 are formed on the third circuit layer 24c of the outermost layer of the build-up structure 26, and solder resists are formed on the outermost layer of the build-up structure 26, and are equal to or smaller than the second conductive pillars 25b. The layer 27 is formed with a plurality of solder mask openings 270 in the solder resist layer 27 to correspondingly expose the respective electrical contact pads 264.

The present invention provides a circuit board comprising: a core board 20 having opposing surfaces 20a, the surface 20a having a core circuit layer 201; a first dielectric layer 21a disposed on the core board 20; A circuit layer 24a is disposed on the first dielectric layer 21a, and a conductive via hole 241a is disposed in the first dielectric layer 21a to electrically connect the core circuit layer The second dielectric layer 21b is disposed on the first dielectric layer 21a and the first circuit layer 24a; the plurality of first conductive pillars 25a are disposed in the second dielectric layer 21b and electrically connected The first circuit layer 24a, and the end surface 251a of the first conductive pillar 25a is flush with the surface of the second dielectric layer 21b; the second circuit layer 24b is disposed on the second dielectric layer 21b and has a plurality of The electrical connection pads 242b, 242b', 242b" are electrically connected to the first conductive pillars 25a.

According to the above circuit board, the core board 20 has conductive vias 202 electrically connected to the core circuit layer 201 on the two surfaces 20a of the core board 20; and a build-up structure 26 is disposed on the second dielectric On the layer 21b and the second circuit layer 24b, the build-up structure 26 includes at least one third dielectric layer 21c, a third circuit layer 24c formed on the third dielectric layer, and a plurality formed on the third layer The second conductive pillars 25b of the third circuit layer are electrically connected to the dielectric layer, and a portion of the second conductive pillars 25b are electrically connected to the second circuit layer 24b. The third circuit layer 24c includes a plurality of electrical circuits. The connection pad 242c is formed on the second conductive post 25b. The electrical connection pad 242c is greater than, equal to, or smaller than the second conductive post 25b, and the buildup structure 26 is the most The third circuit layer 24c of the outer layer is formed with a plurality of electrical contact pads 264, and a solder resist layer 27 is formed on the outermost layer of the buildup structure 26, and a plurality of solder resist layers are formed in the solder resist layer 27. The holes 270 are correspondingly exposed to the respective electrical contact pads 264.

[Second embodiment]

Referring to Figures 3A to 3P, there are shown schematic cross-sectional views showing a second embodiment of the method of fabricating the circuit board of the present invention.

As shown in Fig. 3A, a structure as shown in Fig. 2A is provided.

As shown in FIG. 3B, a first dielectric layer 21a is formed on the core plate 20, and a plurality of first openings 211a and first slots 212a are formed in the first dielectric layer 21a, and the first An opening 211a exposes a portion of the core wiring layer 201.

As shown in FIG. 3C, a first conductive layer 22a is formed on the first dielectric layer 21a, the first opening 211a, and the first opening 212a, and a portion of the core wiring layer 201.

As shown in FIG. 3D, a first metal layer 241 is formed on the first conductive layer 22a, and a first circuit layer 24a is formed in the first trench 212a, and is formed in the first opening 211a. There is a first conductive hole 241b.

As shown in FIGS. 3E and 3E', the first metal layer 241 is thinned to become the first thinned metal layer 241' as shown in FIG. 3E; or the first wiring layer 24a is not completely removed and a first metal layer 241 of the first conductive via 241b and a first conductive layer 22a covered by the first metal layer to expose the first circuit layer 24a and the first conductive via 241b, and then the first dielectric layer Another conductive layer 22a' is formed on the first wiring layer 24a and the first conductive via 241b as shown in FIG. 3E'; and the structure shown in FIG. 3E will be described later.

As shown in FIG. 3F, a first resist layer 23a is formed on the first thinned metal layer 241', and a plurality of first open regions 230a are formed in the first resist layer 23a to correspond to the exposed portions. The first thinned metal layer 241'.

As shown in Fig. 3G, a first conductive pillar 25a is plated on the first thinned metal layer 241' in the first opening region 230a.

As shown in FIG. 3H, the first resistive layer 23a and the first thinned metal layer 241' and the first conductive layer 22a covered thereon are removed to expose the first wiring layer 24a, and the first line is removed. a protrusion 240 protruding from the surface of the first dielectric layer 21a is formed on the layer 24a, and the first conductive pillar 25a is disposed on the protrusion 240; if the subsequent process is performed in the 3E' diagram, the first The wiring layer 24a is flush with the surface of the first dielectric layer 21a.

As shown in FIG. 3I, a second dielectric layer 21b is formed on the first dielectric layer 21a, the first wiring layer 24a, and the first conductive pillar 25a, and the second dielectric layer 21b is formed in the second dielectric layer 21b. The plurality of second slots 211b are exposed, and the second slots 211b expose the end faces 251a of the first conductive posts 25a.

As shown in FIG. 3J, a second conductive layer 22b is formed on the second dielectric layer 21b, the hole wall of the second slit 211b, and the end surface 251a of the first conductive post 25a.

As shown in FIG. 3K, a second metal layer 242 is formed on the second conductive layer 22b, and a second line having a plurality of electrical connection pads 242b, 242b', 242b" is formed in the second trench 211b. The layer 24b, and the electrical connection pads 242b, 242b', 242b" are located on the first conductive pillar 25a, and the electrical connection pads 242b, 242b', 242b" are greater than, equal to, or smaller than the first conductive pillar 25a.

As shown in FIGS. 3L and 3L', the second metal layer 242 is thinned to become the second thinned metal layer 242' as shown in FIG. 3L; or the second wiring layer 24b is not formed and removed. After the second metal layer 242 and the second conductive layer 22b of the connection pads 242b, 242b', 242b", the second dielectric layer 21b, the second circuit layer 24b, and the electrical connection pads 242b, 242b', 242b" Another conductive layer 22b' is formed thereon as shown in Fig. 3L'; the structure shown in Fig. 3L will be described later.

As shown in FIG. 3M, a second resist layer 23b is formed on the second thinned metal layer 242', and a plurality of second open regions 230b are formed in the second resist layer 23b to expose the portion Two thinned metal layers 242'.

As shown in FIG. 3N, a second conductive pillar 25b is formed in the second opening region 230b.

As shown in Fig. 30, the second resist layer 23b and the second thinned metal layer 242' and the second conductive layer 22b covered are removed to expose the second wiring layer 24b and the second conductive pillar 25b.

As shown in FIG. 3P, the processes of FIGS. 3I to 30 are repeated to form a build-up structure 26, the build-up structure 26 including at least one second dielectric layer 21b having a second slit 211b, a second circuit layer 24b formed in the second trench 211b of the second dielectric layer, and a plurality of second conductive pillars 25b formed in the second dielectric layer and electrically connected to the second wiring layer 24b, The surface of the second circuit layer 24b is flush with the surface of the second dielectric layer 21b; the second circuit layer 24b of the outermost layer of the buildup structure 26 is formed with a plurality of electrical contact pads 264, and the build-up structure A solder resist layer 27 is formed on the outermost layer of 26, and a plurality of solder resist layer openings 270 are formed in the solder resist layer 27 to correspondingly expose the respective electrical contact pads 264.

The present invention provides a circuit board comprising: a core board 20 having opposite surface 20a, the surface 20a having a core circuit layer 201; a first dielectric layer 21a is disposed on the core board 20, and a plurality of first openings 211a and first slots 212a are provided, and the first openings 211a An exposed portion of the core circuit layer 201; the first circuit layer 24a is disposed in the first slot 212a, and has a plurality of first conductive holes 241b, and correspondingly disposed in each of the first openings 211a, Connected to the core circuit layer 201, the surface of the first circuit layer 24a is flush with the surface of the first dielectric layer 21a, or the first circuit layer 24a has a convex surface protruding from the surface of the first dielectric layer 21a. The first conductive pillar 25a is disposed on the first circuit layer 24a or the convex portion 240; and the build-up structure 26 is disposed on the first dielectric layer 21a, the first circuit layer 24a, and the first On a conductive pillar 25a, the build-up structure 26 has a second circuit layer 24b, and the second circuit layer 24b has a plurality of electrical connection pads 242b, 242b', 242b" correspondingly disposed on each of the first conductive pillars. 25a.

According to the above circuit board, the core board 20 is provided with conductive vias 202 for electrically connecting the core circuit layers 201 on the two surfaces 20a of the core board 20.

According to the above structure, the electrical connection pad 242b is greater than, equal to, or smaller than the first conductive pillar 25a.

In addition, the build-up structure 26 includes at least one second dielectric layer 21b having a second recess 211b and a second line disposed in the second trench 211b of the second dielectric layer 21b. a layer 24b, and a plurality of second conductive pillars 25b disposed in the second dielectric layer 21b and electrically connected to the second wiring layer 24b, and a surface of the second wiring layer 24b and a surface of the second dielectric layer 21b The second circuit layer 24b further includes a plurality of electrical connection pads 242b, and the electrical connection pads 242b are correspondingly disposed on the second conductive posts 25b; and the electrical connection pads 242b are greater than Equal to or less than The second conductive pillar 25b; the second circuit layer 24b of the outermost layer of the build-up structure 26 is provided with an electrical contact pad 264, and a solder resist layer 27 is disposed on the outermost layer of the build-up structure 26, and The solder resist layer 27 is provided with a plurality of solder mask openings 270 to correspondingly expose the respective electrical contact pads 264.

The circuit board of the invention and the method for manufacturing the same can form the conductive column as the electrical connection of the interlayer circuit layer, and can break through the problem of the aperture limitation of the opening by the laser in the dielectric layer and avoiding the problem of generating the glue. Improve wiring density and reliability.

The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

10, 20‧‧‧ core board

10a, 20a‧‧‧ surface

101, 201‧‧‧ core circuit layer

102, 202‧‧‧ conductive through holes

12a, 21a‧‧‧ first dielectric layer

12b, 21b‧‧‧ second dielectric layer

120a‧‧‧Dielectric layer opening

13‧‧‧ Conductive layer

14‧‧‧Resist layer

140‧‧‧Open area

15a, 24a‧‧‧ first line layer

151a‧‧‧First conductive blind hole

15b, 24b‧‧‧second circuit layer

151b‧‧‧Second conductive blind hole

16, 26‧‧‧ layered structure

164, 264‧‧‧Electrical contact pads

17, 27‧‧‧ solder mask

170, 270‧‧‧ solder mask opening

210a‧‧‧Blind hole

211a‧‧‧First opening

212a‧‧‧first slot

211b‧‧‧Second slotting

21c‧‧‧ third dielectric layer

22a‧‧‧First conductive layer

22b‧‧‧Second conductive layer

22c‧‧‧ third conductive layer

22a’, 22b’‧‧‧ another conductive layer

23a‧‧‧First barrier layer

230a‧‧‧First opening area

23b‧‧‧second barrier layer

230b‧‧‧second open area

23c‧‧‧ third resistive layer

230c‧‧‧ third open area

240‧‧‧ convex

241‧‧‧First metal layer

241'‧‧‧First thinned metal layer

242‧‧‧Second metal layer

241a‧‧‧ Conductive blind hole

241b‧‧‧first conductive hole

242’‧‧‧Second thinned metal layer

242b, 242c‧‧‧ electrical connection pads

242b’, 242b”‧‧‧ electrical connection pads

24c‧‧‧ third circuit layer

25a‧‧‧First Conductive Column

251a‧‧‧ end face

25b‧‧‧second conductive column

1A to 1G are schematic cross-sectional views of a conventional circuit board and a method of manufacturing the same; FIGS. 2A to 2M are cross-sectional views showing a first embodiment of the circuit board and the method of manufacturing the same; and FIGS. 3A to 3P are circuit boards of the present invention; FIG. 3E is a cross-sectional view showing another embodiment of FIG. 3E; and FIG. 3L' is a cross-sectional view showing another embodiment of the third embodiment.

20‧‧‧ core board

201‧‧‧ core circuit layer

21a‧‧‧First dielectric layer

21b‧‧‧Second dielectric layer

24a‧‧‧First circuit layer

24b‧‧‧second circuit layer

242b‧‧‧Electrical connection pads

25a‧‧‧First Conductive Column

Claims (35)

A circuit board comprising: a core board having opposite surfaces, having a core circuit layer on the surface; a first dielectric layer disposed on the core board; and a first circuit layer disposed on the first board a conductive via hole is disposed in the first dielectric layer to electrically connect the core circuit layer; the second dielectric layer is disposed on the first dielectric layer and the first circuit layer a plurality of first conductive pillars are disposed in the second dielectric layer and electrically connected to the first circuit layer, and an end surface of the first conductive pillar is flush with a surface of the second dielectric layer; and a second The circuit layer is disposed on the second dielectric layer and has a plurality of electrical connection pads to be electrically connected to each of the first conductive pillars, and the width of the electrical connection pads is equal to or smaller than the first The width of the conductive column. The circuit board of claim 1, wherein the core plate has a conductive via hole to electrically connect the core circuit layer on both surfaces of the core board. The circuit board of claim 1, wherein the circuit board comprises a build-up structure disposed on the second dielectric layer and the second circuit layer. The circuit board of claim 3, wherein the build-up structure comprises at least one third dielectric layer disposed on the third dielectric layer a third circuit layer, and a plurality of second conductive pillars disposed in the third dielectric layer and electrically connected to the second and third circuit layers. The circuit board of claim 4, wherein the third circuit layer further comprises a plurality of other electrical connection pads, and the other electrical connection pads are formed on the second conductive pillar. The circuit board of claim 5, wherein the width of the other electrical connection pad is greater than, equal to, or less than the width of the second conductive pillar. The circuit board of claim 4, wherein the third circuit layer of the outermost layer of the buildup structure has a plurality of electrical contact pads. The circuit board of claim 7, wherein the circuit board further comprises a solder resist layer disposed on the outermost third dielectric layer and the third circuit layer of the build-up structure, and a plurality of the solder resist layers are disposed The solder resist layer is opened to correspondingly expose each of the electrical contact pads. A circuit board comprising: a core board having opposite surfaces, having a core circuit layer on the surface; a first dielectric layer disposed on the core board; and a first circuit layer disposed on the first board The dielectric layer is flush with the first dielectric layer, and the first circuit layer has a plurality of first conductive holes electrically connected to the core circuit layer; the plurality of first conductive pillars are disposed at the first And the layered structure is disposed on the first dielectric layer, the first circuit layer, and the first conductive pillar, and the layered structure includes at least one second dielectric a second circuit layer disposed on the second dielectric layer, and the second circuit layer of the innermost layer has a plurality of electrical connection pads correspondingly disposed on each of the first conductive pillars, the electrical connection The width of the pad is equal to or less than the width of the first conductive pillar. The circuit board of claim 9, wherein the core plate is provided with a conductive through hole to electrically connect the core circuit layer on both surfaces of the core plate. The circuit board of claim 9, wherein the first dielectric layer is provided with a plurality of first openings and a first slot, and the first opening exposes a portion of the core circuit layer, the first line The layer is disposed in the first slot, and the first conductive hole is disposed in each of the first openings to be electrically connected to the core circuit layer. The circuit board of claim 9, wherein the second dielectric layer has a second slot, and the second circuit layer is disposed in the second slot of the second dielectric layer, the build-up structure The second conductive pillar is disposed in the second dielectric layer and electrically connected to the second wiring layer, and the surface of the second wiring layer is flush with the surface of the second dielectric layer. The circuit board of claim 12, wherein the second circuit layer further comprises a plurality of other electrical connection pads, and the other electrical connection pads are correspondingly disposed on each of the second conductive columns. The circuit board of claim 13, wherein the width of the other electrical connection pad is greater than, equal to, or less than the width of the second conductive pillar. Such as the circuit board of claim 9 of the patent scope, including electrical contact The pad is disposed on the second circuit layer of the outermost layer of the buildup structure. The circuit board of claim 15 , further comprising a solder resist layer disposed on the outermost second dielectric layer and the outermost second circuit layer of the build-up structure, and having a plurality of solder mask openings In order to expose each of the electrical contact pads. The circuit board of claim 9 further comprising a protrusion disposed on the first circuit layer to protrude the surface of the first dielectric layer such that the first conductive pillar is disposed on the protrusion. A circuit board comprising: a core board having opposite surfaces, having a core circuit layer on the surface; a first dielectric layer disposed on the core board; and a first circuit layer embedded in the first a dielectric layer having a convex portion protruding from the surface of the first dielectric layer, and the first circuit layer has a plurality of first conductive holes electrically connected to the core circuit layer; and a plurality of first conductive pillars, And a layered structure is disposed on the first dielectric layer, the first circuit layer, and the first conductive pillar, the buildup structure includes at least one a second dielectric layer, a second circuit layer formed on the second dielectric layer, a plurality of second conductive layers disposed in the second dielectric layer and electrically connected to the second conductive layer of the second circuit layer, and the innermost layer The second circuit layer has a plurality of electrical connection pads correspondingly formed on the first conductive pillars, such that the width of the electrical connection pads is greater than the width of the first conductive pillars, and the second circuit layer The surface is flush with the surface of the second dielectric layer. A method for manufacturing a circuit board, comprising: providing a core board having opposite surfaces, having a core circuit layer on the surface; forming a first dielectric layer on the core board, the first dielectric layer Forming a plurality of blind holes to expose a portion of the core circuit layer; forming a first conductive layer on the first dielectric layer, the hole wall of the blind hole, and a portion of the core circuit layer; a first resist layer is formed on the layer, and a first open region is formed in the first resist layer to expose a portion of the first conductive layer, and a portion of the first open region corresponds to a blind hole and a periphery thereof a conductive layer is formed on the first dielectric layer in the first open region, and a conductive via hole is formed in the blind via of the first dielectric layer to electrically connect the core line a second resist layer is formed on the first resist layer and the first circuit layer, and a second open region is formed in the second resist layer to expose a portion of the first circuit layer; Forming a first conductive pillar on the first circuit layer in the region; removing the second resistive layer, the first resistive layer and Covering the first conductive layer; in the first dielectric layer, a first wiring layer and the first conductive pillar is formed with a second dielectric layer; Removing a portion of the second dielectric layer to expose an end surface of the first conductive pillar; forming a second conductive layer on an end surface of the second dielectric layer and the conductive pillar; and forming a second conductive layer on the second conductive layer a third resist layer, and a plurality of third open regions are formed in the third resist layer to expose a portion of the second conductive layer, and a portion of the third open region corresponds to the first end of the first conductive pillar a second conductive layer; a second circuit layer having a plurality of electrical connection pads is formed in the third opening region, wherein the electrical connection pads are electrically connected to each of the first conductive columns; and the third is removed a resist layer and a second conductive layer covered thereby. The method of manufacturing a circuit board according to claim 19, wherein the core plate is formed with a conductive via hole to electrically connect the core circuit layer on both surfaces of the core board. The method for manufacturing a circuit board according to claim 19, wherein the second dielectric layer and the second circuit layer are formed with a build-up structure. The method of manufacturing a circuit board according to claim 21, wherein the build-up structure comprises at least a third dielectric layer, a third circuit layer formed on the third dielectric layer, and a plurality of layers formed thereon And electrically connecting the second conductive pillars of the second and third circuit layers to the third dielectric layer. The method of manufacturing a circuit board according to claim 22, wherein the third circuit layer comprises a plurality of other electrical connection pads, and the other An electrical connection pad is formed on each of the second conductive posts. The method of manufacturing the circuit board of claim 23, wherein the width of the other electrical connection pad is greater than, equal to, or less than the width of the second conductive pillar. For example, in the method of manufacturing a circuit board according to claim 21, a plurality of electrical contact pads are formed on the third circuit layer including the outermost layer of the buildup structure. The method for manufacturing a circuit board according to claim 25, wherein a protective layer is formed on the outermost third dielectric layer and the outermost third circuit layer of the build-up structure, and is formed in the solder resist layer. A plurality of solder mask openings are formed to correspondingly expose the respective electrical contact pads. A method for manufacturing a circuit board, comprising: providing a core board having opposite surfaces, having a core circuit layer on the surface; forming a first dielectric layer on the core board; and forming the first dielectric layer on the core board a first circuit layer is formed in the first circuit layer, and the first circuit layer is flush with the surface of the first dielectric layer, and a first conductive hole is formed in the first dielectric layer to be electrically connected to the core circuit layer; Forming a first conductive pillar on a portion of the first circuit layer; and forming a build-up structure on the first dielectric layer, the first circuit layer, and the first conductive pillar, the build-up structure includes At least one second dielectric layer, a second circuit layer formed on the second dielectric layer, and the innermost second circuit layer has a plurality of electrical connection pads to be formed correspondingly The width of the electrical connection pad on each of the first conductive pillars is equal to or smaller than the width of the first conductive pillar. The method of manufacturing a circuit board according to claim 27, wherein the core plate is formed with a conductive via hole to electrically connect the core circuit layer on both surfaces of the core board. The method of manufacturing a circuit board according to claim 27, wherein the second dielectric layer has a second slot, the second circuit layer is formed in the second slot of the second dielectric layer, and the increase The layer structure includes a plurality of second conductive pillars disposed in the second dielectric layer and electrically connected to the second wiring layer, and the surface of the second wiring layer is flush with the surface of the second dielectric layer. The method of manufacturing a circuit board according to claim 29, wherein the second circuit layer further comprises a plurality of other electrical connection pads, and the other electrical connection pads are correspondingly formed on each of the second conductive columns. on. The method of manufacturing the circuit board of claim 30, wherein the width of the other electrical connection pad is greater than, equal to, or less than the width of the second conductive pillar. For example, in the method of manufacturing a circuit board of claim 27, a plurality of electrical contact pads are formed on the second circuit layer including the outermost layer of the buildup structure. The method for manufacturing a circuit board according to claim 32, wherein a second solder layer is formed on the outermost second dielectric layer and the outermost second circuit layer of the build-up structure, and is formed in the solder resist layer. A plurality of solder mask openings are formed to correspondingly expose the respective electrical contact pads. The method for manufacturing a circuit board according to claim 27, further comprising a convex portion formed on the first circuit layer to protrude the surface of the first dielectric layer, so that the first conductive pillar is disposed on the convex portion . A method for manufacturing a circuit board, comprising: providing a core board having opposite surfaces, having a core circuit layer on the surface; forming a first dielectric layer on the core board; and forming the first dielectric layer on the core board A first circuit layer is embedded in the first circuit layer, and the first circuit layer has a convex portion protruding from the surface of the first dielectric layer, and a first conductive hole is formed in the first dielectric layer to be electrically connected to a core layer; a first conductive pillar is plated on the convex portion of the first circuit layer; and a build-up structure is formed on the first dielectric layer, the first circuit layer, and the first conductive pillar, The build-up structure includes at least one second dielectric layer, a second circuit layer formed on the second dielectric layer, and a plurality of second dielectric layers disposed in the second dielectric layer and electrically connected to the second circuit layer a second conductive layer, wherein the innermost second circuit layer has a plurality of electrical connection pads correspondingly formed on each of the first conductive pillars, such that the width of the electrical connection pads is greater than the width of the first conductive pillars, and The surface of the second wiring layer is flush with the surface of the second dielectric layer.