200950038 凡，货啲說明： 【發明所屬之技術領域】 J 纟發明係有關於—種封襄基板之製法，尤指-種無核 -心層封裝基板之製法。 【先前技術】 ' 冑著電子產業的蓬勃發展’為滿足半導體封裝件高積 -集度integration)及微型化的封裝要求下發展出多數 ，、被動元件及線路之多層電路板，以於有限間下， β糟由層間連接技術（Interlayer eQnneetiQn)擴大電路板 上可利用的佈線空間，以配合高密度線路之積體電路的使 用需求。另外’習知覆晶式半導體封裝件係將半導體晶片 以覆晶接合（Flip chip)電性連接封裝基板。 请參閱第1A至1F圖，係為習知封裝基板之製法。 如第1A圖所示，提供一核心板1()，於該核心板 之表面形成第-線路層m，且於該核心板1〇中形成導 • It 1〇2以電性連接該核心板1〇兩表面上之第-線路 _ 層 1 01。 如第1B圖所示’於該核心板1〇及第一線路層1〇1 ^^第-介電層η，且於該第—介電層u中形成複數 ^丨电層開孔110，以顯露部份第一線路層1〇1。 如第1C圖所示，於部份第一線路層1(H、介電層開 孔m的孔壁、及第-介電層η上形成導電層12，:於 =導電層上形成光阻層13’該光阻層13並形成複數 開口區130,其中部份開口區130對應顯露該介電層開孔 110788 5 200950038 iju汉丹孔端周圍之導電声I?。 如第1D圖所示，於該開口區13〇中 “鍍形成第二線路層14,且;導电層12上％ -一導電盲孔141以年# * 層開孔110中形成第 電 以’电性連接該第-線路層101。 如《 1E圖所示，移除該光阻層13 層12,以顯露該第一介雷 復|之導电 7丨電層11及第二線路層14。 如第1F圖所示’於該第一介電 14上形成增層結構15 及第-線路層 入+ a Λ頊層、'，口構15係包括至少一第一 ❹二二一第二介電層⑸上之第三線Ϊ: 152、及形成於該第二介 I路層 且兮筮__道中亡， 弟一導電盲孔153, ^ ^目1 153 t性連接該第二及第三線路声 ’152’又該第三線路層152具有電性接觸墊 ς =增層結構15均餘焊層16，㈣焊層16中成 :=顯露該電性接觸塾154，而完成一封裝基板成 =裝基板H性接觸塾154㈣供電性連接半導 日日片（圖未示），而另一側之電性 〇 nil i Ν ^ 电芘接觸墊154藉由焊料球 (圖未不）以供電性連接印刷電路板（圖未示）。 t習知封裝基板結構具有核^。板1Q，因訊號傳遞 ^過長而使訊號傳遞速率降低或訊號衰減，且於封裝基 反中設有該核W板1G，導致該封裝基板整 : 而無法達到薄小之目的。 曰加 。另外，習知於核心板10形成之導電通孔102，其兩 為分別於該核心板10兩表面占用佈線之面積，而無法辦 加線路佈局密度。 …、曰 110788 6 200950038 一囚此，如何提出一種封裝基板製法，以使封裴基板達 到薄小體積、提高訊號傳遞速率、及增加線路佈局密度， '實以成為目前業界亟待克服之課題。 '【發明内容】 ， 鑑於上述習知技術之種種缺失，本發明之一目的在於 提供一種封装基板之製法，以使封裝基板達到體積薄小、。 本發明之另一目的在於提供一種封裝基板之製法，以 提南訊遽傳遞速率。 ❹ 本發明之又—目的在於提供一種封裝基板之製法，以 增加線路佈局密度。 本發明之再一目的在於提供一種封裝基板之製法，以 保護基板本體可避免產生過度侵钮現象。 、為達上述及其它㈣，本發明揭露-種封裝基板之製 法，係包括：、提供_承載板，係具有側表面及相對之兩表 面於，玄承載板之兩表面形成剝離層，且於該剝離層上及 β :載2:表面形成第一金屬層’並於第-金屬層上形成 入…屬層，於该第二金屬層上形成第—介電層，且形成 ^電層開孔’以顯露部份第二金屬層；於該第—介電層上 f成第一線路層’並於該介電層開孔中形成電性連接i 一 =層之第—導電盲孔；於該第—介電層及第-線路層上 、隹」增層、、、口構’以形成一初始基板；沿該初始基板之邊緣 龅:刀割、以顯路㈣離層及承載板；移除該承載板及剝 以刀成兩基板本體，並顯露各基板本體之第一金屬 層；以及移除該第—及第二金屬層，以顯露該第一介電層 110788 7 200950038 及弟一等電盲孔。 上述製法中，係可田τ η J二金屬層。 5蝕刻液以依序移除第一及第 ' 上述製法中，該第一+ Μ 二係為錫或鎳，藉以:護:板本第二金屬層 上述製法中，該第一 第-二:孔。 法，係可包括··於該第—介電岸;t該弟一導電盲孔之製 成第-導電層；於該第_導^及Μ層開孔之孔壁上形 ©開口區以顯露部份第—導兩:曰形成第一阻層，且形成 介電層開孔及其周圍之第：二對二:;層=以顯露 —線路層，而於該介電⑼^層’㈣開吨中形成第 移除該第__阻；β L中形成第—導電盲孔；以及 乂弟阻層及其所覆蓋之第 上述製法中，復可包括於一八^ 構之表面及第一導恭亡，；U苐一，丨電層未形成增層結 連接第—導電盲孔成第;"電性接觸塾，以電性 包括··於該第一介電層中及二 © ®禾等電盲孔上形成篦-道雪 ㈣:ι=層及增層結構上分別形成第二阻；，且 導電盲孔及其周圍形成開孔，以顯露該第-層上形成該第-電性層；於該開孔中之第二導電 覆蓋之第二導電層。’以及移除該第二阻層及其所 觸復可包括於該第一介電層及第-電性接 上^成第一防焊層，Β 4结 孔m當…層中形成第一開 顯路5亥第一電性接觸塾，並可於該第-電性接觸塾 110788 8 200950038 上形成表面處理層。 上述製法中，該增；ό士堪 ‘層、形成於該第二介電;可包括至少-第二介電 -·第二介電層中之第二導電曰盲孔之第=路㉟、及形成於該 接嗲第η^ . 目 且该第一導電盲孔電性連 ； 按邊弟一及弟二線路層， Φ M itL M 卜g之第二線路層具有第二 电！生接觸墊；又於該增層έ 第- 構上形成第二防焊層，且形成 第—開孔，以顯露該第二電性接觸塾。 依上述之製法’該第二電性接 Λ層，亦可於兮笼-+以J〜取衣卸/处埋 導電凸觸墊上先形成導電凸塊，再於該 电凸塊上形成表面處理層。 焊芦法之另一貫施態樣中，復可包括於該第二防 _上形成支撐層，且呈有去 防焊層、第一雷…㈠:支撐層開口’以顯露部分第二 層第一電性接觸墊及其周圍之佈局區域。 _ + Γ上可知，本發明之封裝基板之製法係藉由第一及第 =層1承載板’以保護基板本體，再以不同触刻液 0 ^第-及4二金㈣，俾能避免過度侵姑而破壞第一導 电盲孔。另外，相較於習知技術，本發明所製作之封裝基 =無核心層之設置’而減少封裝基板之厚度，有效達到 =小之目的，並可避免訊號傳遞路捏過長，有效達到 接就傳遞速率提高之目的，更因無導電通孔占用佈線之面 積’而得以有效達到提高佈線密度之目的。 【實施方式】 以下藉由特定的具體實施例說明本發明之實施方 式’熟悉此技藝之人士可由本說明書所揭示之内容輕易地 1J0788 9 200950038 瞭解本發明之其他優點及功效。 請參閱第2A至20圖’係為本發明之封裝基板之製法 之剖面示意圖。 . 如第2A圖所示，首先，提供一整版面（panel)之承載 /板20，係具有側表面20b及相對之上、下兩表面20a，該 承載板20可為具雙面銅箔（圖未示）之樹脂基材（CCL)，於 該上、下表面20a形成剝離層201，且於該剝離層2〇1上 及該承載板20之側表面20b形成例如為銅箔之第一金屬 ❹層21a，並於該第一金屬層21a上形成例如為錫或錄之 二金屬層21b。 如第2B圖所示，於對應承載板2〇上下表面 2第二金屬層21b上形成第—介電層％，且形成複數介 電層開孔220a，以顯露部份該第二金屬層21b。 :第2C圖所示，於該第一介電層^及該介電層開 a之孔壁上形成第—導電| 23&，且於該第一導 上第一阻層24a’並於該第一阻層24a中形成 =數開口區240a’以顯露部份之第—導電層…，而部份 孔22^2::^應"電層開孔22〇a’以顯露各該介電層開 中之第二金屬層21b及其周圍之第一導電層仏。 所述之導電層23a主要作 傳導路徑’其可由金屬、合金、沉積數層二 子材料所構成;而該第一阻層 膜或液態光阻等，且刹田^ l J札 該第一導電；23/i 塗或貼合等方式形成於 " 再藉由曝光、顯影等方式加以圖案 110788 10 200950038 化’以形成該開口區2 4 〇 a。 如第2D圖所示，藉由兮 ‘ , μ弟一導電層23a作為電流傳 v路瓜，以於6亥開口區240a ^ 〇〇 -嚷m ^ , 甲之弟一導電層23a上形成 -第v泉路層2 5 a ’並於各該介带 R “丨电層開孔220a中形成第一 ,4¾盲孔251a’且該第一莫# - 乐导电盲孔251a電性連接該第一 線路層25a;所述之第一線路 二逐接㈣ &纷增25a之材料係為金屬；惟， 依貫際操作之經驗，由於銅為 ^ , 钔為成热之電鍍材料且成本較 低，因此，以電鍍銅較佳，但非以此為限。 ❹ 如弟2Ε圖所示，務险兮结 斤丁移“第-阻層24a及其所覆蓋之 弟一 h層23a，以顯露該第—線路層❿及第—介電層 22a。 曰 如第2F圖所不，接著’於該第一介電層22a及第一 線路層25a上形成增層結構2β，以形成一初始基板％。 所述之增層結構26係包括至少一第二介電層22卜 形成於該第二介電層22b上之第二線路層挪、及形成於 該第二介電㉟22b中之複數第二導電盲孔251b，且各該 第二導電盲孔251b電性連接該第二線路層25b，而部^ 之第二導電盲孔251b電性連接第一線路層25a。 如第2G圖所示，沿該初始基板2a之邊緣s(如第2ρ 圖所示）進行切割，以移除部份增層結構26、部份第一 介電層22a、部份第二金屬層21b、部份第一金屬層21&、 份剝離層201、及部份承載板2〇，以顯露該剝離層2〇 j 及承載板20之側邊20c。 如第2H圖所示，移除該承載板2〇及剝離層2〇1以分 110788 11 200950038 成兩基板本體2,並顯露各基板本體2之第一金屬層21a。 • 2之第如一第八2=，以不__序移除各基;反:體 之4 i屬層21a及第二金屬層21b ’以顯露 -體2之第一介電層22a及第一導電盲孔2叫。土 · 如第2J圖所示，於該第一介電層22a及第—導電盲 孔⑸a上形成第二導電層挪；再於該第 声 ^曾層結構26上分別形成第二阻層24b，且於㈣二23b 宅層23b上之第二阻層24b形成複數開孔鳩 ❹：露各該第-導電盲孔如及其孔端周圍之第二導^ 上4°开第二圖所示’於該開孔240b中之第二導電層咖 塾=形成,性連接第一導電盲孔251a之第一電性接觸 如第2L圖所示，移除該增層結構26上之第二 ❹ 如圖所示’於該第一介電層^未形成增層結 26之表面及第一電性接㈣咖上形成第一防谭層 應辟^玄第一防焊層％形成複數第一開孔270a，以對 ;=各二亥第一電性接觸墊26a ;又’增層結構26最外 二二一線路層25b具有第二電性接觸塾，並於增層 有H 第二防焊層27b’且該第二防焊層抓具 弟一開孔27〇b’以對應顯露第二電性接觸墊26b。 第2N及2N圖所示’於該第一電性接觸整心上 110788 12 200950038 處理層28b，且於第二電性接觸塾_上依序形 .凸塊.及表面處理層28b，以完成一整版面之封 ^板，如第2N圖所該導電凸塊如係為銅(㈤， .该表面處理層28b係'為錫一錯（Sn〜Pb)、錫省⑸―⑻ ;銀铺AC)、或錫(Sn)。另外，於其他實施例中，如第 如第20圖所示，係接續第⑽圖’將整版面之封裝基 ❺板經由㈣形成複數縣基板單元，再於各縣基板單^ 之第二防焊層27b上形成支樓層29,且該支撐層29且有 支撑層開口 290,以顯露部分之第二防焊層m及全部第 —電性接觸塾26b及其周圍之佈局區域；藉由該支撐層 29以提高封裝基板強度，避免封裝基板產生m a 斤綜上所述，本發明之封装基板之製法，係藉由該第— 及第-金屬層21a，21b包覆該承餘2G，以保護形成於 違承載板20上之基板本體2，再以不同㈣液依序移除 •該第-及第二金屬層21a，21b，以藉由該第二金屬層仙 保護該基板本體2’俾能避免過度侵蝕而破壞第一導電 孔 251a 。 另外’本發明所製作之封裝基板因該基板本體2不具 核心層，故能使訊號傳遞路徑減短，而避免因訊號傳遞路 徑過長，致使訊號傳遞速率降低或訊號衰減，故有效達到 訊號傳遞速率提高之目的。 又，因不具核心層，不僅得以減少封裝基板之厚度， 】10788 13 200950038 且無需製作導電通孔，以避免導 而有效達到提高佈線密度之目 向逹到體積薄小之目的 %通孔占用飾線之面積 的。 上述實施例係用以例示性 吋， 〖生5兄明本發明之原理及其功 ' 而非用於限制本發明。任何孰習并炤妯矿 力、土北丄 J .，，、白此項技蟄之人士均可200950038 Where, the description of the goods: [Technical field to which the invention belongs] J 纟 The invention relates to the method of manufacturing a substrate, especially a method for producing a coreless-heart layer package substrate. [Prior Art] 'With the booming development of the electronics industry', in order to meet the high-product integration of semiconductor packages and miniaturized packaging requirements, many, passive components and circuit multilayer boards have been developed. Next, the inter-layer connection technology (Interlayer eQnneetiQn) expands the wiring space available on the board to meet the needs of the integrated circuit of high-density lines. Further, the conventional flip-chip semiconductor package electrically connects a semiconductor wafer to a package substrate by flip chip bonding. Please refer to FIGS. 1A to 1F for the fabrication of a conventional package substrate. As shown in FIG. 1A, a core board 1 is provided, a first circuit layer m is formed on the surface of the core board, and a conductive layer is formed in the core board 1〇 to electrically connect the core board. 1〇 on the two surfaces - line _ layer 1 01. As shown in FIG. 1B, the core layer 1 and the first circuit layer 1 〇 1 ^ ^ dielectric layer η, and the plurality of dielectric layer openings 110 are formed in the first dielectric layer u, To expose part of the first circuit layer 1〇1. As shown in FIG. 1C, a conductive layer 12 is formed on a portion of the first wiring layer 1 (H, a hole wall of the dielectric layer opening m, and the first dielectric layer η): a photoresist is formed on the = conductive layer The layer 13' of the photoresist layer 13 forms a plurality of open regions 130, wherein a portion of the open regions 130 correspondingly expose the conductive sound I around the dielectric layer opening 110788 5 200950038 iju Handan hole end. As shown in FIG. 1D Forming a second wiring layer 14 in the opening region 13 ,, and a %-a conductive blind via 141 on the conductive layer 12 forms a first electric current in the layer opening 110 to electrically connect the first - circuit layer 101. As shown in Fig. 1E, the photoresist layer 13 layer 12 is removed to expose the first dielectric layer 11 and the second wiring layer 14 of the first dielectric layer. The formation of a build-up structure 15 and a first-layer layer of + a Λ顼 layer on the first dielectric 14 is shown, and the mouth structure 15 includes at least a first second 221 second dielectric layer (5). The third line Ϊ: 152, and formed in the second I-channel layer and 兮筮__ in the road, the younger one conductive blind hole 153, ^ ^ 1 153 t connected the second and third line sound '152 'The third circuit layer 152 is electrically The contact pad ς = the build-up structure 15 is the residual solder layer 16, and (4) the solder layer 16 is formed: = the electrical contact 塾 154 is exposed, and a package substrate is completed = the substrate H-contact 154 is formed (4) the power supply connection semi-conducting day The film (not shown), and the other side of the electrical 〇nil i Ν ^ 芘 contact pad 154 is electrically connected to the printed circuit board (not shown) by solder balls (not shown). The package substrate structure has a core board 1Q, because the signal transmission is too long, the signal transmission rate is reduced or the signal is attenuated, and the core W board 1G is disposed in the package base, resulting in the package substrate being completely: In addition, it is known that the conductive vias 102 formed in the core board 10 are occupied by the area of the wiring on both surfaces of the core board 10, and the layout density cannot be increased. ..., 110788 6 200950038 In this case, how to propose a method of packaging substrate, so that the sealing substrate can achieve a small volume, improve the signal transmission rate, and increase the layout density of the circuit, which has become an urgent problem to be overcome in the industry. In view of the above-mentioned techniques One of the objects of the present invention is to provide a method for manufacturing a package substrate so that the package substrate can be made thinner. Another object of the present invention is to provide a method for manufacturing a package substrate to improve the transfer rate of the signal. Further, another object of the present invention is to provide a method for manufacturing a package substrate to increase the layout density of the circuit. A further object of the present invention is to provide a method for fabricating a package substrate to protect the substrate body from excessive over-knocking. The above and other (4), the invention discloses a method for manufacturing a package substrate, comprising: providing a carrier plate having a side surface and opposite surfaces, wherein a peeling layer is formed on both surfaces of the sinuous carrier plate, and the peeling layer is formed on the peeling layer And β: carrier 2: forming a first metal layer on the surface and forming a layer on the first metal layer, forming a first dielectric layer on the second metal layer, and forming an opening of the electrical layer Exposing a portion of the second metal layer; forming a first circuit layer on the first dielectric layer and forming an electrical connection i -=the first conductive hole in the opening of the dielectric layer; On the dielectric layer and the first layer, the layer is formed, and the interface is formed to form an initial substrate; along the edge of the initial substrate: a knife cut, a path (4) and a carrier plate; Carrying the board and stripping the two substrate bodies, and exposing the first metal layer of each substrate body; and removing the first and second metal layers to expose the first dielectric layer 110788 7 200950038 Blind hole. In the above method, it is a metal layer of the field τ η J. 5 etching liquid in order to remove the first and the second in the above method, the first + Μ second is tin or nickel, by: protection: the second metal layer of the board, the first method of the second method: hole. The method may include: forming a first conductive layer on the first conductive wall; and forming a first conductive layer on the conductive hole of the first and second openings; Exposing part of the first-lead two: 曰 forming a first resistive layer, and forming a dielectric layer opening and its surroundings: two pairs of two:; layer = to reveal - circuit layer, and in the dielectric (9) layer (4) forming the first __ resistance in the opening ton; forming the first conductive blind hole in the β L; and the 阻 阻 阻 及其 and the above-mentioned method of covering the same, the complex may be included on the surface of the structure The first guide is dying; U苐一, the 丨 electric layer is not formed with a build-up junction connection—the conductive blind hole is the first; "electric contact 塾, electrically including ··· in the first dielectric layer ©-道雪(四): ι= layer and layered structure respectively form a second resistance; and a conductive blind hole and its periphery form an opening to reveal the formation on the first layer The first electrical layer; the second conductive layer covering the second conductive layer in the opening. And removing the second resist layer and the contact thereof may be included in the first dielectric layer and the first electrical connection to form a first solder resist layer, and the junction hole m is formed as a first layer in the layer The first electrical contact 开 of the road is opened, and a surface treatment layer can be formed on the first electrical contact 塾110788 8 200950038. In the above method, the ό ό ό 层 层 形成 形成 形成 形成 形成 形成 形成 形成 形成 层 层 层 层 层 层 层 层 层 层 层 层 层 层 层 层 层 层 层 层 层 层 层 层 层 层 层 层 层 层And formed in the interface η^. and the first conductive blind hole is electrically connected; according to the edge of the brother and the second circuit layer, the second circuit layer of Φ M itL M 卜 g has the second power! And forming a second solder mask on the first layer of the buildup layer, and forming a first opening to expose the second electrical contact. According to the above method of manufacturing, the second electrical interface layer may also form a conductive bump on the conductive bump pad on the 〜 - + + + / / / 处 / / / / 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电Floor. In another embodiment of the soldering method, the complex may include forming a supporting layer on the second anti- _, and having a solder resist layer, a first thunder... (1): a support layer opening 'to expose a portion of the second layer An electrical contact pad and a layout area around it. _ + Γ 可 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Excessive aggression destroys the first conductive blind hole. In addition, compared with the prior art, the package base made by the invention has no setting of the core layer to reduce the thickness of the package substrate, effectively achieving the purpose of small, and avoiding the signal transmission path being pinched too long, effectively achieving the connection. For the purpose of improving the transfer rate, the area of the wiring is occupied by the non-conductive via hole, and the wiring density is effectively improved. [Embodiment] The following describes the embodiments of the present invention by way of specific embodiments. Those skilled in the art can readily appreciate the other advantages and effects of the present invention from the disclosure of the present specification. 2A to 20' are schematic cross-sectional views showing a method of manufacturing a package substrate of the present invention. As shown in FIG. 2A, firstly, a full-panel carrier/plate 20 is provided having a side surface 20b and opposite upper and lower surfaces 20a, and the carrier 20 may be a double-sided copper foil ( A resin substrate (CCL), not shown, forms a peeling layer 201 on the upper and lower surfaces 20a, and forms a first copper foil, for example, on the peeling layer 2〇1 and the side surface 20b of the carrier sheet 20. The metal layer 21a is formed on the first metal layer 21a, for example, a tin or a metal layer 21b. As shown in FIG. 2B, a first dielectric layer % is formed on the second metal layer 21b of the upper and lower surfaces 2 of the corresponding carrier board 2, and a plurality of dielectric layer openings 220a are formed to expose a portion of the second metal layer 21b. . : in FIG. 2C, a first conductive layer is formed on the first dielectric layer and the sidewall of the dielectric layer, and a first resistive layer 24a' is formed on the first conductive layer. The first resistive layer 24a is formed with a plurality of open regions 240a' to expose portions of the first conductive layer ..., and a portion of the holes 22^2::^ should be " electrical layer openings 22〇a' to reveal each of the dielectric layers The second metal layer 21b of the electrical layer is opened and the first conductive layer 周围 around it. The conductive layer 23a is mainly used as a conductive path, which may be composed of a metal, an alloy, and a plurality of layers of two sub-materials; and the first resistive film or liquid photoresist, etc., and the first conductive layer; The 23/i coating or lamination is formed by " and then patterned by exposure, development, etc. to form the open area 2 4 〇a. As shown in FIG. 2D, a conductive layer 23a is used as a current-transferring layer to form a current-emitting layer 23a in the 6-well opening region 240a ^ 〇〇-嚷m ^ The first v-spring layer 2 5 a 'and the first dielectric layer R is formed in each of the dielectric layers R, and the first and second conductive holes 251a are electrically connected to the first a circuit layer 25a; the first circuit 2 is connected (4) & the material of the 25a is metal; however, according to the experience of continuous operation, since copper is ^, 钔 is a hot plating material and the cost is relatively high. Low, therefore, it is better to use electroplated copper, but not limited to this. ❹ As shown in the figure 2, the risky 兮 移 移 移 移 移 移 移 移 移 移 移 移 移 移 移 移 移 移 移 移 移 移 移 移 移 移 移 移 移 移 移 移The first-layer layer and the first-dielectric layer 22a are exposed.曰 As shown in FIG. 2F, a build-up structure 2β is formed on the first dielectric layer 22a and the first wiring layer 25a to form an initial substrate %. The build-up structure 26 includes at least a second dielectric layer 22, a second circuit layer formed on the second dielectric layer 22b, and a plurality of second conductive layers formed in the second dielectric 3522b. The second conductive layer 251b is electrically connected to the second circuit layer 25b, and the second conductive blind hole 251b is electrically connected to the first circuit layer 25a. As shown in FIG. 2G, the edge s of the initial substrate 2a (shown as FIG. 2p) is cut to remove a portion of the buildup structure 26, a portion of the first dielectric layer 22a, and a portion of the second metal. The layer 21b, the portion of the first metal layer 21&, the portion of the release layer 201, and the portion of the carrier sheet 2 are exposed to expose the release layer 2〇j and the side 20c of the carrier sheet 20. As shown in Fig. 2H, the carrier plate 2 and the peeling layer 2〇1 are removed to form the two substrate bodies 2 by dividing 110788 11 200950038, and the first metal layer 21a of each substrate body 2 is exposed. • 2 is as an eighth 2=, removing each base in a non-_ sequence; inverse: 4 i is a layer 21a and a second metal layer 21b' to expose the first dielectric layer 22a and the body 2 A conductive blind hole 2 is called. As shown in FIG. 2J, a second conductive layer is formed on the first dielectric layer 22a and the first conductive via hole (5)a; and a second resist layer 24b is formed on the first sound layer structure 26, respectively. And forming a plurality of openings 于 in the second resist layer 24b on the (4) 2 23b floor 23b: exposing each of the first conductive baffles, such as the second guide around the hole end thereof, 4° on the second figure The second conductive layer is formed in the opening 240b, and the first electrical contact that is connected to the first conductive blind via 251a is removed as shown in FIG. 2L, and the second layer on the buildup structure 26 is removed. ❹ As shown in the figure, the first anti-solder layer is formed on the surface of the first dielectric layer that is not formed with the build-up layer 26 and the first electrical connection (four) coffee. An opening 270a, in pairs; = each of the second electrical contact pads 26a; and a 'layered structure 26 outermost two-two circuit layer 25b has a second electrical contact 塾, and has a second layer in the second layer The solder resist layer 27b' and the second solder mask gripper has an opening 27〇b' to correspondingly expose the second electrical contact pad 26b. The 2N and 2N diagrams show that the first electrical contact is centered on the 110788 12 200950038 processing layer 28b, and is sequentially formed on the second electrical contact 塾_. The bump and the surface treatment layer 28b are completed. A full-page sealing plate, such as the 2N figure, the conductive bump is made of copper ((5), the surface treatment layer 28b is 'tin-dislocation (Sn~Pb), tin province (5)-(8); silver shop AC), or tin (Sn). In addition, in other embodiments, as shown in FIG. 20, the splicing of the package substrate of the entire layout is carried out by (4) forming a plurality of substrate units of the plurality of substrates, and then the second prevention of the substrate of each county. A support floor 29 is formed on the solder layer 27b, and the support layer 29 has a support layer opening 290 to expose a portion of the second solder resist layer m and all of the first electrical contact pads 26b and surrounding layout areas thereof; The supporting layer 29 is used to improve the strength of the package substrate and avoid the generation of the package substrate. The method for manufacturing the package substrate of the present invention is to cover the residual 2G by the first and second metal layers 21a, 21b. Protecting the substrate body 2 formed on the carrier board 20, and sequentially removing the first and second metal layers 21a, 21b with different (four) liquids to protect the substrate body 2' by the second metal layer The crucible can avoid excessive erosion and damage the first conductive via 251a. In addition, the package substrate manufactured by the present invention can reduce the signal transmission path because the substrate body 2 does not have a core layer, and avoids the signal transmission path being too long, resulting in a decrease in signal transmission rate or signal attenuation, thereby effectively achieving signal transmission. The purpose of speed increase. Moreover, because there is no core layer, not only can the thickness of the package substrate be reduced, 10788 13 200950038, and there is no need to make conductive via holes, so as to avoid the purpose of increasing the wiring density and the thin volume. The area of the line. The above embodiments are intended to be illustrative, and the principles of the invention and its function are not intended to limit the invention. Anyone who is awkward and has the skills of mining, earthworms, J., and white
在不延为本發明之精神及範綠 拟L+A E令。阳* 4· 乾可下，對上述實施例進行修 圍所列。 ㈣保⑼圍’應如後述之中請專利範 ©【圖式簡單説明】 第1A至1F圖係為習知 筮9a 对裝基板之製法示意圖；以及 至· 2 0圖係為本發明| 4由丨 【主要元杜： 圖之另-實施態樣。 L主要兀件符號說明】 10 核心板 101，25a第一線路層 102 ^ 11,22a 1 10, 220a 12 13 130,240a 14,25b 141,251a 1 53, 251b 導電通孔 第一介電層 介電層開孔 導電層 光阻層 開〇區 务線路層 第〜導電盲孔 第二導電盲孔 110788 14 200950038 ID, Zb 增層結構 151,22b 第二介電層 .152 第三線路層 '154 * 電性接觸墊 16 防焊層 160, 240b 開孔 ' 2 基板本體 2a 初始基板 ❹20 承載板 20a 表面 20b 側表面 20c 側邊 201 剝離層 21a 第一金屬層 21b 第二金屬層 23a 第一導電層 ❹23b 第二導電層 24a 第一阻層 24b 第二阻層 26a 第一電性接觸墊 26b 第二電性接觸墊 27a 第一防焊層 270a 第一開孔 27b 第二防焊層 15 Π 0788 Z i UD 第二開孔 28a 導電凸塊 28b 表面處理層 29 支撐層 290 支撲層開口 s 邊緣 200950038It is not intended to be the spirit of the invention and the general green L+A E order. Yang*4. Dry, the above examples are listed for revision. (4) Bao (9) Wai 'should be as follows, please ask for a patent model © [Simple description of the drawings] Figures 1A to 1F are schematic diagrams of the method for preparing a substrate for the 筮9a; and to Fig. 2 is a diagram of the invention | 4 Because of [main yuan Du: Figure another - implementation aspect. L main element symbol description] 10 core board 101, 25a first circuit layer 102 ^ 11, 22a 1 10, 220a 12 13 130, 240a 14, 25b 141, 251a 1 53, 251b conductive via first dielectric layer dielectric layer Open-hole conductive layer photoresist layer open-circuit area circuit layer ~ conductive blind hole second conductive blind hole 110788 14 200950038 ID, Zb build-up structure 151, 22b second dielectric layer. 152 third circuit layer '154 * electric Contact pad 16 solder mask layer 160, 240b opening ' 2 substrate body 2a initial substrate ❹ 20 carrier plate 20a surface 20b side surface 20c side 201 peeling layer 21a first metal layer 21b second metal layer 23a first conductive layer ❹ 23b Two conductive layers 24a First resistive layer 24b Second resistive layer 26a First electrical contact pads 26b Second electrical contact pads 27a First solder mask 270a First opening 27b Second solder mask 15 Π 0788 Z i UD Second opening 28a conductive bump 28b surface treatment layer 29 support layer 290 branch layer opening s edge 200950038
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