200816416 •九、發明說明： 暴 V【發明所屬之技術領域】 本發明係關於—種半導體製程，尤指-種應用於半導 體封裝件之基板結構及其製法。 【先前技術】 • 對於以基板作為晶片承載件的球柵陣列（Ball Grid ：ΑΓΓ8Τ，BGA)半導體封裝件而言，其訊號傳輸設計往往係藉 由基板之設計’而將晶片之訊號透過銲線傳遞至基板上之 銲指（Finger)’再藉由基板之導電貫孔（via)傳遞至基板底 面的！干球墊（Ball Pad)，以透過植設於該銲球墊上之銲 球，進而傳遞至外界，同時為提升及維持封裝件之電性功 月匕亦而在該基板上设置電源環（power ring)及接地環 (ground ring)，以供晶片透過銲線電性搞合至該電源環及 接地環，如美國專利US5,581 122所揭示者。 祕板之銲指、銲耗、電源環及接地環—般係為金 肩屬銅材質’而為提供銲線或銲球與該基板之電源環、接地 銲減銲球墊良好接著，同時保護該電源環、接地環、 :^曰及#球墊避免受外在環境污染，通常即須在該電源 . 接地％、鋅指及銲球墊表面覆蓋一鎳金層（Ni/Au)。 ,然而，傳統形成鎳金層之製法缺點在於基板之表面必 須額外佈，多數電鍍導線，以進行電鐘錄金層之步驟；因 此’對於南密度之基板，此種設計即有基板面積不足之缺 ^此外’對於高頻產品而言，此些電錢導線將形成天線 （antennaeffect)’而有雜訊之產生，亦將干擾訊號 19593 5 200816416 之傳輸，故而此類結構已漸不符今日產品所需。 為解決此一問題，業界遂發展出兩種不需電鍍導線的 基板製法，包括選擇性電鍍（SelectedG〇ld，SG)製法及無 電鍍線鏡鎳金（Non Piating Line，NPL)製法，以下即分述 其製法流程與所形成的基板結構。 對SG製法而言’其係先如第1A圖所示，於基板芯層 1〇上形成銅層（CuFoil)11，再如第1Bs，利用光阻層12 楚^ k銅層π上定義出如電源環、接地環、銲指及銲球墊 f電性連接部之開口 12〇位置；接著，如第1C目，於該些 浐=開口 120中鍛上錄金層13 ’此錄金層13之電錄面 二=光阻層12之開口 120面積相同；再如第1D圖， :::=層12 ’然後’如第1E圖’圖案化該銅層 ^導電跡線、電源環、接地環、銲指及銲球墊等之電 連接部110,並敷設拒銲層14， ’ ⑽露出該些已錄有錄金層13的電性m14之開口 開口140面積係略小於該鎳金層之面 m該拒鮮層14係覆蓋住部分 110上之鎳金層13周圍。 對NPL製法而言，則係如第2a 層20上形成銅層2卜再如第2B圖，.利：於基板芯 程而圖案化該銅層21，並定義出如電，知曝光顯影製 及銲球墊等電性連接部21();接著，如/、接地=鋒指 如利用無電解電鍍之薄銅層25，再乐2C圖’覆蓋-例 層22，以利用該光阻層22之開口 22〇 j圖’形成光阻 疋義出該電性連接 19593 6 200816416 •部則中預定鍍上錄金層之區域；接著，如第 鎳金層23,並如第_，移除該光阻層&並钱刻掉該 1 銅層25，·最後，如第2G圖，敷設拒銲層24，並令^ 層24之開口 240外露出該電性連接部21〇之錦全層μ、干 =習知上由於形成拒銲層之開口有對位±75"之誤 .差限制，且該拒銲層之解析度誤差有約土5〇_，因此，兮 二金層，大小需略大於該拒銲層開口之大小，兩者間有： ^(7^+50㈣）的重疊區域L(如第2G圖所示）。 此二習知製法雖可免除電鑛導線之設計，改善習 2的電性問題1而，此二製法所形成之基板結構卻另有 、料上之問題。此因拒銲層與鎳金層間的附著性並不佳， 尤其對於基板上相鄰設置之電源環及接地環而言，如第3A 至3C圖所示，其中該第3B&3C圖係為對該第μ圖之不 同J面示％、圖„又於基板表面之拒銲層34係覆蓋於相鄰設 置之電源環361及接地環362上表面錄金層33之各別兩 侧’而外露出該電源環361及接地環362上表面錄金層Μ 中央邛刀，其中位於該電源環361及接地環中間處之 拒銲層34,部分（如$ 3B圖所示），因其兩邊均係各別覆蓋 於該電源環361及接地環362之鎳金層33上，因此很容易 自該，金層33上剝離，產生脫層現象，形成不良品。 是以，如何避免形成於基板電性連接部，尤為接地環 f電源環表面之鎳金層與覆蓋其上之拒銲層間產生脫層問 題，實為半導體相關領域中所亟待解決之課題。 【發明内容】 19593 7 200816416 . 因此，有鑑於前述及其他缺點，本發明之主要目的在 於提供一種避免鎳金層與覆蓋其上之拒銲層產生脫層之基 板結構及其製法。 —本龟明的又一目的在於提供一種可強化鎳金層與覆 盍其上之拒銲層接合力之基板結構及其製法。 :制、、為達成上述及其他目的，本發明所提出的基板結構之 :衣去，係包括：製備一芯層，該芯層表面形成有圖案化之 ㈣結構’且該線路結構中包含有導電環；於該芯層上覆 :阻層、其中该阻層係覆蓋住線路結構部分區域及導電 T邛刀區域，以顯露出該線路結構部分區域及導電環部分 區域，進而定義出預定鑛設區域；於該預定鑛設區域上形 成鎳金層；移除該阻層，以外露出未形成有鎳金層之部分 線路結構及部分導電環；以及於該芯層上覆蓋拒銲層，並 外露出該線路結構及導電環之鎳金層。 、透過剛速製法所製得之基板結構，_包括：芯層；形 •，Hu層上之圖案化線路結構，該線路結構包含有導電 :T ’、鎳金層，係形成於該線路結構部分區域及導電環部分 區域上，以及拒銲層，係敷設於該芯層及線路結構上，且 外露出該線路結構及導電環上之錄金層，其中該拒鲜層係 覆盍该線路結構及導電環中未形成有錄金層之區域。 B因此，相較習知製程中在例如t源環及接地環等導電 環上全面鍍覆鎳金層之方式，本發明即在該原本須完全 鎳孟層之‘私糸上，利用阻層留下至少一個區域未進行= "又錄金層’於外露出該阻層之導電環上It設鎳金層，接著 8 19593 200816416 = =、:：形成部分區域鑛有鎳金層及部分區域未鍍 有-桌孟層之h環，之後再於芯層及導電 之部分區域上敷設拒銲層，俾利賴銲層與 =本體的結合力大於拒銲層對形成於導電環上鎳金層的結 :力1免拒銲層與鎳金層間產生脫層問題，改善基板結 構之品質。 【實施方式】 以下係藉由特定的具體實例說明本發明之實施方 式，熟悉此技藝之人士可由本說明書所揭示之内容輕易地 瞭解本發明之其他優點與功效。 讀參閱第4A至4H圖，係為本發明之基板結構及其製 法之不意圖，如f 4A及4B圖所示’其中該第㈣係為對 應弟4A圖之剖面圖，首先，製備一芯層4〇，該芯層4〇可 為樹脂，該芯層40表面形成有圖案化之線路結 該線路結構41中包含有導電環411及其它導^跡線412 •及銲墊413’ *中，該導電環411係例如為電源環及接地 環等，且該線路結構41之導電環4n、導電跡線412及銲 墊413之材質係為金屬銅’接著利用如npl製法於其上覆 蓋一無電解電鍍之薄銅層（未圖示）。 〃 如第4C及4D圖所示，其中該第4D圖係為對應第4C 圖之剖面圖，於該芯層40上之薄銅層上覆蓋一阻層42， 其中該阻層4 2係覆蓋住線路結構41部分區域（如導θ電跡線 412)及導電環411部分區域，並顯露出該線路結構41部分 區域（如銲墊413)及導電環411部分區域，以定義出預定 19593 9 200816416 鐘設區域。 圖之及处圖所示，其中該第处圖係為對應第4E H’i面圖，㈣預定錄設區域上形成錄金層， 未為該阻層42所覆芸之“* x f μ 之¥電裱411部分區域及銲墊413 電鍍形成一鎳金層43,接荖卽s 掉該薄鋼層，以外露出未形:有:=a f4 2 ’並㈣ (如^ ώ 成有鎳金層43之部分線路結構 C如導電跡線412)及部分導電環411。 ”4G及4Η圖所示’其中該第4Η圖係為對應第π 面圖’之後於該芯層4〇上覆蓋拒鲜屬44，並外露 邊線路結構（如銲墊413)及導電環411之鎳金層“盆 導電環411而言，部分區域係形成有錄^層… 4刀區域則未敷設鎳金層，如此於形成該拒銲層料時，誃 ，銲層44將覆蓋至該導電環4ni未設有錄金層仏之區/ 域，俾透過該拒銲層44與導電環411本體（銅材質）之結合 度大於與鎳金層43之結合度，使該拒銲層44不易自診 金層43上剝離。 ^ v、 透過前述製法，本發明亦揭示一種基板結構，係包 括：芯層40;形成於該芯層4〇上之圖案化線路結構41， 該線路結構41包含有導電環411;鎳金層43,係^成於該 線路結構41及導電環⑴之部分區域上;以及拒銲層 係敷設於該芯層40及線路結構41上，且外露出該^路結 構41及導電環411上之鎳金層43，其中該拒銲層44係覆 蓋該導電環411中未形成有鎳金層43之區域。另該線路= 構41復包含有導電跡線412及銲墊413，其中該導電埽 19593 10 200816416 411、導電跡線412、及銲墊413之材質為金屬銅，且該導 電環411部分區域及銲墊413上係形成有鎳金層43。 因此，相較習知製程中在例如電源環及接地環等導電 環上全面鍍覆鎳金層之方式，I發明即在該原本須完全= 鎳金層之導電環上’利用阻層留下至少—㈣塊未進行^ 設鎳金層，以於外露出該阻層之導電環上鐘設鎳金層，^ 著移除該阻層’以形成部分區域鍍有錄金層及部分區域未 鍍有鎳金層之導電環，之後再於芯層及導電環未鍍設錄金 層之部分區域上敷設拒銲層，俾湘拒銲層與銅材質之導 電環本體的結合力大於拒銲層對形成於導電環上鎳金層的 結合力’避免拒銲層自該鎳金層上發生剝離問題，改善美 板結構之品質。 ^ 以上所述僅為本發明之較佳實施方式而已，並非用以 限疋本U之® ’亦即，本發明事實上仍可做其他改變， 此’〜舉凡熟f該項技術者在未麟本發明所揭示之精神 1術思想下所完成之—切等效修飾錢變，仍應由後述 之申請專利範圍所涵蓋。 【圖式簡單說明】 ςη·弟1八至則係習知之選擇性電鍍（Selected Gold， SG)製法之示意圖； \ τ .第2A至2G圖係習知之無電鍍線鍍鎳金（Mon Plating Llne，~NPL)製法之示意圖； 弟3A至3C圖将羽丄^發 a 一立 口係白知之基板結構中電源環及接地環區 域不意圖；以及 19593 11 200816416 ^ 第4A至4H圖係本發明之基板結構及其製法示意圖 【主要元件符號說明】 10 芯層 11 銅層 110 電性連接部 .12 光阻層 120 開口 13 鎳金層 • 14 拒銲層 140 開口 20 芯層 21 銅層 210 電性連接部 22 光阻層 220 開口 ^ 23 鎳金層 / 24 拒銲層 :240 開口 、25 薄銅層 33 鎳金層 34, 34, 拒銲層 361 電源環 362 接地環 40 芯層 12 19593 200816416 41 線路結構 411 導電環 412 導電跡線 413 銲墊 42 阻層 43 鎳金層 44 拒鲜層200816416 • Nine, invention description: violent V [Technical field to which the invention pertains] The present invention relates to a semiconductor process, and more particularly to a substrate structure applied to a semiconductor package and a method of fabricating the same. [Prior Art] • For Ball Grid (BGA) semiconductor packages with a substrate as a wafer carrier, the signal transmission design often uses the design of the substrate to transmit the signal of the wafer through the bonding wire. The finger that is transferred to the substrate is transferred to the bottom surface of the substrate through the conductive via of the substrate! a ball pad (Ball Pad) is transmitted to the outside through a solder ball implanted on the solder ball pad, and a power ring is provided on the substrate to enhance and maintain the electrical power of the package. And a ground ring for electrically connecting the wafer to the power ring and the grounding ring through the bonding wire, as disclosed in US Pat. No. 5,581,122. The welding finger, welding consumables, power supply ring and grounding ring of the secret board are generally made of copper shoulder material. In order to provide the welding wire or solder ball and the power ring of the substrate, the grounding welding solder ball mat is well followed, and at the same time protect The power ring, grounding ring, and the ball mat are protected from external environmental pollution. Usually, the nickel/gold layer (Ni/Au) is covered on the surface of the power supply. The grounding %, the zinc finger and the solder ball pad. However, the conventional method for forming a nickel-gold layer has the disadvantage that the surface of the substrate must be additionally clothed, and most of the electroplated wires are used to perform the steps of recording the gold layer by the electric clock; therefore, for the substrate of the south density, the design has insufficient substrate area. In addition, 'for high-frequency products, these electric money wires will form an antenna effect' and there will be noise, which will also interfere with the transmission of signal 19593 5 200816416, so this structure has gradually become inconsistent with today's products. need. In order to solve this problem, the industry has developed two substrates that do not require electroplated wires, including selective plating (SG) and non-electroplating line (Non Piating Line, NPL). The process flow and the formed substrate structure are described. For the SG process, the first step is to form a copper layer (CuFoil) 11 on the substrate core layer 1 as shown in FIG. 1A, and as defined in the first BB, the photoresist layer 12 is used to define the copper layer π. For example, the power supply ring, the grounding ring, the welding finger, and the opening 12 of the solder ball pad f electrical connection portion; then, as in the 1st C, the gold layer 13' is forged in the 浐= opening 120. 13 of the lithography surface 2 = the opening 120 of the photoresist layer 12 has the same area; again as in the 1D figure, ::: = layer 12 'and then 'as shown in FIG. 1E' to pattern the copper layer ^ conductive trace, power ring, The electrical connection portion 110 of the grounding ring, the welding finger and the solder ball pad, and the solder resist layer 14 are disposed, and the area of the opening opening 140 exposing the electrical m14 of the recorded gold layer 13 is slightly smaller than the nickel gold. The surface of the layer m is such that the anti-friction layer 14 covers the periphery of the nickel-gold layer 13 on the portion 110. For the NPL method, a copper layer 2 is formed on the 2a layer 20, and as shown in FIG. 2B, the copper layer 21 is patterned on the substrate core and defined as electricity, and the exposure is developed. And the solder ball pad isoelectric connection portion 21 (); then, such as /, ground = front finger such as the use of electroless plating of the thin copper layer 25, then 2C diagram 'covering - the example layer 22 to utilize the photoresist layer 22's opening 22〇jFig. 'Forming a photoresist' to make the electrical connection 19593 6 200816416 • The area where the gold layer is to be plated; then, as the nickel-gold layer 23 The photoresist layer & and the 1 copper layer 25 is removed. Finally, as shown in FIG. 2G, the solder resist layer 24 is applied, and the opening 240 of the layer 24 is exposed to expose the electrical connection portion 21 Layer μ, dry = conventionally, due to the formation of the solder resist layer, the opening has a ±75" error, and the resolution error of the solder resist layer is about 5 〇 _, therefore, the bismuth layer, The size needs to be slightly larger than the size of the solder resist layer opening, and there is an overlap region L of ^(7^+50(4)) (as shown in Fig. 2G). Although the two conventional methods can eliminate the design of the electric ore wire and improve the electrical problem of the conventional electrode 1 , the substrate structure formed by the second method has another problem. The adhesion between the solder resist layer and the nickel-gold layer is not good, especially for the adjacent power supply ring and ground ring on the substrate, as shown in Figures 3A to 3C, wherein the 3B&3C is The different J faces of the μth diagram show %, and the solder resist layer 34 on the substrate surface covers the respective sides of the gold layer 33 on the upper surface of the power supply ring 361 and the ground ring 362. The power ring 361 and the grounding ring 362 are exposed on the upper surface of the gold layer 邛 central trowel, wherein the solder resist layer 34 at the middle of the power ring 361 and the ground ring is partially (as shown in FIG. 3B), because of its two sides Each of them is covered on the nickel-gold layer 33 of the power ring 361 and the grounding ring 362, so that it is easy to peel off from the gold layer 33, and a delamination phenomenon occurs to form a defective product. Therefore, how to avoid formation on the substrate The electrical connection portion, in particular, the problem of delamination between the nickel-gold layer on the surface of the power ring of the grounding ring and the solder-resisting layer covering the ground ring is a problem to be solved in the field of semiconductors. [Abstract] 19593 7 200816416 In view of the foregoing and other shortcomings, the main object of the present invention The invention provides a substrate structure for avoiding delamination of a nickel gold layer and a solder resist layer covering the same, and a method for preparing the same. - Another objective of the present turtle is to provide a nickel-gold layer and a solder resist layer thereon The substrate structure of the bonding force and the method of manufacturing the same. The substrate structure of the present invention is: a coating, the core layer is formed with a pattern (4) The structure includes a conductive ring; the core layer is overlying: a resist layer, wherein the resist layer covers a portion of the line structure and the conductive T trowel region to expose a portion of the line structure and conduct electricity a partial region of the ring, thereby defining a predetermined mineralized region; forming a nickel-gold layer on the predetermined mineralized region; removing the resistive layer to expose a portion of the wiring structure and a portion of the conductive ring in which the nickel-gold layer is not formed; and The core layer is covered with a solder resist layer, and the nickel structure of the circuit structure and the conductive ring is exposed. The substrate structure obtained by the rigid speed method comprises: a core layer; a shape, a patterned line on the Hu layer Knot The circuit structure comprises a conductive: T', a nickel-gold layer formed on a portion of the circuit structure and a portion of the conductive ring, and a solder resist layer disposed on the core layer and the line structure, and the outer layer is exposed a circuit structure and a gold layer on the conductive ring, wherein the anti-friction layer covers the line structure and a region in the conductive ring where no gold layer is formed. B. Therefore, compared with the conventional process, for example, the t source ring and The method of uniformly plating a nickel-gold layer on a conductive ring such as a grounding ring, the present invention is to use the resist layer to leave at least one region uncompleted on the 'private layer of the nickel layer to be completely completely = "and gold layer On the conductive ring on which the resist layer is exposed, it is provided with a nickel-gold layer, and then 8 19593 200816416 = =, :: a partial region is formed with a nickel-gold layer and a portion of the region is not plated with a h-ring of the table, and then A solder resist layer is disposed on the core layer and the conductive portion, and the bonding force between the solder layer and the body is greater than the solder layer to the nickel gold layer formed on the conductive ring: force 1 between the solder layer and the nickel layer A problem of delamination is produced to improve the quality of the substrate structure. [Embodiment] The embodiments of the present invention are described below by way of specific examples, and those skilled in the art can readily understand other advantages and effects of the present invention from the disclosure of the present disclosure. Refer to Figures 4A to 4H for the purpose of the substrate structure of the present invention and its method of manufacture, as shown in Figures f 4A and 4B, wherein the fourth (4) is a cross-sectional view corresponding to the 4A diagram. First, a core is prepared. The core layer 4 〇 may be a resin, and the surface of the core layer 40 is formed with a patterned circuit junction. The circuit structure 41 includes a conductive ring 411 and other conductive traces 412 • and a solder pad 413 ′ The conductive ring 411 is, for example, a power ring and a grounding ring, and the conductive ring 4n, the conductive trace 412, and the pad 413 of the circuit structure 41 are made of metal copper, and then covered with a method such as npl. A thin copper layer (not shown) that is electrolessly plated. As shown in FIGS. 4C and 4D, wherein the 4D image is a cross-sectional view corresponding to FIG. 4C, a thin copper layer on the core layer 40 is covered with a resist layer 42, wherein the resist layer 42 is covered. A portion of the line structure 41 (such as the conductive θ electrical trace 412) and a portion of the conductive ring 411 are partially exposed, and a portion of the line structure 41 (such as the pad 413) and a portion of the conductive ring 411 are exposed to define a predetermined 19593 9 200816416 Clock setting area. As shown in the figure, the figure is corresponding to the 4E H'i surface, and (4) the gold layer is formed on the predetermined recording area, and the "* xf μ" is not covered by the resist layer 42. A portion of the electrode 411 and the pad 413 are plated to form a nickel-gold layer 43 which is smashed away from the thin steel layer and exposed to an unshaped shape: yes: = a f4 2 'and (four) (eg ^ ώ into nickel gold A part of the line structure C of the layer 43 is as a conductive trace 412) and a part of the conductive ring 411. "The 4th and 4th drawings show that the fourth picture is corresponding to the πth surface view" and is overlaid on the core layer 4 The fresh genus 44, and the exposed side line structure (such as the pad 413) and the nickel-gold layer of the conductive ring 411 "the basin conductive ring 411, part of the area is formed with a recording layer ... 4 knives area is not laid nickel gold layer, When the solder resist layer is formed, the solder layer 44 covers the region/domain where the conductive layer 4ni is not provided with the gold layer, and the solder resist layer 44 and the conductive ring 411 body (copper material) are passed through the conductive layer 4ni. The degree of bonding is greater than the degree of bonding with the nickel-gold layer 43, so that the solder resist layer 44 is not easily peeled off from the diagnostic gold layer 43. ^ v. Through the foregoing method, the present invention also discloses a substrate structure The system includes: a core layer 40; a patterned circuit structure 41 formed on the core layer 4, the circuit structure 41 includes a conductive ring 411; a nickel-gold layer 43 is formed on the circuit structure 41 and the conductive ring (1) And a solder resist layer is disposed on the core layer 40 and the line structure 41, and the nickel-gold layer 43 on the circuit structure 41 and the conductive ring 411 is exposed, wherein the solder resist layer 44 covers the layer A region of the nickel-gold layer 43 is not formed in the conductive ring 411. The circuit 41 includes a conductive trace 412 and a pad 413, wherein the conductive pad 19593 10 200816416 411, the conductive trace 412, and the pad 413 The material is metal copper, and a nickel-gold layer 43 is formed on a portion of the conductive ring 411 and the pad 413. Therefore, nickel plating is completely plated on a conductive ring such as a power ring and a ground ring in a conventional process. In the form of a layer, the invention of the invention is to use at least a portion of the conductive ring of the nickel-gold layer to leave at least a layer of nickel and gold on the conductive ring of the resistive layer. A nickel-gold layer is provided, and the resist layer is removed to form a partial region plated with a gold layer and a portion of the region is unplated a conductive ring of a nickel-gold layer, and then a solder resist layer is disposed on a portion of the core layer and the conductive ring that is not plated with a gold layer, and the bonding force between the Xiaoxiang solder resist layer and the copper-based conductive ring body is greater than that of the solder resist layer The bonding force of the nickel-gold layer formed on the conductive ring 'avoids the problem of peeling of the solder resist layer from the nickel-gold layer, improving the quality of the beautiful structure. ^ The above is only a preferred embodiment of the present invention, and is not used In other words, the present invention can still make other changes, which is done by the person who knows the skill of the invention. The effect of modifying the money should still be covered by the scope of the patent application described later. [Simple description of the diagram] ςη·弟1八至 is a schematic diagram of the conventional selective plating method (Selected Gold, SG); \ τ . 2A to 2G is a conventional electroless plating line nickel-plated gold (Mon Plating Llne , ~NPL) schematic diagram of the method; brother 3A to 3C diagram will be feathered ^ a a mouthpiece Bai Zhizhi substrate structure in the power ring and ground ring area is not intended; and 19593 11 200816416 ^ 4A to 4H diagram of the present invention Schematic diagram of substrate structure and its manufacturing method [Description of main components] 10 core layer 11 copper layer 110 electrical connection part. 12 photoresist layer 120 opening 13 nickel gold layer • 14 solder resist layer 140 opening 20 core layer 21 copper layer 210 Contact layer 22 photoresist layer 220 opening ^ 23 nickel gold layer / 24 solder resist layer: 240 opening, 25 thin copper layer 33 nickel gold layer 34, 34, solder resist layer 361 power ring 362 ground ring 40 core layer 12 19593 200816416 41 line structure 411 conductive ring 412 conductive trace 413 pad 42 resist layer 43 nickel gold layer 44 reject layer