200901419 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種封裝基板表面結構及其製法，尤指 一種適用於高應力之封裝基板或細間距之金屬凸塊的設計 5 之封裝基板表面結構及其製法。 【先前技術】 f 隨著電子產業的蓬勃發展，電子產品亦逐漸進入多功 能、高性能的研發方向。為滿足半導體封裝件高積集度 10 (Integrati〇n)以及微型化（Miniaturization)的封裝要求，提供 夕數主被動元件及線路連接之封裝基板，亦逐漸由單層板 演變成多層板，以使在有限的空間下，藉由層間連接技術 (Interlayer connection)擴大封裝基板上可利用的佈線面積 而配合尚電子在、度之積體電路（Integrated circuit)需求。 15 一般半導體裝置之製程，首先係由晶片載板製造業者 生產適用於該半導體裝置之晶片載板，如基板或導線架。 之後再將該些晶片載板交由半導體封裝業者進行置晶、壓 模、以及植球等製程，又一般半導體封裝結構是將半導體 晶片背面黏貼於基板頂面，進行打線接合（wire ， 20或將半導體晶片主動面以覆晶接合（Flip chip)方式與基板 電性連接，再於基板之背面植以錫球以供與另一電子裝置 進行電性連接。 ~ 習知的封裝基板的表面結構的製法，請見圓以至圖 1F。如圖1A所示，包括一基板10,該基板10的表面具有複 5 200901419 數電性連接墊Η並具有一防焊層12，該防焊層12具有複數 開孔120以顯露該些電性連接墊12。再者，如圖1B所示，於 此基板ίο表面先形成一導電層（seed layer)13。再如圖⑴所 示，形成一阻層14，該阻層14具有複數阻層開孔14〇對應於 5 該些防焊層開孔12〇。接著，如圖1D所示，於阻層開孔14〇 電鍍形成金屬凸塊15，其材料可為銅等金屬。然後，如圖 1E所示，再移除阻層14及覆蓋於其下之導電層13。繼之， 如圖1F所示，於金屬凸塊15表面形成一焊料凸塊（8〇1(1打 bump)16 ° 10 上述結構中，該烊料凸塊16可經由迴焊（refl〇w soldering)以提供與一晶片進行覆晶接合（FHp chip)，該封裝 方式中，當封裝基板表面結構線寬及線距縮短時，因接點 強度亦隨著接點尺寸而縮小，接點強度不足以承受晶片與 基板間的剪應力（shear st簡）而產生接點（j()int)斷裂的現 15象將更加顯著。另—方面，若防焊層的開孔形狀不佳或是 開孔内之電性連接墊表面的清潔不足時’金屬凸塊對於防 焊層或是電性連接墊會有結合力不足的問題產生。 【發明内容】 20 有鑑於此，本發明之主要目的係在提供一種封裝基板 表面結構及其製法，俾能使金屬凸塊與防焊層之間更^有 結合力，可應用於高應力之封裝基板設計，或細凸塊焊墊 間距之封裝基板設計。 為達成上述目的，本發明提供一種封裝基板表面結 200901419 構包括.-基板，其表面具有複數電性連接塾及一防焊 層，該防焊層具有複數開孔以顯露該些電性連接塾；一介 電環’係配置於該些開孔内壁且延伸至開孔週緣該防谭層 部分表面’·以及-金屬凸塊’係配置於該些開孔及其顯露 之電性連接墊表面上，並與該介電環接合。 本發明之封裝基板表面結構，復可包括一谭料凸塊， 係形成於該金屬凸塊之表面。 Ο 10 月j述之、i可包括—金屬接著層，係、形成於該金 屬凸塊表面及該焊料凸塊之間。 本發明復提供-種封裝基板表面結構之製法，其步驟 ^提供一基板，其表面具有複數電性連接墊及一防焊層， 該防焊層具有複數開孔以顯露該些電性連接塾；於該些開 孔内壁及延伸至開孔週緣之防焊層部分表面上形成一介電 15環；於形成該介電環之該基板表面形成一導電層；於該導 電層表面形成-阻層，該阻層於對應該防焊層之開孔處形 成複數阻層開孔；於該些阻層開孔内電鍍形成一金屬凸 塊；以及移除該阻層及覆蓋於其下之導電層。 述之製法’復可包括於該金屬凸塊表面形一 20 凸塊。 上述之製法，復可包括於形成該焊料凸塊前，於該金 屬凸塊表面形成一金屬接著層。 上述之製法中’該介電環係經由壓合—感光性介電層於 该基板表面後，再以曝光以及顯影之方式形成。或者，該 7 200901419 再以曝光 介電環係塗佈一感光性介電層於該基板表面後 以及顯影之方式形成。 【實施方式】 二下係藉由特定的具體實施例說明本發明之實施 式’熟習此技藝之人士可由本說明書所揭示之内容輕：地 了解本發明之其他優點與功效。本發明亦可藉由其他不同 〇 的具體實施例加以施行或應用，本朗書中的各項細節亦 可基於不同觀點與應用，在不悖離本發明之精神下進行各 種修飾與變更。 製法實施例 首先，請見圖2A，提供一基板20,其表面具有複數電 性連接墊21及一防焊層22,該防焊層22具有複數開孔22〇以 顯露該些電性連接墊21。在此，電性連接墊21的材料為銅、 15錫、鎳、鉻、鈦、銅-鉻合金以及錫-鉛合金中所組成之群組 其中之一者，本實施例則使用銅。 接著，請見圖2B，壓合一感光性介電層23於該基板2〇 表面。或者’塗佈感光性介電層23於該基板表面2〇。然後， 凊見圖2C，再以曝光以及顯影之方式，於該些開孔22〇内壁 20 及延伸至開孔220週緣之防焊層22部分表面上形成一介電 環 231。 在本實施例中的介電環231係可為一感光性介電材 料。此感光性介電材料可選自BCB(benzocylobuthene)、雙 順丁酿二酸酿亞胺/三氛陕（BT，Bismaleimidetriazine)、液 200901419 晶聚合物（Liquid Crystal Polymer)、PI(Poly- imide)、聚乙 稀 (Poly(phenylene ether))、聚四氟乙稀（Poly (tetra-fluoroethylene))、芳香尼龍（Aramide)、環氧樹脂以及玻璃 纖維所組成之群組等等。 5 繼之，請見圖2D，於形成該介電環231之該基板20表面 利用無電電鍍形成一導電層24。 再者，請見圖2E，於該導電層24表面形成一阻層25， 該阻層25於對應該防焊層22之開孔220處形成複數阻層開 孔250。其中，阻層25係可為乾膜或液態光阻，而在本實施 10 例中係使用乾膜。 接著，請見圖2F，於該些阻層開孔250内電鍍形成一 金屬凸塊2 6。該金屬凸塊2 6使用的材料係選自銅、錄、鉻、 鈦、銅/鉻合金以及錫/鉛合金所組成之群組之一者，在本實 施例中係為銅。最後，請見圖2G，移除該阻層25及覆蓋於 15 其下之導電層24。 上述之製法中，請見圖2H，復包括於金屬凸塊26表面 形成一焊料凸塊28。此外，復可於形成焊料凸塊28前，於 該金屬凸塊26表面形成一金屬接著層27。其中，可利用物 理沉積（例如濺鍍或蒸鍍）或化學沉積（例如無電電鍍）方式 20 之一者形成該金屬接著層27。而該金屬接著層27使用的材 料係選自錫、銀、鎳、金、鉻/鈦、錄/金、錄/纪與鎳/4巴/ 金所組成群組其中之一者，本實施例則使用錫。 結構實施例 本實施例如圖2G所示，係本發明提供之一種封裝基板 9 200901419 表面結構，包括：-基板20，其表面具有複數電性連接塾 2!及-防焊層22,該防嬋層22具有複數開孔22〇以顯露該些 電性連接墊2i ; -介電環231，係配置於該些開孔22〇内壁 且延伸至開孔20週緣該防焊層22部分表面；以及一金屬巧 5塊26’係配置於該㈣孔22q及其顯露之電性連接仙表面 上’並與該介電環231接合。 、上述之結構，請見圖2^!，復包括—焊料凸塊Μ，係形 〇 成於該金屬凸塊26之表面。此外，復包括-金屬接著層27， 係形成於該金屬凸塊26表面及該焊料凸塊28之間。其中， 1〇該金屬凸塊26使用的材料係選自銅、鎳、鉻、鈦、銅/鉻合 金以及錫⑽合金靠成之輕之—者，在本實施例中係^ 銅。該金屬接著層27使用的材料係選自錫、銀、鎳、金、 鉻/鈦、鎳/金、鎳/鈀與鎳/鈀/金所組成群組其中之一者，在 本實施例中則使用錫。 15 综上所述，本發明之封裝基板表面結構及其製法， 主要在利用金屬凸塊與防焊層之間形成一感光性之介電材 6 肖所形成之介電環，以提升金屬凸塊與防焊層之間的結合 力’解決了習知技術中金属凸塊與防焊層以及電性連接塾 ，間結合力不佳的情形，可應用於高應力之封裝基板設 20 計，或細凸塊焊墊間距之封裝基板設計。 上述實施例僅係為了方便說明而舉例而已，本發明所 主張之權利範圍自應以申請專利範圍所述為準，而非僅限 於上述實施例。 义 200901419 【圖式簡單說明】 圖1A至1F係習知之封裝基板表面結構製作流程剖視 圖。 圖2A至2H係本發明一較佳實施例之封裝基板表面結 構製作流程剖視圖。 【主要元件符號說明】 11，21 電性連接墊 120,220 開孔 14.25 阻層 15.26 金屬凸塊 23 感光性介電層 27 金屬接著層 ^ 1()，2〇 基板 12,22 防焊層 13,24 導電層 14〇,250阻層開孔 16,28 焊料凸塊 231 介電環200901419 IX. Description of the Invention: Technical Field of the Invention The present invention relates to a surface structure of a package substrate and a method of fabricating the same, and more particularly to a package substrate surface suitable for a high stress package substrate or a fine pitch metal bump design 5 Structure and its method of production. [Prior Art] f With the rapid development of the electronics industry, electronic products have gradually entered the direction of multi-functional and high-performance research and development. In order to meet the packaging requirements of semiconductor package high integration degree 10 and miniaturization, the package substrate with the main active and passive components and the line connection is gradually evolved from a single layer board to a multi-layer board. In a limited space, the interlayer area available on the package substrate is expanded by an interlayer connection technology to meet the demand for an integrated circuit. 15 The general semiconductor device process begins with a wafer carrier manufacturer producing a wafer carrier, such as a substrate or leadframe, suitable for the semiconductor device. Then, the wafer carrier boards are transferred to a semiconductor package manufacturer for processing such as crystallization, stamping, and ball implantation. In general, the semiconductor package structure is to adhere the back surface of the semiconductor wafer to the top surface of the substrate for wire bonding (wire, 20 or The active surface of the semiconductor wafer is electrically connected to the substrate by flip chip bonding, and the solder ball is implanted on the back surface of the substrate for electrical connection with another electronic device. ~ The surface structure of the conventional package substrate For the manufacturing method, please refer to the circle and FIG. 1F. As shown in FIG. 1A, the substrate 10 includes a substrate 10 having a surface of a plurality of 200901419 electrical connection pads and having a solder resist layer 12 having the solder resist layer 12 The plurality of openings 120 are formed to expose the electrical connection pads 12. Further, as shown in FIG. 1B, a conductive layer 13 is formed on the surface of the substrate ί. A resist layer is formed as shown in FIG. 14. The resist layer 14 has a plurality of resistive opening 14 〇 corresponding to the plurality of solder resist openings 12 〇. Next, as shown in FIG. 1D, a metal bump 15 is formed on the resist opening 14 , The material can be a metal such as copper. Then, as shown in Figure 1E And removing the resist layer 14 and the conductive layer 13 covering the underlying layer. Then, as shown in FIG. 1F, a solder bump is formed on the surface of the metal bump 15 (8〇1 (1 dozen bump) 16 ° 10 In the structure, the solder bumps 16 can be flip-chip bonded to provide FH chip with a wafer. When the package substrate surface line width and line pitch are shortened, Because the contact strength is also reduced with the contact size, the joint strength is not enough to withstand the shear stress between the wafer and the substrate, and the current image of the joint (j()int) is more pronounced. On the other hand, if the shape of the opening of the solder resist layer is not good or the surface of the electrical connection pad in the opening is insufficiently cleaned, the metal bump may have insufficient bonding force to the solder resist layer or the electrical connection pad. [Problem of the Invention] In view of the above, the main object of the present invention is to provide a surface structure of a package substrate and a method for fabricating the same, which can provide a bonding force between the metal bump and the solder resist layer, and can be applied to High-stress package substrate design, or fine bump pad pitch package In order to achieve the above object, the present invention provides a package substrate surface junction 200901419 comprising a .-substrate having a plurality of electrical connections on the surface thereof and a solder mask having a plurality of openings for revealing the electricity. a dielectric ring is disposed on the inner wall of the opening and extends to the periphery of the opening. The surface of the anti-tank layer is disposed on the surface of the anti-tank layer and the metal bumps are disposed on the openings and the exposed electrical properties thereof. Bonding the surface of the pad and bonding with the dielectric ring. The surface structure of the package substrate of the present invention may include a tan bump formed on the surface of the metal bump. Ο October, i may include a metal bonding layer formed between the surface of the metal bump and the solder bump. The present invention provides a method for fabricating a surface structure of a package substrate, the step of providing a substrate having a plurality of electrical connection pads and a solder resist layer on the surface thereof, the solder resist layer having a plurality of openings to expose the electrical connections Forming a dielectric 15 ring on the inner wall of the opening and the surface of the solder resist layer extending to the periphery of the opening; forming a conductive layer on the surface of the substrate forming the dielectric ring; forming a resistance on the surface of the conductive layer a layer, the resist layer forms a plurality of resistive opening at an opening corresponding to the solder resist layer; plating a metal bump in the opening of the resist layer; and removing the resist layer and conducting the conductive layer thereunder Floor. The method of manufacturing may include forming a 20-bump on the surface of the metal bump. The above method may include forming a metal bonding layer on the surface of the metal bump before forming the solder bump. In the above method, the dielectric ring is formed on the surface of the substrate via a press-photosensitive dielectric layer, followed by exposure and development. Alternatively, the 7 200901419 is formed by applying a photosensitive dielectric layer to the surface of the substrate and developing it. [Embodiment] The embodiments of the present invention are described by way of specific embodiments. Those skilled in the art can understand the other advantages and effects of the present invention. The present invention may be embodied or applied in various other specific embodiments, and various modifications and changes can be made without departing from the spirit and scope of the invention. First, please refer to FIG. 2A, a substrate 20 having a plurality of electrical connection pads 21 and a solder resist layer 22 having a plurality of openings 22 to expose the electrical connection pads. twenty one. Here, the material of the electrical connection pad 21 is one of a group consisting of copper, 15 tin, nickel, chromium, titanium, a copper-chromium alloy, and a tin-lead alloy. In this embodiment, copper is used. Next, as shown in FIG. 2B, a photosensitive dielectric layer 23 is pressed onto the surface of the substrate 2. Alternatively, the photosensitive dielectric layer 23 is coated on the surface of the substrate. Then, as shown in FIG. 2C, a dielectric ring 231 is formed on the inner wall 20 of the opening 22 and the surface of the solder resist 22 extending to the periphery of the opening 220 by exposure and development. The dielectric ring 231 in this embodiment can be a photosensitive dielectric material. The photosensitive dielectric material may be selected from the group consisting of BCB (benzocylobuthene), bis, BT (Bismaleimidetriazine), liquid 200901419 Liquid Crystal Polymer, PI (Poly-imide) , Poly(phenylene ether), Poly (tetra-fluoroethylene), Aramide, Epoxy, and glass fiber groups, and the like. 5 Next, as shown in Fig. 2D, a conductive layer 24 is formed by electroless plating on the surface of the substrate 20 on which the dielectric ring 231 is formed. Moreover, as shown in FIG. 2E, a resist layer 25 is formed on the surface of the conductive layer 24, and the resist layer 25 forms a plurality of resistive opening 250 at the opening 220 corresponding to the solder resist layer 22. Among them, the resist layer 25 may be a dry film or a liquid photoresist, and in the present embodiment 10, a dry film is used. Next, as shown in FIG. 2F, a metal bump 26 is electroplated in the barrier openings 250. The material used for the metal bumps 26 is selected from the group consisting of copper, chrome, chromium, titanium, copper/chromium alloys, and tin/lead alloys, and in this embodiment is copper. Finally, please refer to FIG. 2G to remove the resist layer 25 and the conductive layer 24 covering the underlying layer 15. In the above manufacturing method, as shown in Fig. 2H, a solder bump 28 is formed on the surface of the metal bump 26. In addition, a metal back layer 27 is formed on the surface of the metal bump 26 before the solder bumps 28 are formed. Among them, the metal back layer 27 can be formed by one of physical deposition (e.g., sputtering or evaporation) or chemical deposition (e.g., electroless plating). The material used in the metal back layer 27 is selected from the group consisting of tin, silver, nickel, gold, chromium/titanium, recorded/gold, recorded/kid, and nickel/4 bar/gold. Then use tin. The embodiment of the present invention, as shown in FIG. 2G, is a package substrate 9 200901419 surface structure provided by the present invention, comprising: a substrate 20 having a plurality of electrical connections 塾2! and a solder resist layer 22 on the surface thereof. The layer 22 has a plurality of openings 22 to expose the electrical connection pads 2i; a dielectric ring 231 disposed on the inner walls of the openings 22 and extending to a portion of the surface of the solder mask 22 around the opening 20; A metal 5 piece 26' is disposed on the (four) hole 22q and its exposed electrical connection surface and engages with the dielectric ring 231. The structure described above is shown in Fig. 2^!, and includes a solder bump Μ which is formed on the surface of the metal bump 26. In addition, a complex metal-containing layer 27 is formed between the surface of the metal bump 26 and the solder bump 28. Wherein, the material used for the metal bumps 26 is selected from the group consisting of copper, nickel, chromium, titanium, copper/chromium alloys, and tin (10) alloys, which in the present embodiment is copper. The material used for the metal back layer 27 is selected from the group consisting of tin, silver, nickel, gold, chromium/titanium, nickel/gold, nickel/palladium, and nickel/palladium/gold, in this embodiment. Then use tin. In summary, the surface structure of the package substrate of the present invention and the method for fabricating the same are mainly used to form a dielectric ring formed by a photosensitive dielectric material 6 between the metal bump and the solder resist layer to enhance the metal bump. The bonding force between the block and the solder resist layer solves the problem that the bonding force between the metal bump and the solder resist layer and the electrical connection port in the prior art is poor, and can be applied to a high stress package substrate. Or package substrate design with fine bump pad spacing. The above-described embodiments are merely examples for the convenience of the description, and the scope of the claims is intended to be limited by the scope of the claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A to FIG. 1F are cross-sectional views showing a process of fabricating a surface structure of a package substrate. 2A to 2H are cross-sectional views showing a process of fabricating a surface structure of a package substrate in accordance with a preferred embodiment of the present invention. [Main component symbol description] 11,21 Electrical connection pad 120, 220 Opening hole 14.25 Resistive layer 15.26 Metal bump 23 Photosensitive dielectric layer 27 Metallization layer ^ 1 (), 2 〇 substrate 12, 22 Solder mask 13, 24 Conductive layer 14〇, 250 resistive opening 16, 28 solder bump 231 dielectric ring