TWI333265B - Window manufacture method of semiconductor package type printed circuit board - Google Patents
Window manufacture method of semiconductor package type printed circuit board Download PDFInfo
- Publication number
- TWI333265B TWI333265B TW095135043A TW95135043A TWI333265B TW I333265 B TWI333265 B TW I333265B TW 095135043 A TW095135043 A TW 095135043A TW 95135043 A TW95135043 A TW 95135043A TW I333265 B TWI333265 B TW I333265B
- Authority
- TW
- Taiwan
- Prior art keywords
- circuit board
- printed circuit
- mask
- finger
- semiconductor package
- Prior art date
Links
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
- H05K3/241—Reinforcing the conductive pattern characterised by the electroplating method; means therefor, e.g. baths or apparatus
- H05K3/242—Reinforcing the conductive pattern characterised by the electroplating method; means therefor, e.g. baths or apparatus characterised by using temporary conductors on the printed circuit for electrically connecting areas which are to be electroplated
-
- H10W70/60—
-
- H10W70/05—
-
- H10W70/68—
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0137—Materials
- H05K2201/0166—Polymeric layer used for special processing, e.g. resist for etching insulating material or photoresist used as a mask during plasma etching
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
- H05K3/061—Etching masks
- H05K3/064—Photoresists
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
-
- H10W42/20—
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Electroplating Methods And Accessories (AREA)
- Wire Bonding (AREA)
Description
1333265 九、發明說明: 【發明所屬之技術領域】 針對半導體封裝用印刷電路板之製造方法,本發明涉及一 種半導體封裝用印刷電路板之窗口加工方法,通過在單面、雙 • 面、多層(Multi Layer)產品上下整體敷銅之基板上,通過顯影、 • 蝕刻及剝離形成電路,在除上述形成之電路之指狀焊片與焊盤 之外之部分形成絕緣層,通過鍍金用導線,在上述指狀焊片與 焊盤上鍍金形成鍍金/鍍鎳層,為去除在上述鍍金用導線及槽口 • 加工發生之金屬毛刺,在上述指狀焊片部分進行遮蓋後,進行 布線及剝離,從而能夠消除上述指狀焊片之金屬毛刺造成之電 氣乾擾,提高可靠性。 【先前技術】 圖一涉及以往半導體封裝用印刷電路板之製造方法。如上 述圖一所示,以往方法包括如下幾個步驟:顯影步驟,在敷銅 基板兩面壓附乾膜,除將形成指狀焊片之部分外,其餘部分均 暴露於外部。蝕刻步驟,去除在上述顯影步驟中暴露於外部之 鲁部分之銅’形成指狀焊片。退膜步驟,在上述银刻步驟中形成 指狀焊片後,去除上述壓附之乾膜。阻焊塗布步驟,使除通過 上述退膜步驟所形成之指狀焊片與焊盤之外之所有區域絕緣。 " 鍍金/鍍鎳步驟,在上雜㈣布步财暴露之指狀焊片與焊般 進行電鍍,形成鍍金/鍍鎳層。布線步驟,在上述鍵金/鍵^ 驟中進行鍍金後,加工形成印刷電路板之外形及槽口。 對於通過如上方法製造之半導體封裝件⑸1333265 IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a method of manufacturing a printed circuit board for a semiconductor package, which is processed by a single-sided, double-sided, multi-layer ( Multi Layer) On the substrate on which the whole copper is applied, the circuit is formed by development, etching, and stripping, and an insulating layer is formed on the portions other than the finger pads and the pads of the circuit formed above, and the wires are plated with gold. The finger-shaped soldering piece and the pad are plated with gold to form a gold-plated/nickel-plated layer, and the metal burr generated by the wire-plating wire and the notch is removed, and the finger-shaped pad portion is covered, and wiring and peeling are performed. Therefore, the electrical interference caused by the metal burrs of the finger pads can be eliminated, and the reliability can be improved. [Prior Art] FIG. 1 relates to a method of manufacturing a conventional printed circuit board for semiconductor packaging. As shown in Fig. 1 above, the conventional method includes the following steps: a developing step of pressing a dry film on both sides of a copper-clad substrate, except that a portion where the finger-shaped soldering piece is to be formed is exposed to the outside. The etching step removes the copper er which is exposed to the outer portion of the developing portion in the above developing step to form a finger-shaped soldering piece. In the film-removing step, after the finger-shaped soldering piece is formed in the silver etching step, the pressed dry film is removed. The solder resist coating step insulates all of the regions except the finger pads formed by the above-described film-removing step from the pads. " Gold-plated/nickel-plated step, which is plated with a finger-welded solder exposed on the top (four) cloth step to form a gold-plated/nickel-plated layer. The wiring step is performed by gold plating in the above-mentioned key gold/key, and then processed to form a printed circuit board outer shape and a notch. For a semiconductor package manufactured by the above method (5)
Chip)或 FBGA(Fine Pitch Ball Grid Array,猜細傾斜球狀網 列)板而言,引線接合區域排列於封裝件之中央在引線指狀产Chip) or FBGA (Fine Pitch Ball Grid Array) board, the wire bonding area is arranged in the center of the package in the lead finger production
片進行鍍金所需之鍍金線排列於中央。但县 曰T 一< 如圖二所示,在 6 1333265 上述“狀4片⑽上未塗布其它物質之情況下利用布線方法加 工槽口(3〇)時,上述指狀焊片(20)之鍍金線(1〇)被推動,發生金 屬毛郝G) ’上述金屬毛刺⑽)可能會接近或接觸與半導體芯片 導電連接<焊線’如果與鄰近之指狀焊片接觸 : 干擾,狀短路,導致印觀路板出現不良。 【發明内容】 …本發月正疋為解決上述問題而提出’其目的在;^提供一種 半導封裝用印刷電路板之窗口加工方法,在半導體封裝所使 #用之印刷電路板之製造步驟中,為防止在鐘金/鍵鎳後進行布線 加時41金,,泉向推向上述布線之加工方向之現象,在上述鍵 金/鍍鎳後’姻支持遮罩加工部位的鍍金線,防止發生金屬毛 刺。 【圖式簡單說明】 圖一顯π以往半物封裝用印刷電路板之製造方法之流 程圖。 圖一顯不以往半導體封裝用印刷電路板之製造方法中之 ^ 布線步驟之附圖。 圖-顯不本發明之半導體封裝用印刷電路板之窗 口加工 方法之流程圖。 圖四顯示本發明之半導體封裝用印刷電路板之窗口加工 方法中之遮罩塗布步驟之附圖。 圖玉顯*本發明之轉體封裝用印刷電路板之窗口加工 方法中之遮罩剝離步驟之附圖。 【實施方式】 本發明之半導體封裳用印刷電路板之製造方法可以減少因 去除印刷電路板之引線指狀焊片之鐘金導線及加工與半導體芯 7 1333265 以上說月本發明之有益實 請專所 = 況下’、具有本㈣㈣-賴者料断多種變更實施清 综上所述’本㈣㈣錄德加工方法中存=槽口加 刺之問題’在上述槽口加工部位排列之鍍金線 7止在上述槽口處發生分離,消除因布線加 以成^推祕象,可使上述金屬毛起之電氣干擾最小化, 可以顯著降低印刷電路板之不良率。 【主要元件符號說明】 10 鍍金線 20 指狀烊片 30 槽口 (窗口) 40 金屬毛刺 100 指狀焊片 110 鍍金線 120 遮罩 130 槽口 (窗口) 9The gold-plated wires required for gold plating are arranged in the center. However, the above-mentioned finger-shaped soldering piece (20) is used when the notch (3 〇) is processed by the wiring method in the case where the above-mentioned "four pieces (10) are not coated with other substances, as shown in FIG. ) The gold-plated wire (1〇) is pushed, the metal hair is produced, G) 'The above metal burr (10)) may approach or contact the conductive connection with the semiconductor chip. <Welding wire' if it is in contact with the adjacent finger-shaped solder: Interference, Short-circuited, resulting in poor appearance of the printed circuit board. [Summary of the Invention] ... This is the purpose of solving the above problems. [The purpose is to provide a window processing method for a printed circuit board for semi-conductive packaging, in semiconductor packaging In the manufacturing process of the printed circuit board used for the use of the circuit board, in order to prevent the wiring from being added to the gold after the gold/key nickel, the spring is pushed toward the processing direction of the wiring, and the above-mentioned key gold/plating After the nickel, the marriage supports the gold-plated wire of the mask processing part to prevent the occurrence of metal burrs. [Simple description of the drawing] Fig. 1 shows a flow chart of the manufacturing method of the printed circuit board for the conventional semiconductor package. Printed circuit board BRIEF DESCRIPTION OF THE DRAWINGS FIG. 4 is a flow chart showing a window processing method for a printed circuit board for semiconductor package according to the present invention. FIG. 4 is a view showing a window processing method for a printed circuit board for semiconductor package of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a drawing of a mask peeling step in a window processing method for a printed circuit board for a swivel package of the present invention. [Embodiment] A printed circuit for a semiconductor package of the present invention The manufacturing method of the board can reduce the gold wire of the lead finger-shaped soldering piece for removing the printed circuit board and the processing and semiconductor core 7 1333265. The above-mentioned invention is beneficial to the special office = under the condition ', with this (four) (four)- In the above-mentioned (four) (four) recording processing method, the problem of the spurting of the notch is carried out. The gold-plated wire 7 arranged at the above-mentioned notch processing portion is separated at the above-mentioned notch, and the cloth is eliminated. The wire is used to push the secret image to minimize the electrical interference of the metal hair, which can significantly reduce the defect rate of the printed circuit board. [Main component symbol description] 10 Gold plating 20 finger notch molten sheet 30 (window) 40 of the metal burr 100 bond finger shroud 130 120 110 Plated Wire slot (window) 9
Claims (1)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020050030136A KR100648916B1 (en) | 2005-04-12 | 2005-04-12 | Window processing method of printed circuit board for semiconductor package |
| PCT/KR2006/001354 WO2006109997A1 (en) | 2005-04-12 | 2006-04-12 | Window manufacture method of semiconductor package type printed circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW200816407A TW200816407A (en) | 2008-04-01 |
| TWI333265B true TWI333265B (en) | 2010-11-11 |
Family
ID=37087238
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW095135043A TWI333265B (en) | 2005-04-12 | 2006-09-22 | Window manufacture method of semiconductor package type printed circuit board |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JP4701248B2 (en) |
| KR (1) | KR100648916B1 (en) |
| CN (1) | CN100514612C (en) |
| TW (1) | TWI333265B (en) |
| WO (2) | WO2006109967A2 (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100891334B1 (en) | 2007-05-25 | 2009-03-31 | 삼성전자주식회사 | Circuit board, semiconductor package having same, manufacturing method of circuit board and manufacturing method of semiconductor package |
| TWI334320B (en) | 2007-07-16 | 2010-12-01 | Nanya Technology Corp | Fabricating method of gold finger of circuit board |
| CN101488486B (en) * | 2008-01-15 | 2010-06-02 | 力成科技股份有限公司 | Slot-openable circuit substrate |
| KR100941982B1 (en) * | 2008-04-07 | 2010-02-11 | 삼성전기주식회사 | Board-on-Chip Package Substrate Manufacturing Method |
| CN102480844B (en) * | 2010-11-23 | 2014-05-07 | 深南电路有限公司 | Process for manufacturing diffusion coating prevention PCB (printed circuit board) gold-plated board |
| CN108513433A (en) * | 2018-04-24 | 2018-09-07 | 苏州维信电子有限公司 | A kind of flexible circuit board PAD and its manufacturing method every tin |
| CN114121791A (en) * | 2021-11-25 | 2022-03-01 | 日月光半导体(上海)有限公司 | Integrated circuit device and method of manufacturing the same |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05136327A (en) | 1991-11-12 | 1993-06-01 | Toshiba Corp | Semiconductor package |
| US5281851A (en) | 1992-10-02 | 1994-01-25 | Hewlett-Packard Company | Integrated circuit packaging with reinforced leads |
| JP3415089B2 (en) * | 1999-03-01 | 2003-06-09 | 住友金属鉱山株式会社 | Manufacturing method of printed wiring board |
| JP2001110838A (en) * | 1999-10-07 | 2001-04-20 | Hitachi Chem Co Ltd | Semiconductor device, semiconductor support substrate used therein, and method of manufacturing semiconductor device |
| JP2002299790A (en) * | 2001-03-30 | 2002-10-11 | Ibiden Co Ltd | Router processing method and router processed substrate |
| KR20020085635A (en) * | 2001-05-09 | 2002-11-16 | 주식회사 심텍 | Routing method of the outside of a castle type printed circuit board |
| US7173322B2 (en) * | 2002-03-13 | 2007-02-06 | Mitsui Mining & Smelting Co., Ltd. | COF flexible printed wiring board and method of producing the wiring board |
| KR100617585B1 (en) * | 2004-01-28 | 2006-09-01 | 주식회사 뉴프렉스 | Manufacturing method of flexible printed circuit board |
-
2005
- 2005-04-12 KR KR1020050030136A patent/KR100648916B1/en not_active Expired - Lifetime
-
2006
- 2006-04-10 WO PCT/KR2006/001307 patent/WO2006109967A2/en not_active Ceased
- 2006-04-12 JP JP2007532258A patent/JP4701248B2/en active Active
- 2006-04-12 CN CNB2006800001281A patent/CN100514612C/en active Active
- 2006-04-12 WO PCT/KR2006/001354 patent/WO2006109997A1/en not_active Ceased
- 2006-09-22 TW TW095135043A patent/TWI333265B/en active
Also Published As
| Publication number | Publication date |
|---|---|
| KR100648916B1 (en) | 2006-11-27 |
| KR20060108045A (en) | 2006-10-17 |
| WO2006109997A1 (en) | 2006-10-19 |
| CN1989612A (en) | 2007-06-27 |
| JP4701248B2 (en) | 2011-06-15 |
| CN100514612C (en) | 2009-07-15 |
| JP2008519426A (en) | 2008-06-05 |
| WO2006109967A2 (en) | 2006-10-19 |
| TW200816407A (en) | 2008-04-01 |
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