TWI459527B - Substrate structure for semiconductor component and method of forming same - Google Patents

Description

Method for manufacturing substrate structure for semiconductor components

The present invention relates to a method of fabricating a substrate structure, and more particularly to a method of fabricating a substrate structure for a semiconductor device.

Today's consumer electronic products often need to have light, short and short product characteristics. Therefore, many kinds of electronic products have gradually evolved from the structure of packaging substrates combined with electronic components to the structure of electronic components combined with carrier boards to meet the requirements of light and thin. product demand. At present, most of the consumer electronic products in which the electronic components are combined with the electronic components are used in the field of the light emitting diode (LED) industry and the microelectromechanical electronic device industry.

Referring to Fig. 1, there is shown a cross-sectional view of a conventional substrate structure for a semiconductor device. As shown in the figure, the Taiwan Patent No. I305428 discloses a light-emitting diode device having a ruthenium substrate as a carrier, the device comprising a raft carrier 10 having a receiving groove 100, and the raft carrier 10 An insulating layer 111 is formed on the insulating layer 111, 112, and a reflective layer 12 is formed in the insulating layer 111, 112. An electrode via hole 13 is formed in the germanium carrier 10, and the conductive via 14 is filled in the electrode via hole 13, and A positive and negative electrode regions 151, 152 are formed on the insulating layer 112 to be electrically connected to the conductive material 14 in the electrode via hole 13, and then a light emitting diode chip 16 is placed in the receiving groove 100, and is electrically connected to the positive electrode. The negative electrode regions 151, 152, and finally, the accommodating groove 100 and its periphery are filled with an encapsulant 17 to complete a light emitting diode package structure.

Please refer to FIG. 2, which is a cross-sectional view showing another conventional substrate structure for a semiconductor device. As shown in the figure, in order to reduce the overall package structure volume, the micro-electromechanical device manufacturing company FINEMEMS proposed a wafer-level pressure sensing package structure in the United States in 2005 (publication number US 2006/0185429), the package structure A sensing cavity 201 and a through hole 202 penetrating both surfaces of the substrate 20 are formed in the germanium substrate 20 to directly fabricate the microelectromechanical component 21, such as a pressure sensing element, on the germanium substrate 20, and finally The glass cover 22 is joined to the electromechanical element 21.

However, the light emitting diode package structure and the microcomputer inductance measuring device both need to form a patterned circuit on the germanium substrate or perform an etching process to form a cavity or a blind hole, so it is necessary to form the structure before forming the structures. A photoresist layer is formed on the germanium substrate, and the photoresist layer is generally formed on the germanium substrate by spray coating. The technique uses a special channel design plus a million frequency ultrasonic wave. a mega sonic head to splatter the photoresist on the surface of the ruthenium substrate, but which has the disadvantage that the spray coating machine is expensive; in addition, since the material properties of both the ruthenium substrate 30 and the photoresist 31 are different, and Since the photoresist 31 is in a liquid state, the photoresist 31 is liable to fall off from the oblique side of the groove of the substrate 30 by gravity, resulting in uneven film thickness (as shown in FIG. 3), and it is also impossible to achieve a thick film process at a time. Disadvantages.

Since the spray coating has the aforementioned defects, it is difficult to fabricate when the wiring layer is formed by a pattern plating process or a chamber or a blind hole is formed by a pattern etching process. Therefore, how to avoid the various problems in the above-mentioned prior art, and to propose a method for making the resist layer cover the germanium substrate on average, and the production cost thereof is relatively low, thereby improving the overall reliability, which has become The problem that is currently being solved.

In view of the above-mentioned deficiencies of the prior art, the present invention provides a method for fabricating a substrate structure for a semiconductor device, comprising: providing a substrate having a first recess on a top surface thereof; and a top surface of the substrate and a surface of the first recess Forming a conductive layer; forming a solid resist layer on the conductive layer; patterning the solid resist layer to form a solid resistive opening of the exposed portion of the conductive layer in the first recess; and conducting electricity in the opening of the solid resist layer Forming a patterned metal layer on the layer; removing the solid resist layer; and removing the conductive layer not covered by the metal layer.

The method for fabricating a substrate structure for a semiconductor device according to the present invention includes: providing a substrate having a first recess on a top surface thereof; forming a solid resist layer on a top surface of the substrate and the first recess surface; a solid resist layer for forming an exposed portion of the solid resist layer opening of the substrate in the first recess; removing a portion of the substrate in the solid resist opening to form a substrate recess; and removing the solid resist layer.

As can be seen from the above, the substrate structure for a semiconductor device of the present invention is formed by using a solid resist layer of, for example, parylene as a mask for a subsequent patterned metal layer or a patterned substrate, and the solid resist layer can be protected. The angle coating has no problem of thickness unevenness caused by the flow of the resist layer, so that the resist layer having a large thickness can be easily and quickly obtained; and the manufacturing method of the present invention can be completed by using general equipment, so that the method can be greatly reduced. Cost of production.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "upper", "lower", "top" and "one" are used in the description, and are not intended to limit the scope of the invention. Changes or adjustments to a relationship are considered to be within the scope of the invention, without departing from the scope of the invention.

First embodiment

4A to 4G are cross-sectional views showing a first embodiment of a substrate structure for a semiconductor device and a method of manufacturing the same according to the present invention, wherein the fourth embodiment of Fig. 4A and Fig. 4A are other embodiments of Fig. 4A.

First, as shown in FIGS. 4A, 4A' and 4A", a substrate 40 is provided, the top surface of which has a first recess 400, and the substrate 40 can be made of bismuth material; wherein the first recess 400 can be obtusely concave. a groove, as shown in FIG. 4A; the first groove 400 may be a right-angle groove, as shown in FIG. 4A'; or the bottom surface of the substrate 40 may include a second surface connected to the first groove 400. The groove 401 and the second groove 401 and the bottom of the first groove 400 communicate with each other as shown in Fig. 4A". In the following, the present embodiment will be described with reference only to Fig. 4A. The subsequent operations of the 4A' and 4A" patterns can be applied analogously according to Fig. 4A, and therefore will not be described herein.

As shown in FIG. 4B, a conductive layer 41 is formed on the top surface of the substrate 40 and the surface of the first recess 400. The conductive layer 41 may be formed by sputtering or electroless plating.

As shown in FIG. 4C, a solid resist layer 42 is formed on the conductive layer 41. The solid resist layer 42 may not contain a solvent, and the solid resist layer 42 may be made of parylene. The manner of the solid resist layer 42 may be chemical vapor deposition (CVD).

As shown in FIG. 4D, the solid resist layer 42 is patterned to form a solid resistive opening 420 of the conductive layer 41 in the first recess 400. The solid via opening 420 may be formed as a Shoot and burn.

As shown in FIG. 4E, a patterned metal layer 43 is electroplated on the conductive layer 41 in the solid resistive opening 420.

As shown in FIG. 4F, the solid resist layer 42 is removed, and the solid resist layer 42 is removed by heating the substrate 40 in an environment with oxygen to crack the solid resist layer 42 or remove it. The solid resist layer 42 can be in the form of plasma bombardment.

As shown in FIG. 4G, the conductive layer 41 not covered by the metal layer 43 is removed.

Second embodiment

5A to 5E are cross-sectional views showing a second embodiment of a substrate structure for a semiconductor device and a method of manufacturing the same according to the present invention.

First, as shown in FIG. 5A, a substrate 40 is provided, the top surface of which has a first groove 400, and the substrate 40 can be made of a crucible material; wherein the first groove 400 can be an obtuse groove, as shown in FIG. 5A. The first groove 400 can be a right angle groove (see FIG. 4A'); or the bottom surface of the substrate 40 can include a second groove 401 connected to the first groove 400, and The two grooves 401 and the bottom of the first groove 400 are in communication with each other (please refer to FIG. 4A). Hereinafter, the embodiment will be described with reference to FIG. 5A as a representative, as for the 4A' and 4A" views. Subsequent practices can be applied analogously according to Figure 5A, so they are not described here.

As shown in FIG. 5B, a solid resist layer 42 is formed on the top surface of the substrate 40 and the surface of the first recess 400. The solid resist layer 42 may not contain a solvent, and the material of the solid resist layer 42 may be a poly-pair. The form of the parylene and the solid resist layer 42 may be chemical vapor deposition (CVD).

As shown in FIG. 5C, the solid resist layer 42 is patterned to form an exposed portion of the solid resistive opening 420 of the substrate 40 in the first recess 400. The solid resistive opening 420 may be formed as a laser. Burning.

As shown in FIG. 5D, a portion of the substrate 40 in the solid resistive opening 420 is removed to form the substrate recess 402. The etching process may be continued to remove the substrate 40 in the solid resist opening 420. To form a consistent perforation hole (not shown).

As shown in FIG. 5E, the solid resist layer 42 is removed, and the solid resist layer 42 is removed by heating the substrate 40 in an environment having oxygen to remove the solid resist layer 42 by cleavage, or The manner of removing the solid resist layer 42 may be plasma bombardment.

In summary, the substrate structure for a semiconductor device of the present invention is formed by using a solid resist layer such as parylene as a mask for a subsequent patterned metal layer or a patterned substrate, and the solid resist layer can be coated. Conformal coating, and there is no problem of thickness unevenness caused by the flow of the resist layer; and the manufacturing method of the present invention can be completed by using general equipment, so that the production cost can be greatly reduced.

The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

10. . . Load board

100. . . Locating slot

111,112. . . Insulation

12. . . Reflective layer

13. . . Electrode via

14. . . Conductive material

151,152. . . Positive and negative areas

16. . . Light-emitting diode chip

17. . . Encapsulant

20. . .矽 substrate

201. . . Sensing cavity

202. . . Through hole

twenty one. . . Microelectromechanical components

twenty two. . . Glass cover

30. . . Bismuth substrate

31. . . Photoresist

40. . . Substrate

400. . . First groove

401. . . Second groove

402. . . Substrate recess

41. . . Conductive layer

42. . . Solid state resist

420. . . Solid barrier opening

43. . . Metal layer

1 is a cross-sectional view showing a structure of a substrate for a conventional semiconductor device;

Figure 2 is a cross-sectional view showing another conventional substrate structure for a semiconductor device;

Fig. 3 is a schematic cross-sectional view showing a problem that a substrate structure for a conventional semiconductor device is likely to occur;

4A to 4G are cross-sectional views showing a first embodiment of a substrate structure for a semiconductor device of the present invention and a method for fabricating the same, wherein the fourth embodiment AA and 4A are other embodiments of FIG. 4A;

5A to 5E are cross-sectional views showing a second embodiment of the substrate structure for a semiconductor device of the present invention and a method of manufacturing the same.

40. . . Substrate

400. . . First groove

41. . . Conductive layer

43. . . Metal layer

Claims (20)

A method for fabricating a substrate structure for a semiconductor device, comprising: providing a substrate having a first recess on a top surface thereof; forming a conductive layer on a top surface of the substrate and a surface of the first recess; forming a solid resist on the conductive layer Forming the solid resist layer to form a solid resistive opening of the exposed portion of the conductive layer in the first recess; forming a patterned metal layer on the conductive layer in the solid resistive opening; removing the solid a resist layer; and removing a conductive layer that is not covered by the metal layer. The method of fabricating a substrate structure for a semiconductor device according to claim 1, wherein the first groove is a right angle groove or an obtuse groove. The method of fabricating a substrate structure for a semiconductor device according to claim 1, wherein the bottom surface of the substrate further comprises a second recess connected to the first recess, and the second recess and the first recess The bottoms are connected to each other. The method of fabricating a substrate structure for a semiconductor device according to claim 1, wherein the substrate is made of ruthenium. The method for fabricating a substrate structure for a semiconductor device according to claim 1, wherein the conductive layer is formed by sputtering or electroless plating. The method for producing a substrate structure for a semiconductor device according to claim 1, wherein the solid resist layer does not contain a solvent. The method for fabricating a substrate structure for a semiconductor device according to claim 1, wherein the material of the solid resist layer is polyparaphenylene. The method for fabricating a substrate structure for a semiconductor device according to claim 1, wherein the method of forming the solid resist layer is chemical vapor deposition. The method for fabricating a substrate structure for a semiconductor device according to the first aspect of the invention, wherein the method of forming the opening of the solid resist layer is laser ablation. The method for fabricating a substrate structure for a semiconductor device according to claim 1, wherein the solid resist layer is removed by heat cracking or plasma bombardment. A method for fabricating a substrate structure for a semiconductor device, comprising: providing a substrate having a first recess on a top surface thereof; forming a solid resist layer on a top surface of the substrate and the first recess surface; and patterning the solid resist layer; Forming an exposed portion of the solid resist layer opening of the substrate in the first recess; removing a portion of the substrate in the solid resist opening to form a substrate recess; and removing the solid resist. The method of fabricating a substrate structure for a semiconductor device according to claim 11, wherein the first groove is a right angle groove or an obtuse groove. The method of fabricating a substrate structure for a semiconductor device according to claim 11, wherein the bottom surface of the substrate further comprises a second recess connected to the first recess, and the second recess and the first recess The bottoms are connected to each other. The method of fabricating a substrate structure for a semiconductor device according to claim 11, wherein the substrate is made of tantalum. The method for producing a substrate structure for a semiconductor device according to claim 11, wherein the solid resist layer does not contain a solvent. The method for fabricating a substrate structure for a semiconductor device according to claim 11, wherein the material of the solid resist layer is polyparaphenylene. The method for fabricating a substrate structure for a semiconductor device according to claim 11, wherein the method of forming the solid resist layer is chemical vapor deposition. The method for fabricating a substrate structure for a semiconductor device according to claim 11, wherein the solid via layer opening is formed by laser cauterization. The method for fabricating a substrate structure for a semiconductor device according to claim 11, wherein the solid resist layer is removed by heat cracking or plasma bombardment. The method for fabricating a substrate structure for a semiconductor device according to claim 11, wherein a portion of the substrate in the opening of the solid resist layer is removed to form a recess of the substrate, and the etching process is continued to remove the remaining substrate. Part to form a consistent perforation hole.