1273145 九、發明說明： 【發明所屬之技術領域】 本發明係有關一種於無電鍍線基板的製程，特別是使用一種 無電鍍線基板形成金屬線路層的製程。 【先前技術】 在一半導體封裝的基板上，往往布設了許多由導電線路延伸 出來的電性連結墊，來作為電子訊號以及電源傳輸之用，並且經 常在電性連結墊的外露表面上形成一金屬層，例如是以電鍍的方 式形成一鎳/金(Ni/Au)層，如此便能提供基板與其他導電元件做一 良好的電性耦合，同時也可保護電性連結墊本身免受外界環境影 響而產生氧化的情況。 而習知基板在進行電性連結墊的表面電鍍過程時，必須預先 在此基板的邊料區域上布設許多電鍍線(Plating ba⑽及位於電 锻線與線路跡線（trace)之間做為電性連接之電鑛跡線（p丨咖g trace) ’來當作為電流傳導的途徑，如此才能順利將金屬層命ng 於電性連結墊上。μ#古·、土 ^ ^ 上上返之製私方法，基本上包含了製作與 電性連接的電鍍跡線、製作導電通孔、上拒銲層、拒料兔、"線 電鍍金屬層與移除電鍍線。然而，電鍍導線的設置於開孔、 容易產生所謂的”天線效應”而導致雜訊的干擾，此外使用時 存在亦侷限表Φ線路的布局。 ^踯線的 1273145 為解決上述使用電鍍導線而造成雜訊干擾以及影響線路布局 空間的問題，提出無電鍍線之基板製程。第一圖所示為習知無電 鍍線基板上選擇性鍍金屬線路層的步驟示意圖。參照第一圖，首 先於基板的外層只能先進行晶片面的線路（步驟101)，保留錫球面 的全銅面作為電鍍導通之用。接著，覆蓋並圖案化綠漆於晶片面 的線路上（步驟103)以暴露出部分晶片面的線路。之後，以一般絕 緣乾膜覆蓋錫球面的全銅面以避免後續鎳/金層鍍於其上（步驟 105)。接著，於暴露出部分晶片面的線路上鍍上鎳/金層作為金屬 層（步驟107)。之後，移除錫球面的全銅面上的絕緣乾膜，並以適 當方法形成錫球面的線路（步驟109)。最後，覆蓋並圖案化綠漆於 錫球面的線路上（步驟111)。 上述習知無電鍍線基板製程冗長，無可避免的，需應用多次 微影製程，容易有對位誤差的問題產生。此外，每多一道處理製 程，基板的良率便會降低，導致整體的良率無法提升，增加了製 程的成本。 【發明内容】 有鑑於上述發明背景中，有關無電鍍線基板程序時執行多次 圖案化步驟容易產生對位不良的情況，於此提供一種於無電鍍線 基板上形成金屬線路層之方法，晶片面與錫球面的線路可於形成 金屬線路層前一起形成，減少圖案化步驟的次數並提高良率。 1273145 另一方面，有關無電鍍線基板程序中電鍍鎳/金層的問題，於 此提供一種無電鍍線設計基板上形成金屬線路層的方法，利用導 電感光乾膜作為電鍍時電流傳導的媒介。 根據上述之目的，根據本發明'之一實施例，提供一種無電鍍 線設計基板上形成金屬線路層的方法：基板上下表面已形成兩線 路層；一圖案化導電感光乾膜於每一線路層上，其暴露出部分的 線路層；以及藉由圖案化導電感光乾膜傳導電流以電鍍一金屬層 於暴格出的線路層上。 【實施方式】 接下來是本發明的詳細說明，下述說明中對電鍍過程以及基 板本身之描述並不包括詳細的構造組成以及運作原理的完整描 述。本發明所沿用的現有技藝，在此僅作重點式的引用，以助本 發明的闡述。而且下述内文中相關之圖示亦並未依據實際比例繪 製’其作用僅在表達出本發明之特徵。 依據本發明之一較佳具體實施例係提供一種於無電鍍線設計 基板上开^成金屬線路層之方法。首先參照第二A圖所示之剖面結 構不意圖以及第三A圖所示之上視圖（第二a圖係第三A圖中沿剖 面線2A所得到之剖面結構），基板201的上下表面以適當的方法 製作出晶片面（chip side)線路層203與錫球面（ball side)線路層 2〇4 ’晶片面線路層203與錫球面線路層204並無布設一電鍍導 1273145 梟 線。於一實施例中，基板201内部係由許多絕緣層（圖中未示）與 線路層（圖中未示）疊置之組合，並且可包含若干個導通孔（pTH)或 者盲孔（blind via)之結構。絕緣層可由有機材質例如纖維強化 (fiber-reinforced)有機材質、顆粒強化（particle-reinforced)有機材 質等所構成。晶片面線路層203與錫球面線路層204，可以壓合 一金屬導電層（例如一銅層）於基板201上，利用餘刻等方式移除 部分金屬導電層以形成一圖案化之導電線路與電性連結塾。換句 話說，本實施例中之晶片面線路層203或錫球面線路層204包含 一般的導電跡線(trace)、各種尺寸的連接墊（pad)與金手指區域。 之後，於已形成晶片面線路層2〇3與錫球面線路層204的基 板201上下表面先覆蓋一層導電感光乾膜205，以作為進行電鍍 程序時各線路間能有一電流傳導的途徑。於本實施例中所使用的 導電感光乾膜205同時具備，，導電”以及”感光，，兩項特性，所以除了 能做為電鑛時線路間電流傳導的途徑外’本身也可與光阻一樣且 有圖案轉移的功能。根據本發明之一實施例，晶片面線路層2〇3 與錫球面線路層204上所欲形成金屬線路層的位置上可藉由導電 感光乾膜205直接執行曝光以及顯影等程序，移除覆蓋於其上的 部分導電感光乾膜205，暴露出部分晶片面線路層203與錫球面 線路層204表面，如第二B圖以及第三B圖（第二b圖係第三B 圖中沿剖面線2B所得到之剖面結構)所示。 1273145 • 根據上述，習知要在光阻層與導電膜内形成相同圖案化開孔 而而要進行二次對位的複雜步驟，則可依據本發明而簡化了電鍍 刖的程序，並且只需經由一次曝光以及顯影程序後即可讓晶片面 線路層203與錫球面線路層204欲形成金屬線路層之區域的表面 得以暴露。 ^1273145 IX. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to a process for forming an electroless plating substrate, and more particularly to a process for forming a metal wiring layer using an electroless plating substrate. [Prior Art] On a semiconductor package substrate, a plurality of electrical connection pads extending from the conductive lines are often disposed for use as electronic signals and power transmission, and often formed on the exposed surface of the electrical connection pads. The metal layer, for example, is formed by electroplating a nickel/gold (Ni/Au) layer, so that the substrate can be electrically coupled with other conductive elements, and the electrical connection pad itself can be protected from the outside. Oxidation caused by environmental influences. In the conventional substrate, in the surface plating process of the electrical connection pad, a plurality of plating lines (Plating ba (10) and between the electric forging line and the trace line) must be disposed in advance on the edge material region of the substrate. The electrical connection trace of the sexual connection (p丨g g trace) is used as a way of current conduction, so that the metal layer can be smoothly ng on the electrical connection pad. μ#古·,土 ^ ^ The private method basically consists of making electroplated traces, making conductive vias, solder resist layers, rejecting rabbits, "line plating metal layers and removing plating lines. However, the plating wires are disposed on Opening the hole, it is easy to produce the so-called "antenna effect" and cause noise interference. In addition, there is also a limitation on the layout of the line Φ. ^1271145 of the 踯 line to solve the above-mentioned use of the electroplated wire causes noise interference and affects the line layout The problem of space is to propose a substrate process for electroless plating. The first figure shows a schematic diagram of the steps of selectively plating a metal circuit layer on a conventional electroless plating substrate. Referring to the first figure, first only the outer layer of the substrate First, the wafer surface is routed (step 101), and the full copper surface of the solder sphere is retained for electroplating conduction. Then, the green lacquer is covered and patterned on the wafer surface (step 103) to expose portions of the wafer surface. Thereafter, the entire copper surface of the tin sphere is covered with a general insulating dry film to prevent subsequent nickel/gold layers from being plated thereon (step 105). Next, a nickel/gold layer is plated on the line exposing part of the wafer surface as a metal. a layer (step 107). Thereafter, the insulating dry film on the full copper surface of the tin sphere is removed, and a solder sphere line is formed in an appropriate manner (step 109). Finally, the green paint is covered and patterned on the tin sphere line. (Step 111) The above-mentioned conventional electroless plating substrate process is tedious and unavoidable, and it is necessary to apply a plurality of lithography processes, which is easy to have a problem of alignment error. In addition, for each processing process, the yield of the substrate is improved. The result is that the overall yield cannot be increased, and the cost of the process is increased. SUMMARY OF THE INVENTION In view of the above invention, it is easy to generate a plurality of patterning steps when the electroless plating substrate program is executed. In the case of a poor position, a method of forming a metal wiring layer on an electroless plating substrate is provided. The wiring between the wafer surface and the tin spherical surface can be formed together before the formation of the metal wiring layer, reducing the number of patterning steps and improving the yield. 1273145 On the other hand, regarding the problem of electroplating a nickel/gold layer in an electroless plating substrate process, there is provided a method of forming a metal wiring layer on an electroless plating design substrate, using a conductive photosensitive dry film as a medium for current conduction during electroplating. According to the above object, according to one embodiment of the present invention, there is provided a method for forming a metal wiring layer on an electroless plating design substrate: two circuit layers have been formed on the upper and lower surfaces of the substrate; and a patterned conductive photosensitive dry film is disposed on each circuit layer. And exposing a portion of the wiring layer; and conducting current through the patterned conductive photosensitive dry film to plate a metal layer on the turbulent wiring layer. [Embodiment] The following is a detailed description of the present invention, and the description of the electroplating process and the substrate itself in the following description does not include a detailed description of the detailed constitution and operation principle. The prior art to which the present invention pertains is hereby incorporated by reference in its entirety to the extent of the disclosure. Further, the related drawings in the following texts are not drawn on the basis of actual scales, and their effects are merely indicative of the features of the present invention. According to a preferred embodiment of the present invention, there is provided a method of opening a metal wiring layer on an electroless plating design substrate. Referring first to the cross-sectional structure shown in FIG. 2A and the top view shown in FIG. 3A (the cross-sectional structure obtained along the hatching 2A in the second a-picture in FIG. 3A), the upper and lower surfaces of the substrate 201 are referred to. The chip side circuit layer 203 and the ball side circuit layer 2 4' are formed by an appropriate method. The wafer surface wiring layer 203 and the tin spherical surface layer 204 are not provided with a plating guide 1273145. In one embodiment, the inside of the substrate 201 is a combination of a plurality of insulating layers (not shown) and a wiring layer (not shown), and may include a plurality of vias (pTH) or blind vias. ) structure. The insulating layer may be composed of an organic material such as a fiber-reinforced organic material or a particle-reinforced organic material. The wafer surface layer 203 and the tin spherical layer 204 may be pressed onto a substrate 201 by a metal conductive layer (for example, a copper layer), and a portion of the metal conductive layer may be removed by a etch or the like to form a patterned conductive line and Electrical connection 塾. In other words, the wafer surface wiring layer 203 or the tin spherical wiring layer 204 in this embodiment includes a general conductive trace, a pad of various sizes, and a gold finger region. Thereafter, the upper and lower surfaces of the substrate 201 on which the wafer surface wiring layer 2〇3 and the tin spherical wiring layer 204 have been formed are first covered with a conductive photosensitive dry film 205 as a means for conducting current conduction between the lines during the plating process. The conductive photosensitive dry film 205 used in the present embodiment has both, conductive, and "photosensitive" characteristics, so that in addition to being able to conduct current conduction between lines during electric ore, it is also compatible with the photoresist. Same and with the function of pattern transfer. According to an embodiment of the present invention, the position of the metal line layer on the wafer surface layer 2〇3 and the solder ball line layer 204 can be directly performed by the conductive photosensitive dry film 205, and the process of exposure and development is performed to remove the cover. a portion of the conductive photosensitive dry film 205 thereon exposes a portion of the surface of the wafer surface layer 203 and the surface of the solder ball layer 204, as shown in the second B and third B drawings (the second b pattern is in the third B diagram) The cross-sectional structure obtained by line 2B is shown. 1273145 • According to the above, a complicated step of forming the same patterned opening in the photoresist layer and the conductive film to perform secondary alignment is simplified according to the present invention, and only The surface of the wafer surface wiring layer 203 and the region of the tin spherical wiring layer 204 where the metal wiring layer is to be formed can be exposed after one exposure and development process. ^
接著參照第二C圖以及第三C圖（第二C 间1乐第三C圖中沿 ^面線2C所得到之剖面結構），在基板2〇1上 ^ 心订一電鍍程序， 使得被導電感光乾膜2〇5暴露出的晶片面線路的^ 興錫球面線 路層2〇4形成—金屬層2G7。本實施例所提供之導電感光乾膜205 於^電鍍程序中提供電流傳導的雜，其可以於表面為絕緣、但 内。卩為導電材料或是導電材料被分散於絕緣本體中，但本發明不Referring to the second C-picture and the third C-picture (the cross-sectional structure obtained along the surface line 2C in the second C-lean, the third C-picture, the electroplating process is performed on the substrate 2〇1, so that The surface layer 2〇4 of the wafer surface line exposed by the conductive photosensitive dry film 2〇5 forms a metal layer 2G7. The conductive photosensitive dry film 205 provided in this embodiment provides current-conducting impurities in the electroplating process, which may be insulated on the surface. The conductive material or the conductive material is dispersed in the insulating body, but the present invention does not
I 限於上述。再者，在本實施例中，此金脣層207係為一鎳/金層， 但其他金屬及其組合例如金、鎳、鈀、銀、錫、鎳/鈀、鉻/鈦、鈀 /金以及鎳/把/金等也可依據本發明而具體實施。 之後，以適當的方法將導電感光乾膜205自基板2〇1表面移 除。之後再於晶片面線路層203與錫球面線路層204表面覆蓋一 字:. "拒i于層（solder mask)209，例如綠漆，藉其開口而暴露出 4刀金屬層207，如第二D圖與第三D圖（第二D圖係第三D圖 面線2D所得到之剖面結構)所示。於一實施例中，拒銲層 依據貫際需要以形成圖案化的開孔以產生不同種類的電性連 彳】如可控制拒銲層209開孔的範圍而僅讓部分金屬層207 1273145 表面暴露出來而形成一拒鮮層定義SMD(solder mask defined)形 式的電性連結墊211 ;或者控制拒銲層209開孔的範圍使得大部 份金屬層207表面以及部份基板201表面暴露出來，形成一非拒 銲層定義NSMD(non-solder mask defined)形式的電性連結墊 213 ;或者形成導電手指形式的電性連結墊215。 【圖式簡單說明】 第一圖係習知選擇性鍍金屬線路層基板製程的流程示意圖； 第二A圖至第二D圖係依據本發明之一較佳具體實施例說明 一種無電鍍線基板形成金屬棒路層製程的剖面示意圖；以及 第三A圖至第三D圖係依據本發明之一較佳具體實施例說明 一種無電鍍線基板形成金屬線路層製程的上視圖。 【主要元件符號說明】 101、103、105、107、109、111 步驟 201 基板 203 晶片面線路層 204 錫球面線路層 205 導電感光乾膜 207 金屬層 209 拒銲層 211 拒銲層定義形式之導電連結墊 213 非拒銲層定義形式之導電連接墊 導電手指 215I is limited to the above. Furthermore, in the present embodiment, the gold lip layer 207 is a nickel/gold layer, but other metals and combinations thereof such as gold, nickel, palladium, silver, tin, nickel/palladium, chromium/titanium, palladium/gold And nickel/handle/gold, etc. can also be embodied in accordance with the present invention. Thereafter, the conductive photosensitive dry film 205 is removed from the surface of the substrate 2〇1 by an appropriate method. Then, the surface of the wafer surface layer 203 and the tin spherical layer 204 are covered with a word: "solder mask 209, such as green lacquer, by which the 4-knife metal layer 207 is exposed, such as The two D map and the third D map (the second D graph is the cross-sectional structure obtained by the third D graph line 2D). In one embodiment, the solder resist layer is formed according to a continuous need to form patterned openings to produce different kinds of electrical ports. For example, the range of openings of the solder resist layer 209 can be controlled to allow only a portion of the metal layer 207 1273145 surface. Exposed to form a solder joint 211 in the form of a solder mask defined in the form of a solder mask; or to control the opening of the solder resist layer 209 such that the surface of the majority of the metal layer 207 and the surface of the portion of the substrate 201 are exposed. Forming a non-resistive solder layer defining an electrical connection pad 213 in the form of a non-solder mask defined; or forming an electrical connection pad 215 in the form of a conductive finger. BRIEF DESCRIPTION OF THE DRAWINGS The first drawing is a schematic flow chart of a conventional selective metallization circuit layer substrate process; the second A to second D drawings illustrate an electroless plating substrate according to a preferred embodiment of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 3 is a cross-sectional view showing a process of forming a metal wiring layer in an electroless plating substrate according to a preferred embodiment of the present invention. [Main component symbol description] 101, 103, 105, 107, 109, 111 Step 201 Substrate 203 Wafer surface wiring layer 204 Tin spherical wiring layer 205 Conductive photosensitive dry film 207 Metal layer 209 Solder resist layer 211 Conductive layer defined form of conductive Bonding pad 213 non-resistive soldering layer defined form of conductive connection pad conductive finger 215