1306294 •九、發明說明： 【發明所屬之技術領域】 本發明係關於-種半導體製程’尤指—種應用於半 體封裝件之基板結構及其製法。 【先前技術】 對於以基板作為晶片承載件的球栅陣列 Array’ BGA)半導體封裝件而言，其訊號傳輸設計往往係藉 ♦ 土板之„又计，而將晶片之訊號透過銲線傳遞至基板上之 銲指(Finger)，再藉由基板之導電貫孔(Via)傳遞至基板底 面的‘球墊（Bali pad)，以透過植設於該輝球塾上之鋒_ =進而傳遞至外界，同時為提升及維持封裝件之電性功 能，亦需在該基板上設置電源環（叩町Hng)及接地環 ^L0^ndring)’以供晶片透過鲜線電性搞合至該電源環及 接地裱，如美國專利US5,58M22所揭示者。 该基板之輝指、銲球墊、電源環及接地環—般 ^銅^質’而為提供鲜線或鲜球與該基板之電源環、接地 二It,:求墊良好接著，同時保護該電源環、接地環、 免受外在環境污染，料即須在該電源 ㈣、料及銲球録面覆蓋—鎳金層（N1/Au)。 然而，傳統形成錄金層之製法缺點在於 須額外佈設多數電铲導錄，ιν— 板之表面必 此，對於-户 x 進行電鍍鎳金層之步驟丨因 畔。此外1 板’此種設計即有基板面積不足之缺 -^(antennae；lc〇；：；^ 有雜訊之產生，亦將干擾訊號 19593 5 1306294 之傳輸；故而此類結構已漸不符今日產品所需。 為解决此一問題，業界遂發展出兩種不需電鍍導線的 基板衣法，包括選擇性電鍍（SelectedG〇ld，sg)製法及鉦 電鍍線鍍鎳金（NonPlatingLine，帆）製法，以下即分^ 其製法流程與所形成的基板結構。 對SG製法而言，其係先如第u圖所示，於基板怒層 10上形成銅|(C；uF◦⑴u，再如第ΐβ_，利用光阻層κ 銅層11上疋義出如電源環、接地環、銲指及銲球墊 f電性連接部之開n12G位置；接著，如第lcs，於該此 開口 120中鍍上錄金層13’此鍊金層13之電鑛面 該光阻層12之開口 120面積相同；再如第1D圖， 且層12’然後’如第1E圖，圖案化該銅層心 =如導電跡線、電源環、接地環、銲指及銲球塾等之電 丨連，部uo,並敷設拒銲層14，而令該拒㈣14之一 •該拒St已=面層積， _ f 14之開口 14〇面積係略小於該錄金層13之面 積亦即該拒銲層14係覆蓋住部分 ⑴上之鎳金層13周圍。 成於為電!·生連接部 珂製法 μ ^ ^ ' Α圖所示，先於基板芯 層2〇上形成銅層21，再如第2β圖 取、 程而圖荦化嗲钯岸2丨，* —莫， 和用4知曝光顯影製 口木化該銅層21，並定義出如電 及銲球墊等電性連接部21〇 ;接著，:、 ％、銲指 如利用無電解電鍍之薄銅層25 „圖，覆盍-例 層U，以利用該光阻層22之開口 ^圖，形成光阻 又義出該電性連接 19593 1306294 =二中預定鍍上錄金層之區域;接著，如m錢上 層2=並如第㈣，移除該光阻層22並钱刻掉該薄 銅層25，·最後，如第2GW，敷設拒銲層& 層24之開口 240外露出該電性連接部21〇之錄金層t 惟習知上由於形成拒銲層之開口有對位土 f艮制，且該拒銲層之解析度誤差有約咖“，因此，今 錄金層之大小需略大於該拒銲層開口之大小，兩者間有^ _m(75/zra+5Mm)的重疊區域l(如第％圖所示）。 ，此-習知製法雖可免除電鑛導線之設計，改 ::了性問題，然而’此二製法所形成之基板結構卻另有 此因拒銲層與錄金層間的附著性並不佳， 八對於基板上相鄰設置之f源環及接_而言， 圖所示’其中該第祁及％圖係為對該第^ 基板表面之拒鮮層34龜 置電原衣361及接地環362上表面錄金層3 二=露出該電源環361及接地環362上表面鎳二兩扣 、邰刀，其中位於該電源環361及接地環36〇 = 34:部分(如第3B圖所示)，因其兩邊均係各別= 二源％ 361及接地環362之錦金層33上 自該鎳金層33卜矣丨丨她 ^ , c很合易 θ 上釗離，產生脫層現象，形成不良品。 或電:=::==?〜連接部’尤為接地環 題，覆盍其上之拒銲層間產生脫層問 戶、為+¥體相關領域中所亟待解決之課題。 【發明内容】 19593 7 1306294 於接^絲有鐘於前述及其他缺點，本發明之主要目的在 板結構2 =錄金層與覆蓋其上之拒鮮層產生脫層之基 發月的又—目的在於提供—種可強化錄金層與覆 之拒銲層接合力之基板結#及其製法。 制法為述及其他目的’本發明所提出的基板結構之 二’'包括：製備-芯層’該芯層表面形成有圖案化之 二一結構’且該線路結構中包含有導電環；於該芯層上覆 ^阻層’、其巾該阻層係覆蓋住線路結構部分區域及導電 %部分區域，以顯露出該線路結構部分區域及導電環部分 區域’進而定義出預定鑛設區域；於該預定鑛設區域上形 成鎳金層；移除該阻層，以外露出未形成有錄金層之部^ 線^吉構及部分導電環；以及於該芯層上覆蓋拒銲層，並 外露出該線路結構及導電環之鎳金層。 、透過前述製法所製得之基板結構，即包括：怒層；形 ，於該芯層上之圖案化線路結構，該線路結構包含有導電 裒、錄金層係元成於该線路結構部分區域及導電環部分 區域上；以及拒輝層’係敷設於該芯層及線路結構上，且 外露出該線路結構及導電環上之鎳金層，其中該拒銲層係 覆蓋該線路結構及導電環中未形成有鎳金層之區域/、 因此，相較習知製程中在例如電源環及接地環等導 環上全面鐘覆錄金層之方式，本發明即在該原本須完全錄 錄金層之導電環上’利用阻層留下至少一個區域未進行錢 設鎳金層’於外露出該阻層之導電環上鑛設鎳金層，接著 8 19593 .1306294 •移除該阻層，以形成部分區域鍍㈣金層及部分區域未錢 有=層之導電環’之後再於芯層及導電環未鐘設鎳金層 fπ分區域上敷設拒銲層，俾利用拒銲層與銅材質之導電 f本體的結合力大於拒銲層對形成於導電環上鎳金層的結 口力，避免拒銲層與鎳金層間產生脫層問題，改善基板結 構之品質。 ' ° 【實施方式】 .、以下係藉由特定的具體實例說明本發明之實施方 式，热悉此技藝之人士可由本說明書所揭示之内容輕易地 瞭解本發明之其他優點與功效。 、請參閱第4Α至4Η圖，係為本發明之基板結構及其製 法之示思圖，如第4Α及4Β圖所示，其中該第4Β圖係為對 應第4Α圖之剖面圖，首先，製備一芯層4〇，該芯層4〇可 為樹脂，該芯層40表面形成有圖案化之線路結構41，且 該線路結構41中包含有導電環411及其它導電跡線412 ^及如墊413，其中，該導電環411係例如為電源環及接地 環等，且該線路結構41之導電環411、導電跡線412及銲 塾413之材質係為金屬銅’接著利用如NpL製法於其上覆 盒一無電解電錢之薄銅層（未圖示）。 如第4C及4D圖所示，其中該第4D圖係為對應第4C 圖之剖面圖’於該芯層40上之薄銅層上覆蓋一阻層42 , 其中該阻層42係覆蓋住線路結構41部分區域（如導電跡線 412)及導電環411部分區域，並顯露出該線路結構41部分 區域（如銲墊413)及導電環411部分區域，以定義出預^ 19593 9 -1306294 錢設區域。 ，第犯及4F圖所示，其中該第4F圖係為對應第4£ f之。li面圖’於該預定鑛設區域上形成鎳金層，1中係於 未為該阻層42所覆蓋之導電環411部分區域及鲜塾413 2 = 一鎳二層Λ接著即可移除該阻層42,並㈣ 外露出未形成㈣金層43之部分線路結構 (如導電跡線412)及部分導電環411。 =第4G及4H圖所示，其中該第4H圖係為對應第仏 ，面圖，之後於該芯層4〇上覆蓋拒鮮層44，並外露 =該線路結構（如銲墊413)及導電環411之錄金層Μ，其 j於該導電環411而言，部分區域係形成有錄金層… 區域則未敷設錄金層，如此於形成該拒銲層軻時，該 f銲層44將覆蓋至該導電環411 i未設有鍊金層“之區 域，俾透過該拒銲層44與導電環411本體（銅材質）之結合 2於與錄金層43之結合度，使該拒銲層44不易自該錄 I金層4 3上剝離。 透過前述製法，本發明亦揭示—種基板結構，係包 括：芯層40;形成於該芯層4〇上之圖案化線路結構41， ^線路結構41包含有導電環411 ;驗層43，係形成於該 線路結構41及導電環411之部分區域上；以及拒銲層以， 係敷設於該芯層4G及線路結構41上，且外露出該線路結 =41及導電環411上之鎳金層43,其中該拒銲層44係覆 盖该導電環411中未形成有鎳金層43之區域。另該線路結 構41復包含有導電跡線412及銲墊413，其中該導電環 19593 10 1306294 :411^導電跡線412、及銲墊413之材質為金屬銅，且該導 電環411部分區域及銲墊413上係形成有鎳金層。 因此，相較習知製程中在例如電源環及接地環等導電 環上全面鍍覆鎳金層之方式，本發明即在該原本須完全錢 錄金層之導電環上，利用阻層留下至少_個區塊未進行^ f鎳金層’以於外露出該阻層之導電環上鍍設錄金層，接 著移除該阻層，以形成部分區域鍍有錦金層及部分區域未 鑛有錄金層之導電環’之後再於芯層及導電環未錢設錄金 層之部分區域上敷設拒銲層，俾利用拒銲層與銅材質之導 電環本體的結合力大於拒輝層對形成於導電環上錄金層的 結合力，避免拒銲層自該鎳金層上發生剝離問題，改善基 板結構之品質。 ^ 土 以上所述僅為本發明之較佳實施方式而已，並非用以 限疋本發明之範圍，亦即，本發明事實上仍可做其他改變， 因此，舉凡熟習該項技術者在未脫離本發明所揭示之精神 鲁與技術思想下所完成之一切等效修飾或改變，仍應由後述 之申請專利範圍所涵蓋。 【圖式簡單說明】 第1Α至1Ε圖係習知之選擇性電鍍（Selected Gold， SG)製法之示意圖； 第2A至2G圖係習知之無電鍍線鍍鎳金（N〇n piating Line，NPL)製法之示意圖； 第3A至3C圖係習知之基板結構中電源環及接地環區 域示意圖；以及 11 19593 .1306294 :第4A至4H圖係本發明之基板結構及其製法示意圖。 【主要元件符號說明】 10 芯層 11 銅層 110 電性連接部 12 光阻層 120 開口 13 鎳金層 14 拒鲜層 140 開口 20 芯層 21 銅層 210 電性連接部 22 光阻層 220 開口 23 錄金層 24 拒銲層 240 開口 25 薄銅層 33 鎳金層 34, 34， 拒鲜層 361 電源環 362 接地環 40 芯層 12 19593 1306294 ；41 線路結構 411 導電環 412 導電跡線 413 銲墊 42 阻層 43 鎳金層 44 拒銲層1306294 • Nine, invention description: [Technical field to which the invention pertains] The present invention relates to a semiconductor process, particularly a substrate structure applied to a semiconductor package and a method of fabricating the same. [Prior Art] For a ball grid array Array' BGA semiconductor package with a substrate as a wafer carrier, the signal transmission design is often transmitted through the bonding wire to the signal of the chip. The finger on the substrate is transferred to the 'Bali pad' on the bottom surface of the substrate through the conductive via (Via) of the substrate to pass through the front edge _ = implanted on the radiant raft In the outside world, in order to improve and maintain the electrical function of the package, it is also necessary to provide a power supply ring (Higcho Hng) and a grounding ring ^L0^ndring) on the substrate for the chip to be electrically connected to the power supply through the fresh wire. Ring and grounding 裱, as disclosed in U.S. Patent No. 5,58M22. The substrate of the substrate, the solder ball pad, the power ring and the grounding ring are generally used to provide a fresh wire or a fresh ball and a power source for the substrate. Ring, grounding two It,: the mat is good, then protect the power ring, grounding ring, from external environmental pollution, the material must be covered in the power (four), material and solder ball recording surface - nickel gold layer (N1/Au However, the traditional method of forming a gold layer is that it requires additional layout. The number of electric shovel guides, ιν—the surface of the board must be the same. For the household x, the step of electroplating the nickel-gold layer is carried out. In addition, the 1 board's design has the shortage of the substrate area-^(antennae;lc〇 ;:;^ The generation of noise will also interfere with the transmission of signal 19593 5 1306294; therefore, such structures have become less desirable for today's products. To solve this problem, the industry has developed two substrates that do not require plating wires. The clothing method, including the selective plating (Selected G〇ld, sg) method and the 钲 plating line nickel-plated gold (NonPlatingLine, sail) method, the following is the process and the formed substrate structure. For the SG system, First, as shown in Fig. u, copper|(C; uF◦(1)u, and then ΐβ_ is formed on the substrate anger layer 10, and the photoresist layer κ copper layer 11 is used for the power supply ring, the grounding ring, and the soldering. And the opening n12G position of the electrical connection portion of the solder ball pad f; then, as in the lcs, the opening 120 is plated with the gold layer 13' of the gold ore layer of the gold layer 13 and the opening of the photoresist layer 12 120 is the same area; again as in Figure 1D, and layer 12' then 'as shown in Figure 1E, patterning the copper Layer core = such as conductive traces, power ring, grounding ring, welding fingers and solder balls, etc., uo, and the solder resist layer 14 is laid, and one of the rejects (four) 14 • the reject St = face The area of the opening 14 层 of the layer _ f 14 is slightly smaller than the area of the gold layer 13 , that is, the solder resist layer 14 covers the periphery of the nickel gold layer 13 on the portion ( 1 ). The tantalum method μ ^ ^ ' Α , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Exposing and developing the mouth to wood the copper layer 21, and defining electrical connection portions 21 such as electricity and solder ball pads; then,:, %, welding fingers such as a thin copper layer 25 using electroless plating盍-Example layer U, in order to utilize the opening of the photoresist layer 22, to form a photoresist and to define the electrical connection 19593 1306294 = the area in which the gold layer is predetermined to be plated; then, as m m upper layer 2 = And as in the fourth (4), the photoresist layer 22 is removed and the thin copper layer 25 is removed. Finally, as in the second GW, the opening 240 of the solder resist layer & layer 24 is exposed to expose the electrical connection portion 21 Gold layer t It is known that since the opening of the solder resist layer is formed with the alignment soil, and the resolution error of the solder resist layer is about ", the size of the current gold layer needs to be slightly larger than the size of the opening of the solder resist layer. There is an overlap area l of ^ _m (75/zra + 5Mm) between the two (as shown in the % view). Although the conventional method can eliminate the design of the electric ore wire, it changes:: the problem of the problem, however, the substrate structure formed by the second method has another reason because the adhesion between the solder resist layer and the gold layer is not good. 8. For the source ring and the connection _ which are disposed adjacent to each other on the substrate, the figure is shown in the figure, where the third and % diagrams are the anti-friction layer 34 of the surface of the substrate, and the grounding 361 and grounding The gold layer 3 on the upper surface of the ring 362 is exposed to expose the upper surface of the power ring 361 and the grounding ring 362, and the knives are located in the power ring 361 and the grounding ring 36 〇 = 34: (as shown in Fig. 3B) Show), because both sides are different = two source % 361 and the grounding ring 362 of the gold layer 33 from the nickel gold layer 33 divination ^ ^, c is easy to θ on the detachment, resulting in delamination Phenomenon, forming a defective product. Or the electric: =::==?~ The connecting portion is particularly a grounding ring problem, and the problem of delamination between the solder resist layers on the surface is covered, and the problem to be solved in the field of +¥ body is urgently solved. SUMMARY OF THE INVENTION 19593 7 1306294 In the above-mentioned and other shortcomings, the main purpose of the present invention is in the board structure 2 = the gold layer and the anti-fresh layer covering the delamination layer The purpose is to provide a substrate junction # which can strengthen the bonding force between the gold plating layer and the solder resist layer, and a method for preparing the same. The method for the preparation of the present invention is as follows: 'The second structure of the substrate structure proposed by the present invention' includes: preparing a core layer, the surface of the core layer is formed with a patterned two-structure> and the circuit structure comprises a conductive ring; The core layer is covered with a resist layer, and the resist layer covers a portion of the line structure portion and a portion of the conductive portion to expose a portion of the line structure portion and a portion of the conductive ring portion to define a predetermined mineralized region; Forming a nickel-gold layer on the predetermined mineral-bearing region; removing the resist layer, exposing a portion of the metal layer and a portion of the conductive ring that are not formed with the gold-plated layer; and covering the core layer with the solder resist layer, and The nickel structure of the wiring structure and the conductive ring is exposed. The substrate structure obtained by the foregoing method comprises: a anger layer; a patterned circuit structure on the core layer, the circuit structure comprises a conductive raft, and a gold layer is formed in a part of the circuit structure. And a portion of the conductive ring; and a refractory layer is disposed on the core layer and the wiring structure, and exposing the nickel structure layer on the circuit structure and the conductive ring, wherein the solder resist layer covers the line structure and conductive The region in which no nickel gold layer is formed in the ring/, therefore, the present invention is completely recorded in the conventional method in the manner of comprehensively covering the gold layer on a guide ring such as a power supply ring and a grounding ring. On the conductive ring of the gold layer, the nickel layer is deposited on the conductive ring of the resist layer by using at least one region of the resist layer to remove the nickel-gold layer, and then 8 19593 .1306294 • remove the resist layer a portion of the region is plated with a (four) gold layer and a portion of the region is uncharged with a layer of conductive rings', and then a solder resist layer is applied over the core layer and the conductive ring is not provided with a nickel-gold layer fπ sub-region, and the solder resist layer is utilized. The conductive material of the copper material has a large bonding force Solder-repellent layer formed on the conductive ring port junction strength nickel-gold layer, to avoid delamination problems between the solder-repellent layer and the nickel-gold layer, improving the quality of the substrate structure. The embodiments of the present invention are described by way of specific specific examples, and those skilled in the art can readily appreciate other advantages and effects of the present invention from the disclosure herein. Please refer to Figures 4 to 4, which are diagrams of the substrate structure and the method for manufacturing the same according to the present invention, as shown in Figures 4 and 4, wherein the fourth diagram is a cross-sectional view corresponding to the fourth diagram. First, A core layer 4 is prepared. The core layer 4 is a resin. The surface of the core layer 40 is formed with a patterned line structure 41. The line structure 41 includes a conductive ring 411 and other conductive traces 412. The pad 413, wherein the conductive ring 411 is, for example, a power ring and a grounding ring, and the conductive ring 411, the conductive trace 412, and the pad 413 of the circuit structure 41 are made of metal copper, and then the method of NpL is used. The upper cover is a thin copper layer (not shown) of electroless money. As shown in FIGS. 4C and 4D, wherein the 4D image is a cross-sectional view corresponding to FIG. 4C, a thin copper layer on the core layer 40 is covered with a resist layer 42, wherein the resist layer 42 covers the line. A portion of the structure 41 (such as the conductive trace 412) and a portion of the conductive ring 411, and a portion of the line structure 41 (such as the pad 413) and a portion of the conductive ring 411 are exposed to define the amount of pre-19593 9 -1306294 Set the area. , the first offense and the 4F picture, wherein the 4F picture is corresponding to the 4th f f. The li surface pattern 'forms a nickel-gold layer on the predetermined mineral-bearing region, and the middle portion is in a portion of the conductive ring 411 not covered by the resist layer 42 and the fresh 塾413 2 = a nickel-two layer layer, and then the layer can be removed. The resist layer 42 and (4) expose a portion of the line structure (such as the conductive trace 412) and the portion of the conductive ring 411 where the (four) gold layer 43 is not formed. = 4G and 4H, wherein the 4H is a corresponding 仏, a face view, and then the core layer 4 覆盖 is covered with a repellent layer 44, and exposed = the line structure (such as pad 413) and The gold layer 导电 of the conductive ring 411, wherein the conductive ring 411 is formed with a gold layer in a portion of the conductive ring 411, and the gold layer is not applied to the region, so that the f-weld layer is formed when the solder resist layer is formed. 44 is to cover the region where the conductive ring 411 i is not provided with the gold layer ", and the bonding between the solder resist layer 44 and the body of the conductive ring 411 (copper material) 2 is combined with the gold layer 43 so that the The solder resist layer 44 is not easily peeled off from the recorded gold layer 43. Through the foregoing method, the present invention also discloses a substrate structure including: a core layer 40; a patterned line structure 41 formed on the core layer 4 The wiring structure 41 includes a conductive ring 411; the inspection layer 43 is formed on a portion of the wiring structure 41 and the conductive ring 411; and the solder resist layer is applied to the core layer 4G and the wiring structure 41. And exposing the circuit junction=41 and the nickel-gold layer 43 on the conductive ring 411, wherein the solder resist layer 44 covers the conductive ring 411 and is not formed. a region of the nickel-gold layer 43. The circuit structure 41 further includes a conductive trace 412 and a pad 413, wherein the conductive ring 19593 10 1306294 : 411 ^ the conductive trace 412 and the pad 413 are made of metal copper, and A nickel-gold layer is formed on a portion of the conductive ring 411 and the pad 413. Therefore, the present invention is in a manner of completely plating a nickel-gold layer on a conductive ring such as a power supply ring and a ground ring in a conventional process. The conductive ring of the gold layer originally required to be completely recorded, and the resist layer is used to leave at least one of the blocks without performing a nickel-gold layer to plate a gold layer on the conductive ring from which the resist layer is exposed, and then move In addition to the resist layer, a portion of the region is plated with a gold layer and a portion of the region is not contaminated with a gold-plated conductive ring', and then a solder resist layer is applied over a portion of the core layer and the conductive ring.结合 The bonding force between the solder resist layer and the copper conductive ring body is greater than the bonding force of the light-shielding layer on the gold layer formed on the conductive ring, thereby avoiding the peeling problem of the solder resist layer from the nickel gold layer, and improving the substrate structure. Quality. ^ The above is only a preferred embodiment of the present invention. However, it is not intended to limit the scope of the present invention, that is, the present invention may in fact be modified in other ways, and thus, those skilled in the art can do it without departing from the spirit and technical idea disclosed by the present invention. All equivalent modifications or changes shall be covered by the scope of the patent application described below. [Simplified description of the drawings] Figures 1 to 1 are diagrams of the conventional selective plating method (Selected Gold, SG); Figures 2A to 2G A schematic diagram of a conventional method for preparing a nickel-plated gold (NPL) plating method; 3A to 3C are schematic views of a power supply ring and a grounding ring region in a conventional substrate structure; and 11 19593 .1306294: 4A to 4H is a schematic diagram of the substrate structure of the present invention and its preparation method. [Main component symbol description] 10 core layer 11 copper layer 110 electrical connection portion 12 photoresist layer 120 opening 13 nickel gold layer 14 repellent layer 140 opening 20 core layer 21 copper layer 210 electrical connection portion 22 photoresist layer 220 opening 23 gold layer 24 solder mask 240 opening 25 thin copper layer 33 nickel gold layer 34, 34, anti-friction layer 361 power ring 362 ground ring 40 core layer 12 19593 1306294; 41 line structure 411 conductive ring 412 conductive trace 413 welding Pad 42 resist layer 43 nickel gold layer 44 solder resist layer